TW201906029A - 半導體封裝及其製造方法 - Google Patents

半導體封裝及其製造方法

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Publication number
TW201906029A
TW201906029A TW107122380A TW107122380A TW201906029A TW 201906029 A TW201906029 A TW 201906029A TW 107122380 A TW107122380 A TW 107122380A TW 107122380 A TW107122380 A TW 107122380A TW 201906029 A TW201906029 A TW 201906029A
Authority
TW
Taiwan
Prior art keywords
dielectric layer
layer
via hole
opening
semiconductor package
Prior art date
Application number
TW107122380A
Other languages
English (en)
Other versions
TWI683378B (zh
Inventor
王博漢
郭宏瑞
胡毓祥
Original Assignee
台灣積體電路製造股份有限公司
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Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201906029A publication Critical patent/TW201906029A/zh
Application granted granted Critical
Publication of TWI683378B publication Critical patent/TWI683378B/zh

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Abstract

在一實施例中，一種半導體封裝包含：模製化合物；積體電路晶粒，包封在模製化合物中；穿孔，與積體電路晶粒相鄰；以及重佈線結構，在積體電路晶粒、模製化合物以及穿孔上方，重佈線結構電性連接至積體電路晶粒及穿孔，重佈線結構包含：第一介電層，設置於模製化合物上方；第一導通孔，延伸穿過第一介電層；第二介電層，設置於第一介電層及第一導通孔上方；以及第二導通孔，延伸穿過第二介電層且進入第一導通孔之一部分中，第一導通孔與第二導通孔之間的界面為非平面的。

Description

半導體封裝及其製造方法
半導體產業經歷了快速的發展，此可歸因於不斷提高多種電子組件（例如電晶體、二極體、電阻器、電容器等）的積集度（integration density）。主要地，積集度的改良源自於最小特徵尺寸的迭代減小，其允許更多組件整合於給定區域中。隨著對於縮小電子元件的需求增長，已出現對於更小且更具創造性的半導體晶粒的封裝技術的需求。此類封裝系統之一實例為疊層封裝（Package-on-Package；PoP）技術。在PoP元件中，頂部半導體封裝堆疊於底部半導體封裝之頂部上，以提供高積集度以及高組件密度。一般而言，PoP技術能夠使生產的半導體元件具有增強的功能性以及在印刷電路板（printed circuit board；PCB）上具有小的佔據面積。
以下揭露內容提供用於實施本發明之不同構件的許多不同實施例或實例。下文描述組件及配置之特定實例以簡化本發明。當然，此等組件及配置僅為實例且不意欲為限制性的。舉例而言，在以下描述中，第一構件在第二構件上方或上之形成可包含第一構件及第二構件直接接觸地形成的實施例，且亦可包含額外構件可在第一構件與第二構件之間形成使得第一構件與第二構件可不直接接觸的實施例。另外，本發明可在各種實例中重複參考標號及/或字母。此重複是出於簡單性及清晰性之目的，且本身並不指示所論述之各種實施例及/或設置之間的關係。
另外，諸如「在...下方（beneath）」、「在...下面（below）」、「下部的（lower）」、「在...上方（above）」、「上部的（upper）」及類似者之空間相對術語可在本文中出於簡單描述而使用以描述如圖式中所說明的一個組件或構件關於另一組件或構件之關係。除諸圖中所描繪之定向以外，空間相對術語亦意欲涵蓋元件在使用或操作中之不同定向。設備可以其他方式定向（旋轉90度或處於其他定向），且本文中所使用之空間相對描述詞可同樣相應地進行解釋。
本文中所論述之實施例可在特定技術背景下論述，亦即在重佈線結構中具有堆疊式通孔結構的封裝結構（例如，疊層封裝（PoP）結構），以及形成所述封裝結構之方法。堆疊式通孔結構在本文中用以描述互連不同金屬化圖案的多個（「堆疊」）導通孔，其中所述多個導通孔中之每一者豎直對準（例如，垂直於重佈線結構之主要表面的線延伸穿過多個導通孔中之每一者）。各種實施例可提供形成具有經減少缺陷之堆疊式導通孔的方法，其中減少缺陷例如是在熱循環測試期間減少通孔至通孔的界面處（via-to-via interface）之應力、減少通孔內部及/或相鄰堆疊式通孔之間的金屬氧化物（例如，氧化銅）夾層處之空隙形成以及類似者。舉例而言，各種實施例可提供在相鄰堆疊式通孔之間作為擴散阻擋層（例如，銅擴散）的晶種層。在一些實施例中，晶種層可為包括例如鈦層及銅層的多層結構。另外，堆疊式通孔之間的界面可為非平面的（例如，交錯式），以增強堆疊式通孔結構之整體強度。各種實施例可在無需顯著地增加製造成本的情況下提供此等實施例。
本揭露之教示適用於包含堆疊式導通孔的任何封裝結構。其他實施例預期其他應用，諸如不同封裝類型或不同設置對於閱讀本發明後的本領域中具有通常知識者來說是顯而易見的。應注意，本文中所論述之實施例可不必說明可呈現於結構中之每一組件或構件。舉例而言，諸如當對組件中之一者的論述可充分傳達實施例之態樣時，可自圖式省略多個所述組件。另外，可將本文中所論述之方法實施例論述為以特定次序執行；然而，其他方法實施例可以任何合乎邏輯的次序執行。
圖1至圖23根據一些實施例示出形成第一封裝200的製程期間的中間步驟的剖視圖。第一封裝200亦可被稱作積體扇出型（integrated fan-out；InFO）封裝。圖1至圖23是示出用於形成第一封裝200的第一封裝區域600的橫截面視圖。應瞭解，多個封裝可同時形成於多個封裝區域中。
在圖1中，提供載體基底100，且於載體基底100上形成離形層102。載體基底100可為玻璃載體基底、陶瓷載體基底或類似者。載體基底100可為晶圓，使得多個封裝可同時形成在載體基底100上。離形層102可由聚合物系材料形成，可將其連同載體基底100一起從後續步驟中形成之上覆結構移除。在一些實施例中，離形層102為在加熱時損失其黏著特性之環氧樹脂系熱離形材料，諸如光-熱轉換（light-to-heat-conversion；LTHC）離形塗層。在其他實施例中，離形層102可為在暴露於紫外線（ultra-violet；UV）光時損失其黏著特性之UV黏膠。離形層102可配製為液體且經固化、可為疊層至載體基底100上之疊層膜或可為類似者。離形層102之頂部表面可經平坦化，且可具有高度共面性（coplanarity）。
在圖2中，形成介電層104及金屬化圖案106（有時被稱作重佈層或重佈線）。介電層104形成於離形層102上。介電層104之底部表面可與離形層102之頂部表面接觸。在一些實施例中，介電層104由聚合物，諸如聚苯并噁唑（polybenzoxazole；PBO）、聚醯亞胺、苯并環丁烯（benzocyclobutene；BCB）或類似者形成。在其他實施例中，介電層104由以下各者形成：諸如氮化矽的氮化物；諸如氧化矽、磷矽酸鹽玻璃（phosphosilicate glass；PSG）、硼矽酸鹽玻璃（borosilicate glass；BSG）、摻硼磷矽酸鹽玻璃（boron-doped phosphosilicate glass；BPSG）或類似者的氧化物；或類似者。介電層104可藉由任何可接受的沈積製程形成，諸如旋轉塗佈、化學氣相沈積（chemical vapor deposition；CVD）、層壓（laminating）、類似者或其組合。
金屬化圖案106形成於介電層104上。作為形成金屬化圖案106之實例，於介電層104上方形成晶種層（未示出）。在一些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及在鈦層上方之銅層。可使用例如PVD或類似者形成晶種層。接著在晶種層上形成光阻層，且對光阻層進行圖案化。可藉由旋轉塗佈或類似者形成光阻層，且可將光阻層暴露於光線以用於圖案化。光阻層之圖案對應於金屬化圖案106。對光阻層圖案化形成穿過光阻層之開口，以暴露出晶種層。導電材料形成於光阻層之開口中以及晶種層之暴露部分上。可藉由鍍覆（plating）形成導電材料，鍍覆諸如電鍍（electroplating）或無電鍍（electroless plating），或類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁或類似者。接著，移除光阻層以及其上未形成導電材料之一部分的晶種層。可藉由可接受的灰化或剝離製程移除光阻層，諸如使用氧電漿或類似者。一旦移除光阻層，諸如藉由使用可接受的蝕刻製程（諸如，藉由濕式蝕刻或乾式蝕刻）移除晶種層之暴露部分。晶種層的剩餘部分以及導電材料形成金屬化圖案106。
在圖3中，於金屬化圖案106及介電層104上形成介電層108。在一些實施例中，介電層108由聚合物形成，所述聚合物可為可使用微影罩幕圖案化的感光性材料，諸如PBO、聚醯亞胺、BCB或類似者。在其他實施例中，介電層108由以下各者形成：諸如氮化矽的氮化物；諸如氧化矽、PSG、BSG、BPSG的氧化物；或類似者。可藉由旋轉塗佈、層壓、CVD、類似者或其組合形成介電層108。接著，介電層108經圖案化以形成開口，從而暴露一部分的金屬化圖案106。圖案化可藉由可接受的製程，諸如：當介電層108為感光性材料時，藉由將介電層108暴露於光線；或藉由使用例如是非等向性蝕刻進行蝕刻。
介電層104及介電層108以及金屬化圖案106可稱作背側重佈線結構110。在所示實施例中，背側重佈線結構110包含兩層介電層（亦即介電層104及介電層108）以及一層金屬化圖案106。在其他實施例中，背側重佈線結構110可包含任何數目的介電層、金屬化圖案以及通孔。可藉由重複用於形成金屬化圖案106及介電層108的製程而在背側重佈線結構110中形成一或多個額外的金屬化圖案以及介電層。可在形成金屬化圖案期間藉由在下覆介電層之開口中形成金屬化圖案之晶種層及導電材料而形成通孔（未圖示）。通孔可因此互連且電性耦接各種金屬化圖案。
接著形成穿孔112。作為形成穿孔112之實例，於背側重佈線結構110上方形成晶種層，例如在所示出的介電層108及金屬化圖案106之暴露部分上形成晶種層。在一些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及在鈦層上方之銅層。可使用例如PVD或類似者形成晶種層。在晶種層上形成光阻層且圖案化此光阻層。可藉由旋轉塗佈或類似者形成光阻層，且可將光阻層暴露於光線以用於圖案化。光阻層之圖案對應於穿孔。對光阻層進行圖案化形成穿過光阻層之開口，以暴露出晶種層。於光阻層之開口中以及晶種層之暴露部分上形成導電材料。可藉由鍍覆形成導電材料，鍍覆諸如是電鍍或無電鍍，或類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁或類似者。移除光阻層以及其上未形成導電材料的一部分的晶種層。可藉由諸如使用氧電漿或類似者之可接受的灰化或剝離製程移除光阻層。一旦移除光阻層，諸如藉由使用可接受的蝕刻製程（諸如，藉由濕式蝕刻或乾式蝕刻）移除晶種層之暴露部分。晶種層的剩餘部分以及導電材料形成穿孔112。
在圖4中，藉由黏著劑116將積體電路晶粒114黏附至介電層108。在所示實施例中，一個積體電路晶粒114黏附於第一封裝區域600中；在其他實施例中，更多或更少的積體電路晶粒114可黏附於各區域中。舉例而言，在一實施例中，多個積體電路晶粒114可黏附於第一封裝區域600中。積體電路晶粒114可為邏輯晶粒（例如，中央處理單元、微控制器等）、記憶體晶粒（例如，動態隨機存取記憶體（dynamic random access memory；DRAM）晶粒、靜態隨機存取記憶體（static random access memory；SRAM）晶粒等）、功率管理晶粒（例如，功率管理積體電路（power management integrated circuit；PMIC）晶粒）、射頻（radio frequency；RF）晶粒、感測器晶粒、微機電系統（micro-electro-mechanical-system；MEMS）晶粒、訊號處理晶粒（例如，數位訊號處理（digital signal processing；DSP）晶粒）、前端晶粒（例如，類比前端（analog front-end；AFE）晶粒）、其類似者或其組合。此外，在一些實施例中，積體電路晶粒114可為不同尺寸（例如，不同高度及/或表面積），且在其他實施例中，積體電路晶粒114可為相同尺寸（例如，相同高度及/或表面積）。
在黏附至介電層108之前，可根據可適用的製造製程對積體電路晶粒114進行處理，以在積體電路晶粒114中形成積體電路。舉例而言，集成電路晶粒114各自包含半導體基底118，諸如經摻雜矽或未經摻雜矽、或絕緣層上覆半導體（semiconductor-on-insulator；SOI）基底之主動層。半導體基底可包含其他半導體材料，諸如鍺；化合物半導體，包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或其組合。亦可使用其他基底，諸如多層或梯度基底。諸如電晶體、二極體、電容器、電阻器之元件可形成於半導體基底118中及/或半導體基底118上，且可藉由例如半導體基底118上之一或多層介電層中之金屬化圖案形成的內連線結構120互連，以形成積體電路。
積體電路晶粒114更包括對其進行外部連接之接墊122（諸如鋁接墊）。接墊122在積體電路晶粒114之各個可被稱作主動側的位置上。鈍化膜124在積體電路晶粒114上且在一部分的接墊122上。開口經形成以穿過鈍化膜124而接觸接墊122。諸如導電柱（例如，包括諸如銅之金屬）之晶粒連接件126處於穿過鈍化膜124之開口中，且機械及電性耦接至各個接墊122。可藉由例如鍍覆或類似者形成晶粒連接件126。晶粒連接件126電性耦接積體電路晶粒114之各個積體電路。可在晶粒測試期間於晶粒連接件126上形成焊料頂蓋（未繪示）。
介電材料128在積體電路晶粒114之主動側上，諸如在鈍化膜124及晶粒連接件126上。介電材料128側向包封晶粒連接件126，且介電材料128與各個積體電路晶粒114側向地共端（laterally conterminous）。介電材料128可為聚合物，諸如PBO、聚醯亞胺、BCB或類似者；氮化物，諸如氮化矽或類似者；氧化物，諸如氧化矽、PSG、BSG、BPSG或類似者；類似者；或其組合，且可例如藉由旋轉塗佈、層壓、CVD或類似者形成。
黏著劑116在積體電路晶粒114之背側上，且將積體電路晶粒114黏附至背側重佈線結構110，諸如黏附至圖示中之介電層108。黏著劑116可為任何合適之黏著劑、環氧樹脂、晶粒貼合膜（die attach film；DAF）或類似者。黏著劑116可塗覆於積體電路晶粒114之背側，諸如塗覆於各個半導體晶圓之背側，或可塗覆於載體基底100之表面上方。可藉由諸如鋸割或切割而使積體電路晶粒114單體化，且使用例如取放（pick-and-place）工具將積體電路晶粒114藉由黏著劑116黏附至介電層108。
在圖5中，於各種組件上形成包封體130。包封體130可為模製化合物、環氧樹脂或類似者，且可藉由壓縮模製、轉移模製或類似者來形成包封體130。固化之後，包封體130可經歷研磨製程以暴露出穿孔112及晶粒連接件126。在研磨製程之後，穿孔112之頂部表面、晶粒連接件126之頂部表面以及包封體130之頂部表面共面。在一些實施例中，例如，若已暴露穿孔112及晶粒連接件126，則可省略研磨。
在圖6A至圖21B中，形成前側重佈線結構131。如將示出，前側重佈線結構131包含介電層133、介電層146、介電層160以及介電層174、以及金屬化圖案142、金屬化圖案156以及金屬化圖案170（有時被稱作重佈層或重佈線）。在圖6A至圖21B中，諸圖號以結尾「A」標示為示出第一封裝區域600的剖視圖，且諸圖號以結尾「B」標示為示出積體電路晶粒114上方之前側重佈線結構131之區域650的較多細節的剖視圖。在前側重佈線結構131之區域650中，形成堆疊式通孔結構132。堆疊式通孔結構132具有豎直對準的導通孔（例如，垂直於包封體130之主要表面的線延伸穿過多個導通孔中之每一者）。在圖6A至圖21B中，為簡單起見，一些構件（諸如下文論述之晶種層）可僅示出於「A」圖或「B」圖中之一者中，且可省略於各個「B」圖或「A」圖。
在圖6A及圖6B中，於包封體130、穿孔112以及晶粒連接件126上沈積介電層133。在一些實施例中，介電層133由聚合物形成，所述聚合物可為可使用微影罩幕圖案化之感光性材料，諸如PBO、聚醯亞胺、BCB或類似者。在其他實施例中，介電層133是由以下各者形成：氮化物，諸如氮化矽；氧化物，諸如氧化矽、PSG、BSG、BPSG；或類似者。可藉由旋轉塗佈、層壓、CVD、類似者或其組合形成介電層133。
接著，圖案化介電層133。圖案化介電層133形成開口134，以暴露出穿孔112及晶粒連接件126之一部分。圖案化可藉由可接受的製程：諸如藉由當介電層133為感光性材料時，將介電層133暴露於光線；或藉由使用例如非等向性蝕刻進行蝕刻。若介電層133為感光性材料，則介電層133可在曝光之後進行顯影。
接著，於介電層133上方以及延伸穿過介電層133之開口134中形成晶種層136。在一些實施例中，晶種層136為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層136包括鈦層及鈦層上方之銅層。可使用例如PVD或類似者形成晶種層136。
在圖7A及圖7B中，在晶種層136上形成光阻層138，且圖案化光阻層138。可藉由旋轉塗佈或類似者形成光阻層138，且可將光阻層138暴露於光線以用於圖案化。光阻層138之圖案對應於金屬化圖案142。圖案化形成穿過光阻層138之開口140，以暴露晶種層136。
在圖8A及圖8B中，於光阻層138之開口140中以及晶種層136之暴露部分上形成導電材料。可藉由鍍覆形成導電材料，鍍覆諸如電鍍或無電鍍，或類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁或類似者。在一實施例中，藉由共形鍍覆製程形成導電材料。共形鍍覆製程可為以小於約2.2 A/dm2 之電流密度，諸如約0.3 A/dm2 至約0.9 A/dm2 之電流密度執行的銅電鍍製程。電鍍溶液可包括例如硫酸銅，且可具有諸如促進劑、抑制劑、勻塗劑（leveler agent）及/或類似者之添加劑。此類電鍍溶液及電流密度使得鍍覆製程為共形鍍覆製程。由於金屬化圖案142是用共形鍍覆製程形成，因此沿介電層133之頂部表面延伸的金屬化圖案142之部分可具有與沿開口134之側面及底部延伸的金屬化圖案142之部分大約相同的厚度。
導電材料及下覆的晶種層136之部分的組合形成金屬化圖案142。金屬化圖案142之一部分形成堆疊式通孔結構132之第一層。金屬化圖案142包含導通孔143。導通孔143形成於穿過介電層133至例如穿孔112及/或晶粒連接件126之開口134中。另外，由於共形鍍覆製程，凹陷144形成於導通孔143中。
在圖9A及圖9B中，移除光阻層138以及其上未形成導電材料之一部分的晶種層136。可藉由諸如使用氧電漿或類似者之可接受的灰化或剝離製程移除光阻層138。一旦移除光阻層138，諸如藉由使用可接受的蝕刻製程（諸如，藉由濕式蝕刻或乾式蝕刻）移除晶種層136之暴露部分。
在圖10A及圖10B中，於介電層133及金屬化圖案142上沈積介電層146。在一些實施例中，介電層146由聚合物形成，所述聚合物可為可使用微影罩幕圖案化之感光性材料，諸如PBO、聚醯亞胺、BCB或類似者。在其他實施例中，介電層146是由以下各者形成：氮化物，諸如氮化矽；氧化物，諸如氧化矽、PSG、BSG、BPSG；或類似者。可藉由旋轉塗佈、層壓、CVD、類似者或其組合形成介電層146。
接著，圖案化介電層146。圖案化介電層146形成開口148，以暴露一部分的金屬化圖案142。特定而言，開口148暴露凹陷144。可藉由可接受的製程進行圖案化，諸如當介電層為感光性材料時藉由將介電層146暴露於光線，或藉由使用例如非等向性蝕刻進行蝕刻。若介電層146為感光性材料，則介電層146可在曝光之後進行顯影。
接著於介電層146上方以及開口148中形成晶種層150。在一些實施例中，晶種層150為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層150包括鈦層及鈦層上方之銅層。可使用例如PVD或類似者形成晶種層150。晶種層150沿介電層146之頂部表面、開口148之側面、經由開口148暴露之金屬化圖案142的最頂部表面、定義凹陷144之側面的導通孔143的一部分以及定義凹陷144之底部的導通孔143的一部分延伸。
在圖11A及圖11B中，在晶種層150上形成光阻層152，且對光阻層152進行圖案化。可藉由旋轉塗佈或類似者形成光阻層152，且可將光阻層152暴露於光線以用於圖案化。光阻層152之圖案對應於金屬化圖案156。圖案化光阻層152形成穿過光阻層之開口154，以暴露晶種層150。開口154暴露介電層146之開口148。
在圖12A及圖12B中，於晶種層150之暴露部分上及光阻層152之開口154中形成導電材料。可藉由鍍覆形成導電材料，鍍覆諸如電鍍或無電鍍，或類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁或類似者。在一實施例中，藉由共形鍍覆製程（類似於金屬化圖案142的形成方法）形成導電材料。
導電材料及下覆的晶種層150之一部分的組合形成金屬化圖案156。金屬化圖案156之一部分形成堆疊式通孔結構132之第二層。金屬化圖案156包含導通孔157。導通孔157形成於穿過介電層146至金屬化圖案142之開口148中。特定而言，導通孔157延伸至導通孔143之凹陷144中。另外，由於共形鍍覆製程，凹陷158形成於導通孔157中。
在圖13A及圖13B中，移除光阻層152及其上未形成導電材料之晶種層150的一部分。可藉由諸如使用氧電漿或類似者之可接受的灰化或剝離製程移除光阻層152。一旦移除光阻152，諸如藉由使用可接受的蝕刻製程（諸如，藉由濕式蝕刻或乾式蝕刻）移除晶種層150之暴露部分。
藉由形成具有凹陷144的導通孔143，金屬化圖案142及金屬化圖案156之界面可為非平面的（例如，交錯式（staggered））。另外，金屬化圖案142及金屬化圖案156之界面可佔據從介電層133及介電層146之界面偏移（例如，相較於介電層133及介電層146之界面而在不同平面中）之多個平面。封裝應力可集中在介電層133及介電層146之界面處。藉由將介電層133及介電層146之界面從金屬化圖案142及金屬化圖案156的多個平面偏移，可進一步避免封裝應力集中，藉此減少在金屬化圖案142及金屬化圖案156之界面處形成裂紋之機會。
在圖14A及圖14B中，於介電層146及金屬化圖案156上沈積介電層160。在一些實施例中，介電層160由聚合物形成，所述聚合物可為可使用微影罩幕圖案化之感光性材料，諸如PBO、聚醯亞胺、BCB或類似者。在其他實施例中，介電層160由以下各者形成：氮化物，諸如氮化矽；氧化物，諸如氧化矽、PSG、BSG、BPSG；或類似者。可藉由旋轉塗佈、層壓、CVD、類似者或其組合形成介電層160。
接著，圖案化介電層160。圖案化介電層160形成開口162，以暴露金屬化圖案156之一部分。特定而言，開口162暴露凹陷158。可藉由可接受的製程進行圖案化，諸如藉由當介電層為感光性材料時將介電層160暴露於光線，或藉由使用例如非等向性蝕刻進行蝕刻。若介電層160為感光性材料，則介電層160可在曝光之後進行顯影。
接著於介電層160上方以及開口162中形成晶種層164。在一些實施例中，晶種層164為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層164包括鈦層及鈦層上方之銅層。可使用例如PVD或類似者形成晶種層164。晶種層164沿介電層160之頂部表面、開口162之側面、經由開口162暴露之金屬化圖案156的最頂部表面、定義凹陷158之側面的導通孔157之部分以及沿定義凹陷158之底部的導通孔157之部分延伸。
在圖15A及圖15B中，在晶種層164上形成光阻層166，且圖案化光阻層166。可藉由旋轉塗佈或類似者形成光阻層166，且可將光阻層166暴露於光線以用於圖案化。光阻層166之圖案對應於金屬化圖案170。圖案化光阻層166形成穿過光阻之開口168，以暴露出晶種層164。開口168暴露介電層160之開口162。
在圖16A及圖16B中，於晶種層164之暴露部分上及光阻層166之開口168中形成導電材料。可藉由鍍覆形成導電材料，鍍覆諸如電鍍或無電鍍，或類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁或類似者。在一實施例中，藉由共形鍍覆製程（類似於金屬化圖案156的形成方法）形成導電材料。
導電材料及下覆的晶種層164之一部分的組合形成金屬化圖案170。金屬化圖案170之一部分形成堆疊式通孔結構132之第三層。金屬化圖案170包含導通孔171。導通孔171形成於穿過介電層160至金屬化圖案156之開口162中。特定而言，導通孔171延伸至導通孔157之凹陷158中。另外，由於共形鍍覆製程，凹陷172形成於導通孔171中。
在圖17A及圖17B中，移除光阻層166及其上未形成導電材料之晶種層164之一部分。可藉由諸如使用氧電漿或類似者之可接受的灰化或剝離製程移除光阻層166。一旦移除光阻層166，諸如藉由使用可接受的蝕刻製程（諸如，藉由濕式蝕刻或乾式蝕刻）移除晶種層164之暴露部分。
在圖18A及圖18B中，於介電層160及金屬化圖案170上沈積介電層174。在一些實施例中，介電層174由聚合物形成，所述聚合物可為可使用微影罩幕圖案化之感光性材料，諸如PBO、聚醯亞胺、BCB或類似者。在其他實施例中，介電層174由以下各者形成：氮化物，諸如氮化矽；氧化物，諸如氧化矽、PSG、BSG、BPSG；或類似者。可藉由旋轉塗佈、疊層、CVD、類似者或其組合形成介電層174。
接著，圖案化介電層174。圖案化介電層174形成開口176，以暴露金屬化圖案170之一部分。特定而言，開口176暴露凹陷172。可藉由可接受的製程進行圖案化，諸如藉由當介電層為感光性材料時將介電層174暴露於光線，或藉由使用例如非等向性蝕刻進行蝕刻。若介電層174為感光性材料，則介電層174可在曝光之後進行顯影。
接著，於介電層174上方以及開口176中形成晶種層178。在一些實施例中，晶種層178為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層178包括鈦層及鈦層上方之銅層。可使用例如PVD或類似者形成晶種層178。晶種層178沿介電層174之頂部表面、開口176之側面、經由開口176暴露之金屬化圖案170的最頂部表面、定義凹陷172之側面的導通孔171之部分以及定義凹陷172之底部的導通孔171之部分延伸。
在圖19A及圖19B中，在晶種層178上形成光阻層180，且圖案化光阻層180。可藉由旋轉塗佈或類似者形成光阻層180，且可將光阻層180暴露於光線以用於圖案化。光阻層180之圖案對應於接墊184。圖案化光阻層180形成穿過光阻層之開口182，以暴露晶種層178。開口182暴露介電層174之開口176。光阻層180中之開口182之圖案對應於將隨後形成於前側重佈線結構131之外部側上的接墊。
在圖20A及圖20B中，於晶種層178之暴露部分上及光阻層180之開口182中形成導電材料。可藉由鍍覆形成導電材料，鍍覆諸如電鍍或無電鍍，或類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁或類似者。在一實施例中，藉由間隙填充鍍覆製程形成導電材料，其具有不同於共形鍍覆製程的鍍覆製程參數。間隙填充鍍覆製程可為以約2.0 A/dm2 至約6.0 A/dm2 ，諸如大於約2.2 A/dm2 之電流密度執行的銅電鍍製程。電鍍溶液可包括硫酸銅，且可具有諸如促進劑、抑制劑、勻塗劑及/或類似者之添加劑。此類電鍍溶液及電流密度使得鍍覆製程為間隙填充鍍覆製程。用於間隙填充鍍覆製程之電鍍溶液可類似於或不同於用於共形鍍覆製程之電鍍溶液。
導電材料及下覆的晶種層178之一部分的組合形成接墊184。接墊184之一部分形成堆疊式通孔結構132之第四層。接墊184包含導通孔185。導通孔185形成於穿過介電層174至金屬化圖案170之開口176中。特定而言，導通孔185延伸至導通孔171之凹陷172中。另外，由於間隙填充鍍覆製程，接墊184並不具有與堆疊式通孔結構132中之其他通孔一樣深之凹陷186，且可歸因於下覆的開口176之形狀，而僅具有凹陷186。接墊184用以耦接至隨後所形成之導電連接件，且可被稱作凸塊下金屬（under bump metallurgy；UBM）。
在圖21A及圖21B中，移除光阻180以及其上未形成導電材料之晶種層178之一部分。可藉由諸如使用氧電漿或類似者之可接受的灰化或剝離製程移除光阻層180。一旦移除光阻層180，諸如藉由使用可接受的蝕刻製程（諸如，藉由濕式蝕刻或乾式蝕刻）移除晶種層178之暴露部分。
將前側重佈線結構131及堆疊式通孔結構132展示為實例。更多或更少介電層及金屬化圖案可形成於前側重佈線結構131中。若形成較少介電層及金屬化圖案，則可省略上文所論述之步驟及製程。若形成較多介電層及金屬化圖案，則可重複上文所論述之步驟及製程。在本領域中具有通常知識者將容易理解哪些步驟及製程將被省略或重複。
在圖22中，於接墊184上形成導電連接件187。導電連接件187可為球柵陣列（ball grid array；BGA）連接件、焊料球、金屬柱、受控塌陷晶粒連接（controlled collapse chip connection；C4）凸塊、微凸塊、無電式鍍鎳鈀浸金（electroless nickel-electroless palladium-immersion gold technique；ENEPIG）技術形成的凸塊、或類似者。導電連接件187可包含導電材料，諸如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似者或其組合。在一些實施例中，藉由諸如蒸鍍、電鍍、列印、焊料轉移、植球或類似者之此些常用方法最初形成焊料層來形成導電連接件187。一旦於結構上形成焊料層，則可執行回焊以便將材料塑形成所要凸塊形狀。在另一實施例中，導電連接件187為藉由濺鍍、列印、電鍍、無電鍍、CVD或類似者所形成之金屬柱（諸如銅柱）。金屬柱可無焊料且具有實質上豎直的側壁。在此類實施例中，金屬頂蓋層（未圖示）可形成於導電連接件187之頂部上。金屬頂蓋層可包含鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金、類似者或其組合，且可由鍍覆製程形成金屬頂蓋層。
另外，將積體被動元件（integrated passive device；IPD）188附接至前側重佈線結構131。IPD 188電性連接至堆疊式通孔結構132，且堆疊式通孔結構132可電性連接至積體電路晶粒114。在一實施例中，堆疊式通孔結構132之最底部通孔（例如，金屬化圖案142）電性連接且物理連接至積體電路晶粒114之晶粒連接件126中之一者，且堆疊式通孔結構132之最頂部通孔（例如，接墊184）電性連接且物理連接至IPD 188。
在將IPD 188黏接至前側重佈線結構131之前，可根據可適用的製造製程處理IPD 188。舉例而言，IPD 188可包括在IPD 188之主要結構中的一或多個被動元件。主要結構可包含基底及/或包封體。在主要結構包含基底之實施例中，所述基底可為諸如經摻雜矽或未經摻雜矽之半導體基底或SOI基底之主動層。半導體基底可包含其他半導體材料，諸如鍺；化合物半導體，包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或其組合。亦可使用其他基底，諸如多層或梯度基底。被動元件可包含電容器、電阻器、電感器、類似者或其組合。被動元件可形成於半導體基底中及/或半導體基底上及/或包封體內，且可藉由由例如主要結構上之一或多個介電層中之金屬化圖案所形成的內連線結構互連以形成IPD 188。IPD 188可為表面黏著元件（surface mount device；SMD）、2端IPD、多端IPD或其他類型的被動元件。IPD 188是用導電連接件189電性連接及物理連接至堆疊式通孔結構132之接墊184，藉此將前側重佈線結構131耦接至IPD 188。導電連接件189可類似於導電連接件187，或可不同於導電連接件187。
在圖23中，執行載體基底剝離以將載體基底100自背側重佈線結構110（例如，重佈線結構110的介電層104）拆離（剝離）。根據一些實施例，剝離包含使諸如雷射光或UV光之光線投影於離形層102上，以使得離形層102在光熱下分解且可移除載體基底100。接著翻轉結構且將其置放於膠帶192上。
另外，形成穿過介電層104之開口194，以暴露金屬化圖案106之一部分。舉例而言，可使用雷射鑽孔、蝕刻、或類似者形成開口。
圖24至圖26根據一些實施例示出形成封裝結構500之製程期間的中間步驟的剖視圖。封裝結構500可稱為疊層封裝（PoP）結構。
在圖24中，第二封裝300附接至第一封裝200。第二封裝300包含基底302及耦接至所述基底302之一或多個堆疊式晶粒308（晶粒308A及晶粒308B）。儘管示出了單個堆疊式晶粒308（晶粒308A及晶粒308B），但在其他實施例中，多個堆疊式晶粒308（各自具有一或多個堆疊式晶粒）可並排地設置耦接至基底302之相同表面。基底302可由半導體材料，諸如矽、鍺、金剛石或類似者製成。在一些實施例中，亦可使用化合物材料，諸如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化砷鎵、磷化鎵銦、此等之組合以及類似者。另外，基底302可為絕緣層上矽（SOI）基底。通常，SOI基底包含諸如磊晶矽、鍺、矽鍺、SOI、絕緣層上矽鍺（silicon germanium on insulator；SGOI）或其組合之半導體材料層。在一個替代性實施例中，基底302基於諸如玻璃纖維增強樹脂芯之絕緣芯。一個實例核心材料為玻璃纖維樹脂，諸如FR4。核心材料之替代物包含雙馬來醯亞胺三嗪（bismaleimide-triazine；BT）樹脂，或替代地包含其他印刷電路板（printed circuit board；PCB）材料或膜。增層膜，諸如味之素增層膜（Ajinomoto build-up film；ABF）或其他疊層物可用於形成基底302。
基底302可包含主動元件及被動元件（未圖示）。如在本領域中具有通常知識者將認識到，諸如電晶體、電容器、電阻器、此等之組合以及類似者之廣泛的多種元件可用於產生第二封裝300的設計之結構性及功能性需求。可使用任何合適之方法形成所述元件。
基底302亦可包含金屬化層（未圖示）及穿孔306。金屬化層可形成於主動元件及被動元件上方，且經設計以連接各種元件以形成功能性電路。金屬化層可由介電材料（例如，低介電常數介電材料）及導電材料（例如，銅）之交替層形成，其中通孔互連導電材料層，且可經由任何合適之製程（諸如，沈積、鑲嵌、雙鑲嵌或類似者）形成金屬化層。在一些實施例中，基底302實質上不含主動元件及被動元件。
基底302可在基底202之第一側上具有接合墊303，以耦接至堆疊式晶粒308。此外，在基底302之第二側上具有接合墊304（所述第二側與基底302之第一側相對），以耦接至功能性連接件314。在一些實施例中，藉由在基底302之第一側及第二側上將凹陷（未圖示）形成於介電層（未圖示）中而形成接合墊303及接合墊304。凹陷經形成以允許將接合墊303及接合墊304嵌入於介電層中。在其他實施例中，省略凹陷，此是因為接合墊303及接合墊304可形成於介電層上。在一些實施例中，接合墊303及接合墊304包含由銅、鈦、鎳、金、鈀、類似者或其組合製成之薄晶種層（未圖示）。接合墊303及接合墊304之導電材料可沈積於薄晶種層上方。導電材料可藉由電化學鍍覆製程、化學鍍覆製程、CVD、ALD、PVD、類似者、或其組合形成。在一實施例中，接合墊303及接合墊304之導電材料為銅、鎢、鋁、銀、金、類似者或其組合。
在一實施例中，接合墊303及接合墊304為包含三種導電材料層（諸如鈦層、銅層以及鎳層）之UBM。然而，在本領域中具有通常知識者將認識到，存在適合於形成接合墊303及接合墊304之許多合適之材料及層的配置，諸如鉻/鉻銅合金/銅/金之配置、鈦/鈦鎢/銅之配置或銅/鎳/金的配置。可用於接合墊303及接合墊304之任何合適之材料或材料層全部意欲包含於當前申請案之範疇內。在一些實施例中，穿孔306延伸穿過基底302且將至少一個接合墊303耦接至至少一個接合墊304。
在所示實施例中，堆疊式晶粒308是由打線310耦接至基底302，但可使用其他連接件，諸如導電凸塊。在一實施例中，堆疊式晶粒308為堆疊式記憶體晶粒。舉例而言，堆疊式晶粒308可為諸如低功率（low-power；LP）雙倍資料速率（double data rate；DDR）記憶體模組之記憶體晶粒，諸如LPDDR1、LPDDR2、LPDDR3、LPDDR4或類似的記憶體模組。
可由模製材料312包封堆疊式晶粒308及打線310。可例如使用壓縮模製而將模製材料312模製於堆疊式晶粒308及打線310上。在一些實施例中，模製材料312為模製化合物、聚合物、環氧樹脂、氧化矽填充物材料、類似者或其組合。可執行固化步驟以固化模製材料312，其中固化可為熱固化、UV固化、其類似者或其組合。
在一些實施例中，堆疊式晶粒308及打線310埋入於模製材料312中，且在固化模製材料312之後，執行諸如研磨之平坦化步驟以移除模製材料312之過量部分且為第二封裝300提供實質上平坦之表面。
在形成第二封裝300之後，第二封裝300藉助於功能性連接件314、接合墊304以及金屬化圖案106機械地及電性接合至第一封裝200。在一些實施例中，堆疊式晶粒308可經由打線310、接合墊303及接合墊304、穿孔306、功能性連接件314以及穿孔112耦接至積體電路晶粒114。
功能性連接件314可類似於上文所描述之導電連接件187，且在本文中不重複所述描述，但功能性連接件314及導電連接件187不必相同。功能性連接件314可設置於開口194中，且位於基底302之相對於堆疊式晶粒308之一側上。在一些實施例中，亦可於基底302之相對於堆疊式晶粒308的一側上形成阻焊劑318。功能性連接件314可設置於待電性耦接及機械耦接至基底302中之導電構件（例如，接合墊304）之阻焊劑318的開口中。阻焊劑318可用於保護基底302的區域，以避免受到外部損害。
在一些實施例中，在接合功能性連接件314之前，功能性連接件314塗佈有助焊劑（未圖示），諸如免清洗助焊劑。功能性連接件314可浸漬於助焊劑中或助焊劑可噴射至功能性連接件314上。在另一實施例中，助焊劑可塗覆至金屬化圖案106之表面。
在一些實施例中，在進行回焊之前，功能性連接件314可具有視情況應用於其上之環氧樹脂助焊劑（未圖示）。在第二封裝300附接至第一封裝200之後，環氧樹脂助焊劑中的至少一些環氧樹脂部分會殘留下來。此剩餘的環氧樹脂部分可充當底膠以減小應力以及保護對功能性連接件314進行回焊所產生的接點。
底膠（未圖示）可形成於第一封裝200與第二封裝300之間，且包圍功能性連接件314。可在附接第一封裝200之後藉由毛細流動製程形成底膠，或可在附接第一封裝200之前藉由合適的沈積方法形成底膠。
第二封裝300與第一封裝200之間的接合可為焊料接合。在一實施例中，第二封裝300藉由回焊製程接合至第一封裝200。在此回焊製程期間，功能性連接件314與接合墊304及金屬化圖案106接觸，以將第二封裝300物理地且電性耦接至第一封裝200。在接合製程之後，金屬間化合物（intermetallic compound；IMC，未圖示）可形成於金屬化圖案106與功能性連接件314之界面處，且亦形成於功能性連接件314與接合墊304（未圖示）之間的界面處。
在圖25中，藉由沿切割道區（例如，在鄰近的封裝區域之間）進行鋸割190來執行單體化製程。鋸割190使第一封裝區域600自其他封裝區域（未圖示）單體化。所得經單體化的第一封裝200來自第一封裝區域600。
在圖26中，第一封裝200使用導電連接件187安裝至封裝基底400。封裝基底400可由諸如矽、鍺、金剛石或類似者的半導體材料製成。可替代地，亦可使用化合物材料，諸如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化砷鎵、磷化鎵銦、此等之組合以及類似者。另外，封裝基底400可為SOI基底。通常，SOI基底包含諸如磊晶矽、鍺、矽鍺、SOI、SGOI或其組合之半導體材料層。在一個替代性實施例中，封裝基底400基於諸如玻璃纖維增強樹脂芯之絕緣芯。一個實例核心材料為玻璃纖維樹脂，諸如FR4。核心材料之替代物包含雙馬來醯亞胺三嗪（BT）樹脂，或可替代地，包含其他PCB材料或膜。增層膜，諸如ABF或其他疊層物可用於形成封裝基底400。
封裝基底400可包含主動元件及被動元件（未圖示）。如在本領域中具有通常知識者將認識到，諸如電晶體、電容器、電阻器、此等之組合以及類似者之廣泛的多種元件可用於產生封裝結構500之設計的結構性及功能性需求。可使用任何合適之方法形成所述元件。
封裝基底400亦可包含金屬化層及通孔（未圖示）以及金屬化層及通孔上方之接合墊402。金屬化層可形成於主動元件及被動元件上方，且經設計以連接各種元件以形成功能性電路。可由介電材料（例如，低介電常數介電材料）及導電材料（例如，銅）之交替層形成金屬化層，其中通孔互連導電材料層，且可經由任何合適之製程（諸如，沈積、鑲嵌、雙鑲嵌或類似者）形成金屬化層。在一些實施例中，封裝基底400實質上不含主動元件及被動元件。
在一些實施例中，回焊導電連接件187以將第一封裝200附接至接合墊402。導電連接件187電性及/或物理地將封裝基底400（包含封裝基底400中之金屬化層）耦接至第一封裝200。在一些實施例中，被動元件（例如，表面黏著元件（SMD），未示出）可在安裝於封裝基底400上之前附接至第一封裝200（例如，接合至接合墊402）。在此類實施例中，被動元件可接合至第一封裝200的與導電連接件187相同之表面。
在進行回焊之前，導電連接件187可具有應用於其上的環氧樹脂助焊劑（未圖示）。第一封裝200附接至封裝基底400之後，環氧樹脂助焊劑之至少一些環氧樹脂部分會殘留下來。此剩餘環氧樹脂部分可充當底膠以減小應力且保護對導電連接件187進行回焊所產生的接點。在一些實施例中，底膠（未圖示）可形成於第一封裝200與封裝基底400之間，且包圍導電連接件187。可在附接第一封裝200之後藉由毛細流動製程形成底膠，或可在附接第一封裝200之前藉由合適之沈積方法形成底膠。
圖27至圖42根據一些其他實施例示出堆疊式通孔結構132之形成。圖27至圖42示出區域650。在圖27至圖42之實施例中，堆疊式通孔結構132之通孔經形成而圍繞導電柱。
在圖27中，於包封體130、穿孔112以及積體電路晶粒114（例如，晶粒連接件126）上沈積介電層133。接著，圖案化介電層133以形成開口134。接著，於介電層133上方以及延伸穿過介電層133之開口134中形成晶種層136。
在圖28中，在晶種層136上形成光阻層138，且圖案化光阻層138。接著，圖案化光阻層138，形成穿過光阻層138而暴露出晶種層136之開口140。開口140之寬度小於開口134之寬度。
在圖29中，於晶種層136之暴露部分上形成導電材料。可藉由鍍覆形成導電材料，鍍覆諸如電鍍或無電鍍，或類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁或類似者。導電材料及下覆的晶種層136之一部分的組合形成導電柱702。
在圖30中，移除光阻層138以及其上未形成導電材料之晶種層136的一部分。
在圖31中，於介電層133上以及導電柱702周圍沈積介電層146。接著，圖案化介電層146。圖案化介電層146形成開口148，以暴露出開口134。接著在介電層146上方、穿過介電層146之開口148中以及穿過介電層133之開口134中形成晶種層150。晶種層150沿導電柱702之側面延伸。
在圖32中，在晶種層150上形成光阻層152且圖案化光阻層152。圖案化光阻層152形成穿過光阻之開口154，以暴露晶種層150。開口154包圍導電柱702。經圖案化的光阻層152之一部分設置於導電柱702上方。
在圖33中，於晶種層150之暴露部分上形成導電材料。可藉由鍍覆形成導電材料，鍍覆諸如電鍍或無電鍍，或類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁或類似者。導電材料及下覆的晶種層150之一部分的組合形成圍繞導電柱702之導通孔704。導通孔704延伸穿過介電層133及介電層146兩者。
在圖34中，移除光阻層152以及其上未形成導電材料之晶種層150之一部分。
在圖35中，於介電層146及導通孔704上沈積介電層160。接著，圖案化介電層160。圖案化介電層160形成開口162，以暴露部分的導通孔704及導電柱702。接著，於介電層160上方以及穿過介電層160之開口162中形成晶種層164。晶種層164沿導電柱702之側壁及頂部表面延伸。
在圖36中，在晶種層164上形成光阻層166且，圖案化光阻層166。圖案化光阻層166形成穿過光阻層166之開口168，以暴露晶種層164。開口168在導電柱702上方，且可具有約等於導電柱702之寬度的寬度。
在圖37中，於晶種層164之暴露部分上形成導電材料。可藉由鍍覆形成導電材料，鍍覆諸如電鍍或無電鍍，或類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁或類似者。導電材料及下覆的晶種層164之一部分的組合在導電柱702上形成導電柱706。
在圖38中，移除光阻層166及其上未形成導電材料之晶種層164的一部分。沿導電柱702之側壁及頂部表面的晶種層164之部分未被移除。
在圖39中，於介電層160及導通孔704上沈積介電層174，且介電層174環繞導電柱702及導電柱706。圖案化介電層174。圖案化介電層174形成開口176，以暴露出部分的導通孔704、導電柱702以及導電柱706。接著，於介電層174上方以及於穿過介電層174之開口176中形成晶種層178。晶種層178沿導電柱702及導電柱706之側壁以及沿導電柱706之頂部表面延伸。
在圖40中，在晶種層178上形成光阻層180，且圖案化光阻層180。圖案化光阻層180形成穿過光阻層180之開口182，以暴露出晶種層178。開口182在導電柱702及導電柱706上方。
在圖41中，於晶種層178之暴露部分上形成導電材料。可藉由鍍覆形成導電材料，鍍覆諸如電鍍或無電鍍，或類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁或類似者。導電材料及下覆的晶種層178之一部分的組合形成接墊184，其包含環繞導電柱702及導電柱706之導通孔708。導通孔708延伸穿過介電層160及介電層174兩者。導通孔708可在導電柱702及導電柱706上方延伸。
在圖42中，移除光阻層180及其上未形成導電材料之晶種層178的一部分。
實施例可達成優點。藉由從金屬化圖案142及金屬化圖案156之多個界面的平面偏移介電層133及介電層146之界面，可進一步避免封裝應力集中，藉此減少在金屬化圖案142及金屬化圖案156之界面處形成裂紋之機會。另外，晶種層136、晶種層150、晶種層164以及晶種層178可充當相鄰的堆疊通孔之間的擴散阻擋層。在形成導電柱702及導電柱706之實施例中，導電柱702與導電柱706可充當芯部結構，以強化堆疊式通孔結構132。
在一實施例中，一種半導體封裝包含：模製化合物；積體電路晶粒，包封在模製化合物中；穿孔，與積體電路晶粒相鄰；以及重佈線結構，在積體電路晶粒、模製化合物以及穿孔上方，重佈線結構電性連接至積體電路晶粒及穿孔，重佈線結構包含：第一介電層，設置於模製化合物上方；第一導通孔，延伸穿過第一介電層；第二介電層，設置於第一介電層及第一導通孔上方；以及第二導通孔，延伸穿過第二介電層且進入第一導通孔之一部分中，第一導通孔與第二導通孔之間的界面為非平面的。
在一些實施例中，第一導通孔與第二導通孔之間的界面具有處於第一平面中的第一部分及處於第二平面中的第二部分，第一平面接近積體電路晶粒，第二平面遠離積體電路晶粒，且第一介電層與第二介電層之間的界面處於第一平面與第二平面之間的第三平面中。在一些實施例中，重佈線結構更包含：第三介電層，在第二介電層及第二導通孔上方；以及第三導通孔，延伸穿過第三介電層且進入第二導通孔之一部分中，第二導通孔與第三導通孔之間的界面為非平面的。在一些實施例中，元件更包含：積體被動元件（IPD），經附接至第三導通孔。
在一實施例中，一種半導體封裝的製造方法包含：將積體電路晶粒包封在模製化合物中，積體電路晶粒具有晶粒連接件；在模製化合物上方沈積第一介電層；圖案化第一介電層以形成穿過第一介電層且暴露積體電路晶粒之晶粒連接件的第一開口；在第一介電層上方以及第一開口中沈積第一晶種層；於第一晶種層上鍍覆第一導通孔，第一導通孔延伸穿過第一介電層，第一導通孔在第一導通孔的延伸穿過第一介電層的部分中具有第一凹陷；在第一介電層及第一導通孔上方沈積第二介電層；圖案化第二介電層以形成位於第二介電層中的第二開口，第二開口暴露第一導通孔之第一凹陷；在第二介電層上方、第二開口中以及在第一凹陷中沈積第二晶種層；以及於第二晶種層上鍍覆第二導通孔，第二導通孔延伸至第一導通孔之第一凹陷中且穿過第二介電層，第二導通孔在第二導通孔的延伸穿過第二介電層之部分中具有第二凹陷。
在一些實施例中，第二晶種層具有處於第一平面中的第一部分及第二平面中的第二部分，第一介電層與第二介電層之間的第二界面處於第三平面中，且第一平面接近積體電路晶粒，第二平面遠離積體電路晶粒，且第三平面在第一平面與第二平面之間。在一些實施例中，第二晶種層沿第二介電層之頂部表面、第二開口之側面、第一導通孔之最頂部表面、定義第一凹陷之側面的第一導通孔之部分以及定義第一凹陷之底部的第一導通孔之部分延伸。在一些實施例中，第二介電層與第二晶種層之間的界面為非平面的。在一些實施例中，所述方法更包含：在第二介電層及第二導通孔上方沈積第三介電層；圖案化第三介電層以在第三介電層中形成第三開口，所述第三開口暴露第二導通孔之第二凹陷；在第三介電層上方、第三開口中以及第二凹陷中沈積第三晶種層；以及於第三晶種層上鍍覆第三導通孔，第三導通孔延伸至第二導通孔之第二凹陷中且穿過第三介電層。在一些實施例中，第二導通孔延伸穿過第二介電層，且至少部分地延伸至第一介電層及第三介電層中。在一些實施例中，所述方法更包含：將積體被動元件（IPD）附接至第三導通孔。在一些實施例中，將第三導通孔鍍覆於第二晶種層上是以間隙填充鍍覆製程執行。在一些實施例中，間隙填充鍍覆製程包含以2.0 A/dm2 至6.0 A/dm2 之鍍覆電流密度所執行之鍍覆製程，且電鍍溶液包括硫酸銅。在一些實施例中，將第二導通孔鍍覆於第二晶種層上是以共形鍍覆製程執行。在一些實施例中，共形鍍覆製程包含以自0.3 A/dm2 至0.9 A/dm2 之鍍覆電流密度所執行之鍍覆製程，且電鍍溶液包括硫酸銅。
在一實施例中，一種半導體封裝的製造方法包含：將積體電路晶粒包封於模製化合物中，積體電路晶粒具有晶粒連接件；在模製化合物上方沈積第一介電層；圖案化第一介電層以形成穿過第一介電層的第一開口；在積體電路晶粒之晶粒連接件上的第一開口中形成第一導電柱；在第一介電層上方沈積第二介電層；圖案化第二介電層以在第二介電層中形成第二開口，第二開口暴露出第一開口；以及在第一開口及第二開口中形成第一導通孔，第一導通孔環繞第一導電柱。
在一些實施例中，所述半導體封裝的製造方法更包含：在第二介電層上方沈積第三介電層；圖案化第三介電層以在第三介電層中形成第三開口，所述第三開口暴露第一導通孔；在第一導電柱上的第三開口中形成第二導電柱；在第三介電層上方沈積第四介電層圖案化第四介電層以在第四介電層中形成第四開口，所述第四開口暴露第三開口；以及在第三開口及第四開口中形成第二導通孔，第二導通孔環繞第二導電柱。在一些實施例中，所述半導體封裝的製造方法更包含：將積體被動元件（IPD）附接至第二導通孔。在一些實施例中，在沈積第三介電層之後，第一導通孔延伸穿過第一介電層、第二介電層，且部分地進入第三介電層中。在一些實施例中，第二導通孔經形成而更圍繞第一導電柱。
前文概述若干實施例之構件，使得在本領域中具有知識者可更好地理解本發明之態樣。在本領域中具有知識者應理解，其可易於使用本發明作為設計或修改用於實現本文中所引入之實施例的相同目的及/或達成相同優點之其他製程及結構之基礎。在本領域中具有知識者亦應認識到，此類等效構造並不脫離本發明之精神及範疇，且其可在不脫離本發明之精神及範疇的情況下在本文中進行各種改變、替代以及更改。
100‧‧‧載體基底
102‧‧‧離形層
104‧‧‧介電層
106‧‧‧金屬化圖案
108‧‧‧介電層
110‧‧‧背側重佈線結構
112‧‧‧穿孔
114‧‧‧積體電路晶粒
116‧‧‧黏著劑
118‧‧‧半導體基底
120‧‧‧內連線結構
122‧‧‧接墊
124‧‧‧鈍化膜
126‧‧‧晶粒連接件
128‧‧‧介電材料
130‧‧‧包封體
131‧‧‧前側重佈線結構
132‧‧‧堆疊式通孔結構
133‧‧‧介電層
134‧‧‧開口
136‧‧‧晶種層
138‧‧‧光阻層
140‧‧‧開口
142‧‧‧金屬化圖案
143‧‧‧導通孔
144‧‧‧凹陷
146‧‧‧介電層
148‧‧‧開口
150‧‧‧晶種層
152‧‧‧光阻層
154‧‧‧開口
156‧‧‧金屬化圖案
157‧‧‧導通孔
158‧‧‧凹陷
160‧‧‧介電層
162‧‧‧開口
164‧‧‧晶種層
166‧‧‧光阻層
168‧‧‧開口
170‧‧‧金屬化圖案
171‧‧‧導通孔
172‧‧‧凹陷
174‧‧‧介電層
176‧‧‧開口
178‧‧‧晶種層
180‧‧‧光阻層
182‧‧‧開口
184‧‧‧接墊
185‧‧‧導通孔
186‧‧‧凹陷
187‧‧‧導電連接件
188‧‧‧積體被動元件
189‧‧‧導電連接件
190‧‧‧鋸割
192‧‧‧膠帶
194‧‧‧開口
200‧‧‧第一封裝
300‧‧‧第二封裝
302‧‧‧基底
303‧‧‧接合墊
304‧‧‧接合墊
306‧‧‧穿孔
308‧‧‧堆疊式晶粒
308A‧‧‧晶粒
308B‧‧‧晶粒
310‧‧‧打線
312‧‧‧模製材料
314‧‧‧連接件
318‧‧‧阻焊劑
400‧‧‧封裝基底
402‧‧‧接合墊
500‧‧‧封裝結構
600‧‧‧第一封裝區域
650‧‧‧區域
702‧‧‧導電柱
704‧‧‧導通孔
706‧‧‧導電柱
結合附圖閱讀以下詳細描述會最佳地理解本發明之態樣。應注意，根據業界中的標準慣例，各種構件未按比例繪製。實際上，為論述清楚起見，可任意增大或減小各種構件之尺寸。 圖1至圖23根據一些實施例示出形成封裝的製程期間的中間步驟的剖視圖。 圖24至圖26根據一些實施例示出形成封裝結構的製程期間的中間步驟的剖視圖。 圖27至圖42根據一些其他實施例示出堆疊式通孔結構之形成。

Claims (20)

  1. 一種半導體封裝，包括： 模製化合物； 積體電路晶粒，包封於所述模製化合物中； 穿孔，與所述積體電路晶粒相鄰；以及 重佈線結構，在所述積體電路晶粒、所述模製化合物以及所述穿孔上方，所述重佈線結構電性連接至所述積體電路晶粒及所述穿孔，所述重佈線結構包括： 第一介電層，設置於所述模製化合物上方； 第一導通孔，延伸穿過所述第一介電層； 第二介電層，設置於所述第一介電層及所述第一導通孔上方；以及 第二導通孔，延伸穿過所述第二介電層且進入所述第一導通孔之一部分中，所述第一導通孔與所述第二導通孔之間的界面為非平面的。
  2. 如申請專利範圍第1項所述的半導體封裝，其中所述第一導通孔與所述第二導通孔之間的界面具有處於第一平面中的第一部分及處於第二平面中的第二部分，所述第一平面接近所述積體電路晶粒，所述第二平面遠離所述積體電路晶粒，且其中所述第一介電層與所述第二介電層之間的界面處於所述第一平面與所述第二平面之間的第三平面中。
  3. 如申請專利範圍第1項所述的半導體封裝，其中所述重佈線結構更包括： 第三介電層，在所述第二介電層及所述第二導通孔上方；以及 第三導通孔，延伸穿過所述第三介電層且進入所述第二導通孔之一部分中，所述第二導通孔與所述第三導通孔之間的界面為非平面的。
  4. 如申請專利範圍第3項所述的半導體封裝，更包括： 積體被動元件，附接至所述第三導通孔。
  5. 一種半導體封裝的製造方法，包括： 將積體電路晶粒包封在模製化合物中，所述積體電路晶粒具有晶粒連接件； 在所述模製化合物上方沈積第一介電層； 圖案化所述第一介電層，以形成穿過所述第一介電層且暴露所述積體電路晶粒之所述晶粒連接件的第一開口； 於所述第一介電層上方以及所述第一開口中沈積第一晶種層； 於所述第一晶種層上鍍覆第一導通孔，所述第一導通孔延伸穿過所述第一介電層，所述第一導通孔在所述第一導通孔的延伸穿過所述第一介電層的部分中具有第一凹陷； 於所述第一介電層及所述第一導通孔上方沈積第二介電層； 圖案化所述第二介電層，以形成位於所述第二介電層中的第二開口，所述第二開口暴露所述第一導通孔之所述第一凹陷； 於所述第二介電層上方、所述第二開口中以及所述第一凹陷中沈積第二晶種層；以及 於所述第二晶種層上鍍覆第二導通孔，所述第二導通孔延伸至所述第一導通孔之所述第一凹陷中且穿過所述第二介電層，所述第二導通孔在所述第二導通孔的延伸穿過所述第二介電層的部分中具有第二凹陷。
  6. 如申請專利範圍第5項所述的半導體封裝的製造方法，其中所述第二晶種層具有處於第一平面中的第一部分及處於第二平面中的第二部分，其中所述第一介電層與所述第二介電層之間的第二界面處於第三平面中，以及其中所述第一平面接近所述積體電路晶粒，所述第二平面遠離所述積體電路晶粒，且所述第三平面在所述第一平面與所述第二平面之間。
  7. 如申請專利範圍第5項所述的半導體封裝的製造方法，其中所述第二晶種層沿所述第二介電層之頂部表面、所述第二開口之側面、所述第一導通孔之最頂部表面、定義所述第一凹陷之側面的所述第一導通孔之部分以及定義所述第一凹陷之底部的所述第一導通孔之部分延伸。
  8. 如申請專利範圍第5項所述的半導體封裝的製造方法，其中所述第二介電層與所述第二晶種層之間的界面為非平面的。
  9. 如申請專利範圍第5項所述的半導體封裝的製造方法，更包括： 在所述第二介電層及所述第二導通孔上方沈積第三介電層； 圖案化所述第三介電層，以在所述第三介電層中形成第三開口，所述第三開口暴露所述第二導通孔之所述第二凹陷； 在所述第三介電層上方、所述第三開口中以及所述第二凹陷中沈積第三晶種層；以及 於所述第三晶種層上鍍覆第三導通孔，所述第三導通孔延伸至所述第二導通孔之所述第二凹陷中且穿過所述第三介電層。
  10. 如申請專利範圍第9項所述的半導體封裝的製造方法，其中所述第二導通孔延伸穿過所述第二介電層，且至少部分地延伸至所述第一介電層及所述第三介電層中。
  11. 如申請專利範圍第9項所述的半導體封裝的製造方法，更包括： 將積體被動元件附接至所述第三導通孔。
  12. 如申請專利範圍第9項所述的半導體封裝的製造方法，其中將所述第三導通孔鍍覆於所述第二晶種層上是以間隙填充鍍覆製程執行。
  13. 如申請專利範圍第12項所述的半導體封裝的製造方法，其中所述間隙填充鍍覆製程包括以2.0 A/dm2 至6.0 A/dm2 之鍍覆電流密度且電鍍溶液包括硫酸銅所執行的鍍覆製程。
  14. 如申請專利範圍第5項所述的半導體封裝的製造方法，其中將所述第二導通孔鍍覆於所述第二晶種層上是以共形鍍覆製程執行。
  15. 如申請專利範圍第14項所述的半導體封裝的製造方法，其中所述共形鍍覆製程包括以0.3 A/dm2 至0.9 A/dm2 之鍍覆電流密度且電鍍溶液包括硫酸銅所執行的鍍覆製程。
  16. 一種半導體封裝的製造方法，包括 將積體電路晶粒包封在模製化合物中，所述積體電路晶粒具有晶粒連接件； 在所述模製化合物上方沈積第一介電層； 圖案化所述第一介電層，以形成穿過所述第一介電層的第一開口； 在所述積體電路晶粒之所述晶粒連接件上的所述第一開口中形成第一導電柱； 在所述第一介電層上方沈積第二介電層； 圖案化所述第二介電層，以在所述第二介電層中形成第二開口，所述第二開口暴露出所述第一開口；以及 在所述第一開口及所述第二開口中形成第一導通孔，所述第一導通孔圍繞所述第一導電柱。
  17. 如申請專利範圍第16項所述的半導體封裝的製造方法，更包括： 在所述第二介電層上方沈積第三介電層； 圖案化所述第三介電層，以在所述第三介電層中形成第三開口，所述第三開口暴露所述第一導通孔； 在所述第一導電柱上的所述第三開口中形成第二導電柱； 在所述第三介電層上方沈積第四介電層； 圖案化所述第四介電層，以在所述第四介電層中形成第四開口，所述第四開口暴露所述第三開口；以及 在所述第三開口及所述第四開口中形成第二導通孔，所述第二導通孔圍繞所述第二導電柱。
  18. 如申請專利範圍第17項所述的半導體封裝的製造方法，更包括： 將積體被動元件附接至所述第二導通孔。
  19. 如申請專利範圍第17項所述的半導體封裝的製造方法，其中在沈積所述第三介電層之後，所述第一導通孔延伸穿過所述第一介電層以及所述第二介電層，且部分地進入所述第三介電層中。
  20. 如申請專利範圍第17項所述的半導體封裝的製造方法，其中所述第二導通孔經形成而更圍繞所述第一導電柱。
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