TW201923915A - 半導體封裝及其製造方法 - Google Patents

半導體封裝及其製造方法 Download PDF

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Publication number
TW201923915A
TW201923915A TW107120385A TW107120385A TW201923915A TW 201923915 A TW201923915 A TW 201923915A TW 107120385 A TW107120385 A TW 107120385A TW 107120385 A TW107120385 A TW 107120385A TW 201923915 A TW201923915 A TW 201923915A
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Taiwan
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dielectric layer
metallization pattern
layer
width
semiconductor package
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TW107120385A
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English (en)
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TWI708291B (zh
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黃子松
林修任
蔡豪益
曾明鴻
江宗憲
郭庭豪
林彥良
Original Assignee
台灣積體電路製造股份有限公司
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Publication of TWI708291B publication Critical patent/TWI708291B/zh

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Abstract

在一實施例中，半導體封裝包括背側重佈線結構。背側重佈線結構包括位於第一介電層上的金屬化圖案以及位於金屬化圖案上的第二介電層。半導體封裝更包括：穿孔，延伸穿過第一介電層到接觸於金屬化圖案；積體電路晶粒，相鄰於第一介電層上的穿孔；模製化合物，位於第一介電層上，模製化合物包封穿孔和積體電路晶粒；導電連接件，延伸穿過第二介電層至接觸於金屬化圖案，導電連接件電連接至穿孔；以及金屬間化合物，位於導電連接件和金屬化圖案的界面，金屬間化合物僅部分延伸到金屬化圖案中。

Description

半導體封裝及其製造方法
由於各種電子元件（如電晶體、二極體、電阻器、電容器等）積集度的不斷提高，半導體產業經歷了快速發展。主要來說，積集度的改進是由最小特徵尺寸的迭代縮減導致的，這允許更多的元件被整合到給定的區域中。隨著對電子元件進行微縮的需求不斷增長，對半導體晶粒的更小且更具創造性的封裝技術的需求也出現了。這種封裝系統的一個實例是層疊封裝（package-on-package，POP）技術。在疊層封裝元件中，頂部半導體封裝堆疊在底部半導體封裝頂部上，以提供高水平的積集度和元件密度。層疊封裝技術通常可以在印刷電路板（PCB）上製造高效能且小面積的半導體元件。
以下揭露內容提供用於實作所提供主題的不同特徵的諸多不同的實施例或實例。以下闡述組件、值、操作、材料、排列等的具體實例以簡化本發明。當然，該些僅為實例且不旨在進行限制。預期存在其他組件、值、操作、材料、排列等。舉例而言，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本發明可能在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的，但自身並不表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「位於…之下（beneath）」、「下面（below）」、「下部的（lower）」、「上方（above）」、「上部的（upper）」等空間相對性用語來闡述圖中所示一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外亦囊括裝置在使用或操作中的不同定向。設備可具有其他定向（旋轉90度或處於其他定向）且本文中所使用的空間相對性描述語可同樣相應地進行解釋。
根據一些實施例，形成導電連接件以將元件封裝接合至重佈線結構的金屬化圖案。開口經形成以暴露出金屬化圖案，且導電連接件形成於開口中。隨後，導電連接件回流以將金屬化圖案接合至元件封裝。藉由控制開口的寬度以及導電連接件的寬度，可控制在回流期間形成的金屬間化合物的厚度。特別來說，金屬間化合物的厚度可控制為小於金屬化圖案的厚度。因此，可避免在測試期間下伏的晶種層發生分層。
圖1至圖16示出了根據一些實施例的在用於形成第一封裝200的製程期間的中間步驟的剖視圖。圖1至圖16示出了第一封裝區600和第二封裝區602，第一封裝200形成在每個封裝區中。第一封裝200也可以稱為積體扇出（InFO）封裝。
在圖1中，提供承載基底100，並且在承載基底100上形成離型層102。承載基底100可以是玻璃承載基底、陶瓷承載基底等。承載基底100可以是晶圓，以使得承載基底100上可以同時形成多個封裝。離型層102可以由聚合物系材料形成，該聚合物系材料可與承載基底100一起自隨後步驟中形成的上覆結構移除。在一些實施例中，離型層102是一種環氧樹脂系的熱離型材料，其在加熱時失去黏著性。熱離型材料例如是光熱轉化（LTHC）離型塗層。在其他實施例中，離型層102可以是紫外光（UV）膠，當暴露於UV光線時失去黏著性。離型層102可為液體而被分配並固化，可以是層壓到承載基底100上的層壓膜，或者可為類似者。離型層102的頂面可以被平整化，並且可以具有高度的共面性（coplanarity）。
在圖2中，形成介電層104、金屬化圖案106（有時稱為重佈線層或重分佈線）和介電層108。介電層104形成在離型層102上。介電層104的底面可以與離型層102的頂面接觸。在一些實施例中，介電層104由聚苯並噁唑（PBO）、聚乙醯胺、苯並環丁烯（BCB）等聚合物形成。在其他實施例中，介電層104由：諸如氮化矽的氮化物；諸如氧化矽、磷矽酸玻璃（PSG），硼矽玻璃（BSG）、硼摻雜磷矽酸玻璃（BPSG）等氧化物；或類似者而形成。介電層104可以由任何可接受的沉積製程形成。上述的沉積製程例如是旋轉塗佈、化學氣相沉積（CVD）、層壓等，或其組合。
在介電層104上形成金屬化圖案106。作為形成金屬化圖案106的例子，在介電層104上形成晶種層（未示出）。在一些實施例中，晶種層是金屬層，其可以是單層或由不同材料形成的多個子層組成的複合層。在一些實施例中，晶種層包含鈦層和在鈦層上的銅層。晶種層可以使用例如物理氣相沉積（physical vapor deposition，PVD）法等形成。然後在晶種層上形成光阻並將其圖案化。光阻可以通過旋轉塗佈等方法形成，並且可以暴露於光線以進行圖案化。光阻圖案對應於金屬化圖案106。經圖案化而形成的開口穿過光阻且暴露出晶種層。在光阻的開口處和晶種層的暴露部分上形成導體材料。導電材料可以通過例如是電鍍或無電鍍等鍍覆製程形成。導電材料可以包括金屬，如銅、鈦、鎢、鋁等。然後，去除光阻以及上方未形成導電材料的部分的晶種層。光阻可以通過可接受的灰化或剝離製程來去除，例如使用氧電漿等。一旦去除光阻，例如通過使用可接受的蝕刻製程（諸如通過濕法或乾式蝕刻）去除晶種層的暴露部分。晶種層的剩餘部分和導電材料構成金屬化圖案106。
在金屬化圖案106和介電層104上形成介電層108。在一些實施例中，介電層108由聚合物形成，該聚合物可為諸如PBO、聚乙醯胺、BCB等的光敏材料，且此光敏材料可藉由使用微影罩幕而圖案化。在其他實施例中，介電層108由：諸如氮化矽的氮化物；如氧化矽、PSG、BSG、BPSG的氧化物；或類似者形成。介電層108可以通過旋轉塗佈、疊層、CVD等或其組合的方法來形成介電層108。隨後，圖案化介電層108以形成開口，以暴露部分金屬化圖案106。圖案化可以通過可接受的製程來實施，例如當介電層108是光敏材料時，通過將介電層108暴露於光線，或通過使用例如非等向性蝕刻的蝕刻製程來對介電層108進行圖案化。
介電層104、介電層108以及金屬化圖案106可以被稱為背側重佈線結構110。在所示實施例中，背側重佈線結構110包括兩層介電層（介電層104和介電層108）以及一層金屬化圖案106。在其他實施例中，背側重佈線結構110可以包括任何數量的介電層、金屬化圖案和導通孔。通過重複進行形成金屬化圖案106和介電層108的製程，可以在背側重佈線結構110中形成一個或多個額外的金屬化圖案和介電層。導通孔（未示出）可通過在形成金屬化圖案的期間在下伏的介電層的開口中形成金屬化圖案的晶種層和導電材料而形成。導通孔可因此可以與各種金屬化圖案內連並電耦接。
在圖3中，形成穿孔112。作為形成穿孔112的例子，在背側重佈線結構110上形成晶種層113（如下所示於圖18中），例如在介電層108和金屬化圖案106的被開口109暴露的部分上形成晶種層113。在一些實施例中，晶種層113是金屬層，其可以是單層或由不同材料形成的多個子層組成的複合層。在一些實施例中，晶種層113包含鈦層和在鈦層上的銅層。晶種層113可以使用例如PVD等方法形成。在晶種層113上形成光阻，並圖案化光阻。光阻可以通過旋轉塗佈等方法形成，並且可以使光阻暴露於光線而進行圖案化。光阻圖案對應於穿孔（through vias）。經圖案化而形成的開口穿過光阻，以暴露出晶種層113。在光阻的開口處和晶種層113的暴露部分上形成導體材料。導電材料可以通過如電鍍或無電鍍等鍍覆製程形成。導電材料可以包括金屬，如銅、鈦、鎢、鋁等。去除光阻以及上方未形成導電材料的部分的晶種層113。光阻可以通過可接受的灰化或剝離製程（例如使用氧電漿等）來去除。一旦去除光阻，例如通過使用可接受的蝕刻製程（諸如通過濕法或乾式蝕刻）去除晶種層113的暴露部分。晶種層113的剩餘部分和導電材料形成穿孔112。
在圖4中，通過黏著劑116而將積體電路晶粒114黏附到介電層108上。積體電路晶粒114可以是邏輯晶粒（例如中央處理單元與微控制器等）、記憶體晶粒（例如動態隨機存取記憶體（DRAM）晶粒以及靜態隨機存取記憶體（SRAM）晶粒等）、功率管理晶粒（例如電源管理積體電路（PMIC）晶粒）、射頻（射頻）晶粒、感測器晶粒、微機電系統（MEMS）晶粒、訊號處理晶粒（例如數位訊號處理（DSP）晶粒）、前端晶粒（例如類比前端（AFE）晶粒）等或其組合。另外，在一些實施例中，多個積體電路晶粒114可以是不同的尺寸（例如，不同的高度及/或表面積），並且在其他實施例中，多個積體電路晶粒114可以是相同的尺寸（例如，相同的高度及/或表面積）。
在貼附於介電層108之前，可依照適用的製造製程進行處理，以在積體電路晶粒114中形成積體電路。例如，積體電路晶粒114各自包括半導體基底118，例如是經摻雜或未經摻雜的矽或絕緣體上覆半導體（SOI）基底的主動層。半導體基底可以包括其他半導體材料，例如：鍺；包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦的化合物半導體；包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP的合金半導體；或其組合。在一些實施例中，也可使用如多層基底或梯度基底的其他基底。在半導體基底118中及/或半導體基底118上可以形成元件（例如電晶體、二極體、電容器、電阻器等）。並且可以通過例如在半導體基底118上的一個或多個介電層中藉由金屬化圖案所形成的內連線結構120而對元件進行互連，從而形成積體電路。
積體電路晶粒114還包括接墊122，例如鋁接墊。可在接墊122上形成外部連接。接墊122位於可被稱為積體電路晶粒114的相應主動側的區域上。保護膜124位於積體電路晶粒114上並且位於部分的接墊122上。開口穿過保護膜124而到接墊122。晶粒連接件126，諸如導電支柱（例如包括銅之類的金屬）位於穿過保護膜124的開口中，並且機械和電性地耦接到相應的接墊122。晶粒連接件126可以通過例如電鍍等方法形成。晶粒連接件126電耦接於積體電路晶粒114的相應積體電路。
介電材料128位於積體電路晶粒114的主動側上，如位於保護膜124和晶粒連接件126上。介電材料128側向地包封晶粒連接件126，且介電材料128側向地與相應的積體電路晶粒114相接。介電材料128可以是如PBO、聚乙醯胺、BCB等的聚合物；諸如氮化矽等的氮化物；如氧化矽、PSG、BSG、BPSG等的氧化物；類似者或其組合。介電材料128可以通過例如是旋轉塗佈、疊層、CVD等方法形成。
黏著劑116位於積體電路晶粒114的背面，並將積體電路晶粒114黏附至背側重佈線結構110（例如是介電層108）。黏著劑116可以是任何適合的黏著劑、環氧樹脂、晶粒貼合膜（die attach film，DAF）等。黏著劑116可以施加到積體電路晶粒114的背面，例如施加到相應的半導體晶圓的背面，或者可以施加在承載基底100的表面上。積體電路晶粒114可以例如通過鋸切或切割進行單體化，並且通過使用例如拾放工具將積體電路晶粒114藉由黏著劑116黏附到介電層108上。
儘管圖示中第一封裝區600與第二封裝區602的每一者中黏附兩個積體電路晶粒114，應可了解每一封裝區中可黏附更多或更少的積體電路晶粒114。舉例而言，各區中可僅黏附一個積體電路晶粒114。此外，可改變積體電路晶粒114的尺寸。在一些實施例中，積體電路晶粒114可為具有較大佔據面積（footprint）的晶粒（例如是系統晶片（system-on-chip）元件）。在積體電路晶粒114具有大的佔據面積的實施例中，用於穿孔112的空間可受到限制。在封裝區的用於穿孔112的空間受限時，使用背側重佈線結構110可改良內連線的配置。
在圖5中，將包封體130形成在各種部件上。包封體130可以是模製化合物、環氧樹脂等，且可以通過壓縮成型（compression molding）、轉注成型（transfer molding）等來施加。包封體130可以形成在承載基底100上，使得積體電路晶粒114的穿孔112及/或晶粒連接件126埋入於或覆蓋於包封體130中。隨後，固化包封體130。
在圖6中，在包封體130上執行平坦化製程，以暴露出穿孔112和晶粒連接件126。平坦化製程也可研磨介電材料128。在平坦化製程之後，穿孔112、晶粒連接件126、介電材料128和包封體130的頂面共面。平坦化製程可以是例如化學機械研磨（CMP）、研磨（grinding）製程等。在一些實施例中，例如，如果穿孔112和晶粒連接件126已經暴露出來，則可以省略平坦化製程。
在圖7至14中，形成前側重佈線結構132。如下所述，前側重佈線結構132包括介電層134、介電層140、介電層146和介電層152，並且還包括金屬化圖案138、金屬化圖案144和金屬化圖案150。金屬化圖案也可稱為重佈線層或重分佈線，且包括導通孔和導線（未單獨標註）。
在圖7中，在包封體130、穿孔112和晶粒連接件126上沉積介電層134。在一些實施例中，介電層134由聚合物形成，該聚合物可以是諸如PBO、聚乙醯胺、BCB等的光敏材料，且此光敏材料可藉由使用微影罩幕而圖案化。在其他實施例中，介電層134由：諸如氮化矽的氮化物；如氧化矽、PSG、BSG、BPSG的氧化物；或類似者形成。介電層134可以通過旋轉塗佈、疊層、CVD等或其組合來形成。
隨後，圖案化介電層134。圖案化介電層134所形成的開口136暴露出穿孔112和部分的晶粒連接件126。圖案化可以通過可接受的製程來實施，例如當介電層134是光敏材料時，通過將介電層134暴露於光線，或通過使用例如非等向性蝕刻的蝕刻製程來對介電層108進行圖案化。如果介電層134是光敏材料，則介電層134可以在曝光之後被顯影。
在圖8中，在介電層134上形成具有通孔的金屬化圖案138。作為形成金屬化圖案138的示例，在介電層134上方和穿過介電層134的開口136中形成晶種層（未示出）。在一些實施例中，晶種層是金屬層，其可以是單層或由不同材料形成的多個子層組成的複合層。在一些實施例中，晶種層包含鈦層和在鈦層上的銅層。晶種層可以使用例如PVD等方法形成。隨後，在晶種層上形成光阻並將其圖案化。光阻可以通過旋轉塗佈等方法形成，並且可以暴露於光線以進行圖案化。光阻圖案對應於金屬化圖案138。圖案化光阻所形成的開口穿過光阻，以曝露出晶種層。在光阻的開口處和晶種層的暴露部分上形成導體材料。導電材料可以通過例如是電鍍或無電鍍等鍍覆製程來形成。導電材料可以包括金屬，如銅、鈦、鎢、鋁等。接著，去除光阻以及上方未形成導電材料的部分的晶種層。光阻可以通過可接受的灰化或剝離製程來去除，例如使用氧電漿等。一旦去除光阻，例如通過使用可接受的蝕刻製程（諸如通過濕法或乾式蝕刻）去除晶種層的暴露部分。晶種層的剩餘部分和導電材料構成金屬化圖案138和通孔。通孔形成在開口136中，穿過介電層134而到達例如是穿孔112及/或晶粒連接件126。
在圖9中，在金屬化圖案138和介電層134上沉積介電層140。在一些實施例中，介電層140由聚合物形成，該聚合物可以是諸如PBO、聚乙醯胺、BCB等的光敏材料，且此光敏材料可藉由使用微影罩幕而圖案化。在其他實施例中，介電層140由：諸如氮化矽的氮化物；如氧化矽、PSG、BSG、BPSG的氧化物；或類似者形成。介電層140可以通過旋轉塗佈、疊層、CVD等或其組合的方法來形成。
之後，圖案化介電層140。圖案化介電層140所形成的開口142暴露出部分金屬化圖案138。圖案化可以通過可接受的製程來實施，例如當介電層140是光敏材料時通過將介電層140暴露於光線，或通過使用例如非等向性蝕刻的蝕刻製程來對介電層140進行圖案化。如果介電層140是光敏材料，則介電層140可以在曝光之後被顯影。
在圖10中，在介電層140上形成具有通孔的金屬化圖案144。作為形成金屬化圖案144的示例，在介電層140上和穿過介電層140的開口142中形成晶種層（未示出）。在一些實施例中，晶種層是金屬層，其可以是單層或由不同材料形成的多個子層組成的複合層。在一些實施例中，晶種層包含鈦層和在鈦層上的銅層。晶種層可以使用例如PVD等方法形成。然後在晶種層上形成光阻並將其圖案化。光阻可以通過旋轉塗佈等方法形成，並且可以暴露於光線以進行圖案化。光阻圖案對應於金屬化圖案144。經圖案化而形成的開口穿過光阻且曝露出晶種層。在光阻的開口處和晶種層的暴露部分上形成導體材料。導電材料可以通過如電鍍或無電鍍等鍍覆製程形成。導電材料可以包括金屬，如銅、鈦、鎢、鋁等。然後，去除光阻以及上方未形成導電材料的部分的晶種層。光阻可以通過可接受的灰化或剝離製程來去除，例如使用氧電漿等。一旦去除光阻，例如通過使用可接受的蝕刻製程（諸如通過濕法或乾式蝕刻）去除晶種層的暴露部分。晶種層的剩餘部分和導電材料構成金屬化圖案144和通孔。通孔形成在開口142中，穿過介電層140而到達例如是部分的金屬化圖案138。
在圖11中，在金屬化圖案144和介電層140上沉積介電層146。在一些實施例中，介電層146由聚合物形成，該聚合物可以是諸如PBO、聚乙醯胺、BCB等的光敏材料，且此光敏材料可藉由使用微影罩幕而圖案化。在其他實施例中，介電層146由：諸如氮化矽的氮化物；如氧化矽、PSG、BSG、BPSG的氧化物；或類似者形成。介電層146可以通過旋轉塗佈、疊層、CVD等或其組合的方法來形成。
隨後，圖案化介電層146。圖案化介電層146所形成的開口148暴露出部分金屬化圖案144。圖案化可以通過可接受的製程來實施，例如當介電層146是光敏材料時通過將介電層146暴露於光線，或通過使用例如非等向性蝕刻的蝕刻製程來對介電層108進行圖案化。如果介電層146是光敏材料，則介電層146可以在曝光之後被顯影。
在圖12中，在介電層146上形成具有通孔的金屬化圖案150。作為形成金屬化圖案150的例子，在介電層146上和穿過介電層146的開口148中形成晶種層（未示出）。在一些實施例中，晶種層是金屬層，其可以是單層或由不同材料形成的多個子層組成的複合層。在一些實施例中，晶種層包含鈦層和在鈦層上的銅層。晶種層可以使用例如PVD等方法形成。之後，在晶種層上形成光阻並將其圖案化。光阻可以通過旋轉塗佈等方法形成，並且可以暴露於光線以進行圖案化。光阻圖案對應於金屬化圖案150。圖案化光阻所形成的開口穿過光阻，以曝露出晶種層。在光阻的開口處和晶種層的暴露部分上形成導體材料。導電材料可以通過如電鍍或無電鍍等鍍覆製程來形成。導電材料可以包括金屬，如銅、鈦、鎢、鋁等。然後，去除光阻以及未形成導電材料於其上的晶種層的部分。光阻可以通過可接受的灰化或剝離製程來去除，例如使用氧電漿等。一旦去除光阻，例如通過使用可接受的蝕刻製程（諸如通過濕法或乾式蝕刻）去除晶種層的暴露部分。晶種層的剩餘部分和導電材料構成金屬化圖案150和通孔。通孔形成在開口中，穿過介電層146而到達例如部分的金屬化圖案144。
在圖13中，在金屬化圖案150和介電層146上沉積介電層152。在一些實施例中，介電層152由聚合物形成，該聚合物可以是諸如PBO、聚乙醯胺、BCB等的光敏材料，且此光敏材料可藉由使用微影罩幕而圖案化。在其他實施例中，介電層152由：諸如氮化矽的氮化物；如氧化矽、PSG、BSG、BPSG的氧化物；或類似者形成。介電層152可以通過旋轉塗佈、疊層、CVD等或其組合的方法來形成。
之後，圖案化介電層152。圖案化介電層152所形成的開口154暴露出部分金屬化圖案150。圖案化可以通過可接受的製程來實施，例如當介電層152是光敏材料時通過將介電層152暴露於光線，或通過使用例如非等向性蝕刻的蝕刻製程來對介電層152進行圖案化。如果介電層152是光敏材料，則介電層152可以在曝光之後被顯影。開口154可以比開口136、開口142、開口148更寬。
在圖14中，在介電層152上形成凸塊下金屬（under bump metallurgy，UBM） 156。在所示的實施例中，所形成的UBM 156穿過開口154且接觸於金屬化圖案150，其中開口154穿過介電層152。作為形成UBM 156的例子，在介電層152上形成晶種層（未示出）。在一些實施例中，晶種層是金屬層，其可以是單層或由不同材料形成的多個子層組成的複合層。在一些實施例中，晶種層在包含鈦層和鈦層上的銅層。晶種層可以使用例如PVD等方法形成。然後在晶種層上形成光阻並將其圖案化。光阻可以通過旋轉塗佈等方法形成，並且可以暴露於光線以進行圖案化。光阻的圖案對應於UBM 156。經圖案化的光阻所形成的開口穿過光阻且曝露出晶種層。在光阻的開口處和晶種層的暴露部分上形成導體材料。導電材料可以通過如電鍍或無電鍍等鍍覆製程形成。導電材料可以包括金屬，如銅、鈦、鎢、鋁等。然後，去除光阻以及未形成導電材料於其上的晶種層的部分。光阻可以通過可接受的灰化或剝離製程來去除，例如使用氧電漿等。一旦去除光阻，例如通過使用可接受的蝕刻製程（諸如通過濕法或乾式蝕刻）去除晶種層的暴露部分。晶種層的剩餘部分和導電材料形成UBM 156。在以不同方式形成UBM 156的實施例中，可以使用更多的光阻和圖案化步驟來形成UBM 156。
前側重佈線結構132係作為一示例。在前側重佈線結構132中可以形成更多或更少的介電層和金屬化圖案。如果形成更少的介電層和金屬化圖案，則可以省略上述的一些步驟和製程。如果形成更多的介電層和金屬化圖案，可以重複進行如上所述的步驟和製程。所屬領域中具有通常知識者將容易地理解哪個步驟和製程將被省略或重複。
在圖15中，在UBM 156上形成導電連接件158。導電連接件158可以是球柵陣列（ball grid array，BGA）連接件、焊球、金屬柱、受控塌陷晶片連接（controlled collapse chip connection，C4）凸塊、微凸塊、化鎳鈀浸金（electroless nickel-electroless palladium-immersion gold，ENEPIG）形成的凸塊等。導電連接件158可以包括諸如焊料、銅、鋁、金、鎳、銀、鈀、錫等等的導電材料或其組合。在一些實施例中，導電連接件158的形成方法包括先藉由如蒸鍍、電鍍、印刷、焊料轉移、植球等常用方法形成焊料層。一旦在結構上形成了一層焊料，就可以進行回流以便將材料成形為所需的凸塊形狀。在另一個實施例中，導電連接件158是通過濺射、印刷、電鍍、化學鍍、CVD等方法形成的金屬柱（例如銅柱）。金屬柱可以不含焊料，並具有實質上垂直側壁。在一些實施例中，在金屬柱的頂部上形成金屬頂蓋層（未示出）。金屬頂蓋層可以包括鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金等或其組合，並且可以通過鍍覆製程形成。
在圖16中，執行承載基底分離，以將承載基底100從背側重佈線結構110（例如背側重佈線結構110的介電層104）分離（去接合）。藉此在第一封裝區600和第二封裝區602中的每一者中形成第一封裝200。根據一些實施例，去接合包括在離型層102上投射光線（諸如雷射光線或UV光線），使得離型層102在光線的熱量下分解並且使得承載基底100可以被移除。隨後，將結構翻轉並放置在膠帶160上。此外，形成穿過介電層104的開口162，以暴露出部分金屬化圖案106。開口162可以例如使用雷射鑽孔、蝕刻等方法來形成。
圖17至圖20示出了根據一些實施例的在用於形成封裝結構500的製程期間的中間步驟的剖視圖。封裝結構500可以被稱為疊層封裝（packge-on-package，PoP）結構。
在圖17中，第二封裝300附接到第一封裝200。第二封裝300包括基底302和耦接到基底302的一個或多個堆疊晶粒308（包括晶粒308A和晶粒308B）。儘管示出了堆疊晶粒308（包括晶粒308A和晶粒308B）的單一堆疊，但在其他實施例中，多個堆疊晶粒308（各自具有一個或多個堆疊晶粒）可以並排地（side by side）耦接到基底302的同一表面。基底302可以由諸如矽、鍺、金剛石等半導體材料製成。在一些實施例中，也可以使用諸如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、矽鍺碳化物、磷化砷鎵、磷化銦鎵、其組合等化合物材料。另外，基底302可以是絕緣體上覆矽（SOI）基底。一般而言，SOI基底包括半導體材料層，諸如磊晶矽、鍺、矽鍺、SOI、絕緣體上覆矽鍺（silicon germanium-on-insulator，SGOI）或其組合。在一個替代實施例中，基底302是基於諸如玻璃纖維增強樹脂芯的絕緣芯。芯材料的一個實例是玻璃纖維樹脂，例如FR4。芯材料的替代品包括雙馬來醯亞胺-三嗪（bismaleimide-triazine，BT）樹脂，或者其他印刷電路板（PCB）材料或膜。基底302可以使用味之素增層膜（Ajinomoto build-up film，ABF）或其他層壓材料。
基底302可以包括主動元件和被動元件（未示出）。如所屬領域中具有通常知識者所認知，可以使用諸如電晶體、電容器、電阻器、其組合等的各種元件來產生對於第二封裝300的結構上與功能上的要求。上述元件可以使用任何合適的方法形成。
基底302還可以包括金屬化層（未示出）和穿孔306。金屬化層可以形成在主動元件和被動元件上，並且被設計成連接各種元件以形成功能電路。金屬化層可以由交替堆疊的介電質（例如低介電材料）和導電材料（例如銅）形成，其中通孔互連導電材料層。金屬化層可以通過任何合適的製程（例如沉積、鑲嵌、雙鑲嵌等）形成。在一些實施例中，基底302是實質上不具有主動元件和被動元件的。
基底302可在基底302的第一側上具有接合接墊303以耦接至堆疊晶粒308，並且在基底302的第二側上具有接合接墊304以耦接至導電連接件314。基底302的第二側與第一側相對。在一些實施例中，通過在基底302的第一側和第二側上的介電層（未示出）中形成凹槽（未示出）而形成接合接墊303和接合接墊304。凹槽可以形成為可允許接合接墊303和接合接墊304被嵌入到介電層中。在其他實施例中，由於可以在介電層上形成接合接墊303和接合接墊304，故可省去形成凹槽。在一些實施例中，接合接墊303和接合接墊304包括由銅、鈦、鎳、金、鈀等或其組合製成的薄晶種層（未示出）。接合接墊303和接合接墊304的導電材料可以沉積在薄晶種層上。導電材料可以通過電化學鍍覆製程、無電鍍製程、CVD、原子層沉積（atomic layer deposition，ALD）、PVD等或其組合的方法來形成。在一個實施例中，接合接墊303和接合接墊304的導電材料是銅、鎢、鋁、銀、金等或其組合。
在一個實施例中，接合接墊303和接合接墊304是包括三層導電材料（例如鈦層、銅層和鎳層）的UBM。舉例而言，接合接墊304可由銅或鈦（未示出）形成，且可具有鎳表面處理（nickel finish）305。鎳表面處理305可改進元件封裝（第二封裝）300的儲放壽命（shelf life）。當元件封裝（第二封裝）300為例如是動態隨機存取記憶體（dynamic random access memory，DRAM）的記憶體元件時，改進元件封裝（第二封裝）300的儲放壽命是特別有益的。然而，所屬領域中具有通常知識者將會認識到材料和層具有許多合適的配置。舉例而言，適用於形成接合接墊303和接合接墊304的排列包括鉻/鉻銅合金/銅/金的排列、鈦/鈦鎢/銅的排列或銅/鎳/金的排列。可以用於接合接墊303和接合接墊304的任何合適的材料或材料層皆屬於在本申請的範疇。在一些實施例中，穿孔306延伸穿過基底302並且將至少一個接合接墊303耦接到至少一個接合接墊304。
在所示實施例中，堆疊晶粒308通過打線310與基底302耦接，但也可以使用其他連接，例如導電凸塊，以使堆疊晶粒308與基底302耦接。在一個實施例中，堆疊晶粒308是堆疊記憶體晶粒。舉例而言，堆疊晶粒308可以是低功率（low-power，LP）雙倍資料速率（double data rate，DDR）記憶體模組的記憶體晶粒，低功率雙倍資料速率記憶體模組例如是LPDDR1、LPDDR2、LPDDR3、LPDDR4或其類似的記憶體模組。如上所述，在此些實施例中，接合接墊304可具有鎳表面處理305。
堆疊晶粒308和打線310可以藉由模製材料312包封。模製材料312可以例如使用壓縮模製而模製於堆疊晶粒308和打線310上。在一些實施例中，模製材料312是模製化合物、聚合物、環氧樹脂、氧化矽填充材料等、或其組合。可以執行固化製程以固化模製材料312。固化製程可以是熱固化、UV固化等、或其組合。
在一些實施例中，堆疊晶粒308和打線310被埋入於模製材料312中。並且在模製材料312固化之後，執行平坦化步驟（例如研磨），以移除模製材料312的多餘部分並且為第二封裝300提供實質上平整的表面。
在形成第二封裝300之後，通過導電連接件314、接合接墊304和金屬化圖案106將第二封裝300機械地和電性地接合到第一封裝200。在一些實施例中，堆疊晶粒308可通過打線接合310、接合接墊303和接合接墊304、穿孔306、導電連接件314和穿孔112將耦接到積體電路晶粒114。圖18A至圖18C是示出用於將第一封裝200和第二封裝300接合於導電連接件314的製程期間的區650的放大剖視圖。
在圖18A中，在各個開口162中且被暴露出的金屬化圖案106上形成可回流層402。可回流層402可以是焊料層（有時稱為預焊料層）、焊膏等。在一個實施例中，可回流層402是含銅的預焊料材料，例如是錫銅、錫銀銅等或其組合。此外，可回流層402可以被印刷到暴露出的金屬化圖案106上，但是也可以使用其他製程，例如電鍍或無電鍍形成可回流層402。可回流層402的銅濃度可以為約5％至約10％。在一些實施例中，可回流層402完全填充或溢出（overfill）開口162，並且在其他實施例中，可回流層402僅部分填充開口162。開口162經形成具有寬度W1 ，寬度W1 為約230 μm至約260 μm，例如約250 μm。如此一來，每個開口162中的可回流層402的部分也具有寬度W1 。
在圖18B中，在可回流層402上與背側重佈線結構110的背側形成可回流連接件404。可回流連接件404可以類似於導電連接件158。舉例而言，形成可回流連接件404的方法可包括初始地通過諸如蒸鍍、電鍍、印刷、焊料轉移、植球等常用方法形成焊料層。一旦在結構上形成了一層焊料，可進行回流以便將材料成形為所需的凸塊形狀。可回流連接件404實質上不包含銅，或包含非常少量的銅。特別來說，可回流層402的銅濃度大於可回流連接件404的銅濃度。形成之後，可回流連接件404的寬度W2 為約250 μm至約320 μm，例如大約300 μm。
在一些實施例中，在形成之後，塗覆助焊劑（未示出）於可回流連接件404，助焊劑例如是免清潔助焊劑。可回流連接件404可浸入助焊劑中，或助焊劑可噴射到可回流連接件404上。在另一實施例中，助焊劑可施加於金屬化圖案106的表面。
在圖18C中，執行回流製程以通過例如焊料接合將第二封裝300接合到第一封裝200。在回流製程期間，可回流層402和可回流連接件404回流，以形成導電連接件314。在回流製程之後，可回流層402和可回流連接件404可能混合，並且不能清晰地可見分離的結構。在此回流製程期間，導電連接件314接觸於接合接墊304和金屬化圖案106，以將第二封裝300物理性和電性地耦接到第一封裝200。導電連接件314可以設置在基板302的與堆疊晶粒308相對的一側的開口162中。在接合製程之後，在導電連接件314和接合接墊304之間的界面可能形成金屬間化合物（IMC）（未示出）。在金屬化圖案106和導電連接件314的界面處也會形成IMC 164。在形成之後，每個IMC 164的寬度W3 為約245 μm至約275 μm，例如約255 μm。IMC 164的寬度W3 小於導電連接件314的寬度W2 ，並且可大於開口162的寬度W1 。
在鎳表面處理305形成在接合接墊304上的實施例中，回流製程導致在形成IMC 164期間從金屬化圖案106消耗更多的銅。此外，由於鎳表面處理305充當阻擋層，故實質上沒有銅從接合接墊304消耗。如此，根據菲克定律（Fick’s law），在形成鎳表面處理305的實施例中，導電連接件314所含的銅具有梯度濃度。具體地，導電連接件314的銅濃度可以沿著從金屬化圖案106延伸到鎳表面精整305的方向減小。
IMC 164經形成以具有厚度T1 ，並且背側重佈線結構110的金屬化圖案106經形成以具有厚度T2 。如上所述，開口162經形成以具有寬度W1 ，並且可回流連接件404經形成以具有寬度W2 。形成開口162和可回流連接件404的製程條件被控制為使得寬度W2 與寬度W1 的比例在特定範圍內。將寬度W2 與寬度W1 的比例控制為允許控制IMC 164的厚度T1 。值得注意的是，寬度W1 與寬度W1 的比例被控制為使得厚度T1 比厚度T2 小，其中厚度T1 與厚度T2 的差值為厚度差T3 。在一實施例中，金屬化圖案106的厚度T2 可以從約6 μm至約10 μm，諸如約 7μm。在此實施例中，將寬度W2 與寬度W1 的比例限制為小於約1.53，可允許IMC 164的厚度T1 小於金屬化圖案106的厚度T2 。例如，IMC 164的厚度T1 可以小於約6.5 μm，例如約3 μm至約6 μm，並且厚度差T3 可以大於約0.5 μm，諸如從約1 μm至約2.5 μm。
在形成導電連接件314形成之後，可以測試第一封裝200和第二封裝300，以確定封裝的可靠度。測試製程可能會使封裝承受達到高程度的熱量。如果IMC 164經形成為完全通過金屬化圖案106，則在高溫測試期間可能發生晶種層113的分層。因此，儘管在回流期間可能形成可靠的連接，但在隨後的測試期間連接可能失效。
由於可回流層402的銅濃度大於可回流連接件404的銅濃度，並且因為可回流層402形成有約5 ％至約10 ％的銅濃度，所以導電連接件314可具有約0.55 重量％至約0.7 重量％的銅濃度，例如大於約0.5 重量％的銅濃度。此濃度可允許IMC 164形成，但可以減少回流期間從金屬化圖案106消耗的銅含量。減少從金屬化圖案106中消耗的銅含量可以允許一些純銅保留在部分的金屬化圖案106中，避免在測試期間晶種層113的分層。
通過形成IMC 164以具有小於金屬化圖案106的厚度T2 的厚度T1 ，在回流製程之後，一些銅保持設置在IMC 164與晶種層113之間。晶種層113與金屬化圖案106之間的附著力可以比晶種層113與IMC 164之間的附著力強。因此，通過形成IMC 164使其不會一直延伸至晶種層113，在測試過程中可以避免或減少晶種層113的分層。
在一些實施例中，也可以在基底302的與堆疊晶粒308相對的一側上形成焊料抗蝕劑。導電連接件314可以設置在焊料抗蝕劑的開口中，以與基底302中的導電特徵（例如，接合接墊304）電性耦接和機械耦接。焊料抗蝕劑可用於保護基底302的區域，免受外部損傷。
在一些實施例中，導電連接件314具有形成在其上方的環氧助焊劑（未示出），此環氧助焊劑可以在回流前形成。在第二封裝300附接到第一封裝200之後，導電連接件314回流，而環氧助焊劑的至少一些環氧部分殘留下來。
於第一封裝200與第二封裝300之間可形成底部填充件（未示出），且底部填充件圍繞導電連接件314。底部填充件可以減小應力並保護由導電連接件314的回流導致的接點（joint）。底部填充件可以在第一封裝200附接之後通過毛細管流動製程形成，或者可以在第一封裝200附接之前通過合適的沉積方法形成。在形成環氧助焊劑的實施例中，環氧助焊劑可以充當底部填充件。
通過沿切割道區（例如在第一封裝區600和第二封裝區602之間）鋸切以執行單體化製程。上述鋸切使第一封裝區600自第二封裝區602分離。所產生的單體化的第一封裝200和第二封裝300來自第一封裝區域600或第二封裝區域602中的一者。在一些實施例中，在將第二封裝300附接到第一封裝200之後執行單體化製程。在其他實施例中（未示出），在第二封裝300附接到第一封裝200之前執行單體化製程，例如在承載基底100被解除接合且形成開口178之後。
在圖20中，使用導電連接件158將第一封裝200安裝到封裝基底400。封裝基底400可以由諸如矽、鍺、金剛石等半導體材料製成。或者，也可以使用諸如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、矽鍺碳化合物、磷化砷鎵、磷化銦鎵及其組合等化合物材料。另外，封裝基底400可以是SOI基底。一般而言，SOI基底包括諸如磊晶矽、鍺、矽鍺、SOI、SGOI或其組合的半導體材料的層。在一個替代實施例中，封裝基底400是基於諸如玻璃纖維增強樹脂芯的絕緣芯。芯材料的一個例子是玻璃纖維樹脂，例如FR4。芯材料的替代品包括雙馬來酰亞胺三嗪BT樹脂，或者其他PCB材料或膜。封裝基底400可以使用積層膜，如ABF或其他層壓板。
封裝基底400可能包括主動元件和被動元件（未示出）。如所屬領域中具有通常知識者所認知，可以使用諸如電晶體、電容器、電阻器、其組合等的各種元件來產生對於封裝結構500的設計的結構和功能要求。上述元件可以使用任何合適的方法形成。
封裝基底400還可以包括金屬化層和通孔（未示出），且包括金屬化層和通孔上的接合接墊402。金屬化層可以形成在主動元件和被動元件上，並且被設計成連接各種元件以形成功能電路。金屬化層可以由交替堆疊的介電質（例如低介電常數介電材料）和導電材料（例如銅）形成，其中通孔互連導電材料層。金屬化層可以通過任何合適的製程（如沉積、鑲嵌、雙鑲嵌等）形成。在一些實施例中，封裝基底400實質上不含主動元件和被動元件。
在一些實施例中，導電連接件158經回流以將第一封裝200附接到接合接墊402。導電連接件158將封裝基底400電性地及/或物理性地耦接第一封裝200，包括將封裝基底400的金屬化層電性地及/或物理性地耦接至第一封裝200。在一些實施例中，在安裝到封裝基底400上之前，可以將被動元件（例如，表面安裝元件（SMD），未示出）附接至第一封裝200（例如，接合到接合接墊402）。在此實施例中，被動元件可以與導電連接158接合到第一封裝200的同一表面。
在導電連接件158回流之前，可在導電連接件158上形成環氧樹脂助焊劑。在第一封裝200被附接至封裝基底400之後，環氧樹脂助焊劑的至少一些環氧樹脂部分殘留下來。剩餘的環氧樹脂部分可作為底部填充件，以降低應力並保護由導電連接件158回流產生的接點（joint）。在一些實施例中，在第一封裝200與封裝基底400之間並圍繞導電連接件158可形成底部填充件（未示出）。底部填充件可以在第一封裝200附接之後通過毛細管流動製程形成，或者可以在第一封裝200附接之前通過合適的沉積方法形成。
實施例可以實現以下優點。控制寬度W2 對於寬度W1 的比值以小於1.53可使IMC 164的厚度能夠被控制。值得注意的是，藉由將IMC 164形成為具有比金屬化圖案106的厚度更小的厚度，一些銅可餘留在導電連接件314與晶種層113之間的金屬化圖案106中。因此，可避免或減少晶種層113在測試期間發生分層。
在一實施例中，半導體封裝包括：背側重佈線結構，包括位於第一介電層上的金屬化圖案以及位於所述金屬化圖案上的第二介電層；穿孔，延伸穿過所述第一介電層到接觸於所述金屬化圖案；積體電路晶粒，相鄰於所述第一介電層上的所述穿孔；模製化合物，位於所述第一介電層上，所述模製化合物包封所述穿孔和所述積體電路晶粒；導電連接件，延伸穿過所述第二介電層至接觸於所述金屬化圖案，所述導電連接件電連接至所述穿孔；以及金屬間化合物，位於所述導電連接件和所述金屬化圖案的界面，所述金屬間化合物僅部分延伸到所述金屬化圖案中。
在一些實施例中，所述金屬化圖案的厚度為約6 μm至約10 μm。在一些實施例中，所述金屬間化合物延伸至所述金屬化圖案中的距離小於約6.5 μm。在一些實施例中，所述導電連接件與所述穿孔之間的所述金屬化圖案的部分的厚度大於約0.5 μm。在一些實施例中，延伸穿過所述第二介電層的所述導電連接件的第一部分具有第一寬度，所述第二介電層外的所述導電連接件的第二部分具有第二寬度，所述第二寬度對於所述第一寬度的比值小於1.53。在一些實施例中，延伸通過所述第二介電層的所述導電連接件的第一部分具有第一寬度，所述金屬間化合物具有第二寬度，並且所述第二寬度大於所述第一寬度。在一些實施例中，所述金屬化圖案具有第三寬度，且所述第二寬度小於所述第三寬度。
在一實施例中，半導體封裝的製造方法包括：在第一介電層和第二介電層之間形成金屬化圖案；圖案化所述第一介電層以形成穿過所述第一介電層的第一開口，所述第一開口暴露出所述金屬化圖案的第一側；在所述第一開口中沉積晶種層；圖案化所述第二介電層以形成穿過所述第二介電層的第二開口，所述第二開口暴露出所述金屬化圖案的第二側；將導電連接件放置在所述金屬化圖案的所述第二側上的所述第二開口中；以及回流所述導電連接件，藉以在所述導電連接件和所述金屬化圖案的所述界面形成金屬間化合物，所述金屬化圖案將所述金屬間化合物自所述晶種層分離。
在一些實施例中，半導體封裝的製造方法更包括：將積體電路晶粒附著於所述第一介電層。在一些實施例中，半導體封裝的製造方法，更包括：形成包封所述積體電路晶粒的模製化合物；以及將導電材料鍍覆在所述晶種層上，所述導電材料延伸穿過所述模製化合物並至少部分地進入所述第一介電層。在一些實施例中，所述回流所述導電連接件，將第一基底接合至具有所述導電連接件的所述金屬化圖案的所述第二側。在一些實施例中，其中在所述回流後，所述導電連接件包括焊料和銅。在一些實施例中，所述導電連接件的銅具有梯度濃度，所述銅的所述梯度濃度沿著遠離所述金屬化圖案的方向遞減。在一些實施例中，延伸穿過所述第二介電層的所述導電連接件的第一部分具有第一寬度，在所述第二介電層外的所述導電連接件的第二部分具有第二寬度，並且所述第二寬度對於所述第一寬度的比值小於1.53。
在一實施例中，半導體封裝的製造方法包括：在第一介電層上形成金屬化圖案；在所述金屬化圖案和所述第一介電層上沉積第二介電層；形成延伸穿過所述第二介電層的穿孔以接觸所述金屬化圖案的第一側；在所述第一介電層蝕刻出第一開口，暴露所述金屬化圖案的第二側；在所述第一開口中印刷第一可回流材料；以及在所述第一可回流材料上形成第二可回流材料，所述第一可回流材料和所述第二可回流材料包括不同濃度的導電材料；以及回流所述第一可回流材料和所述第二可回流材料，以形成延伸穿過所述第一介電層的導電連接件，以及在所述金屬化圖案和所述導電連接件的所述界面的金屬間化合物。
在一些實施例中，形成所述穿孔包括：在所述第二介電層中蝕刻出第二開口，暴露所述金屬化圖案的所述第一側；在所述第二開口中沉積晶種層；以及在所述晶種層上鍍覆導電材料，所述導電材料和所述晶種層形成所述穿孔。在一些實施例中，半導體封裝的製造方法，更包括：將積體電路晶粒附接到所述第二介電層，所述積體電路晶粒與所述穿孔相鄰；以及以模製化合物包封所述穿孔和所述積體電路晶粒。在一些實施例中，半導體封裝的製造方法，更包括：以所述導電連接件將基底附接至所述金屬化圖案。在一些實施例中，所述金屬化圖案的厚度為約6 μm至約10 μm。在一些實施例中，所述第一開口具有第一寬度，所述導電連接件具有第二寬度，並且所述第二寬度的對於所述第一寬度比值小於1.53。
以上概述了若干實施例的特徵，以便本領域技術人員可以更好地理解本公開的各方面。本領域技術人員應該理解，他們可以容易地使用本公開作為設計或修改其他製程和結構的基礎，以實現與本文介紹的實施例相同的目的及/或實現相同的優點。本領域技術人員還應該認識到，這樣的等同構造不脫離本公開的精神和範圍，並且可以在不脫離本公開的精神和範圍的情況下進行各種改變，替換和變更。
100‧‧‧承載基底
102‧‧‧離型層
104‧‧‧介電層
106‧‧‧金屬化圖案
108‧‧‧介電層
109‧‧‧開口
110‧‧‧背側重佈線結構
112‧‧‧穿孔
113‧‧‧晶種層
114‧‧‧積體電路晶粒
116‧‧‧黏著劑
118‧‧‧半導體基底
120‧‧‧內連線結構
122‧‧‧接墊
124‧‧‧保護膜
126‧‧‧晶粒連接件
128‧‧‧介電材料
130‧‧‧包封體
132‧‧‧前側重佈線結構
134‧‧‧介電層
136‧‧‧開口
138‧‧‧金屬化圖案
140‧‧‧介電層
142‧‧‧開口
144‧‧‧金屬化圖案
146‧‧‧介電層
148‧‧‧開口
150‧‧‧金屬化圖案
152‧‧‧介電層
154‧‧‧開口
156‧‧‧凸塊下金屬
158‧‧‧導電連接件
160‧‧‧膠帶
162‧‧‧開口
164‧‧‧金屬間化合物
200‧‧‧第一封裝
202‧‧‧基底
300‧‧‧第二封裝
302‧‧‧基底
303‧‧‧接合接墊
304‧‧‧接合接墊
305‧‧‧鎳表面處理
306‧‧‧穿孔
308‧‧‧堆疊晶粒
308A‧‧‧晶粒
308B‧‧‧晶粒
310‧‧‧打線
312‧‧‧模製材料
314‧‧‧導電連接件
400‧‧‧封裝基底
402‧‧‧可回流層
404‧‧‧回流連接件
500‧‧‧封裝結構
600‧‧‧第一封裝區域
602‧‧‧第二封裝區域
650‧‧‧區
T1‧‧‧厚度
T2‧‧‧厚度
T3‧‧‧厚度
W1‧‧‧寬度
W2‧‧‧寬度
W3‧‧‧寬度
結合附圖閱讀以下詳細說明，會最佳地理解本發明的各個態樣。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。 圖1至圖16示出了根據一些實施例的在用於形成元件封裝的製程期間的中間步驟的剖視圖。 圖17、圖18A至圖18C、圖19以及圖20示出了根據一些實施例的在用於形成封裝結構的製程期間的中間步驟的剖視圖。

Claims (20)

  1. 一種半導體封裝，包括： 背側重佈線結構，包括： 金屬化圖案，位於第一介電層上；以及 第二介電層，位於所述金屬化圖案上； 穿孔，延伸穿過所述第一介電層到接觸於所述金屬化圖案； 積體電路晶粒，相鄰於所述第一介電層上的所述穿孔； 模製化合物，位於所述第一介電層上，所述模製化合物包封所述穿孔和所述積體電路晶粒； 導電連接件，延伸穿過所述第二介電層至接觸於所述金屬化圖案，所述導電連接件電連接至所述穿孔；以及 金屬間化合物，位於所述導電連接件和所述金屬化圖案的界面，所述金屬間化合物僅部分延伸到所述金屬化圖案中。
  2. 如申請專利範圍第1項所述的半導體封裝，其中所述金屬化圖案的厚度為約6 μm至約10 μm。
  3. 如申請專利範圍第2項所述的半導體封裝，其中所述金屬間化合物延伸至所述金屬化圖案中的距離小於約6.5 μm。
  4. 如申請專利範圍第2項所述的半導體封裝，其中所述導電連接件與所述穿孔之間的所述金屬化圖案的部分的厚度大於約0.5 μm。
  5. 如申請專利範圍第2項所述的半導體封裝，其中延伸穿過所述第二介電層的所述導電連接件的第一部分具有第一寬度，所述第二介電層外的所述導電連接件的第二部分具有第二寬度，所述第二寬度對於所述第一寬度的比值小於1.53。
  6. 如申請專利範圍第1項所述的半導體封裝，其中延伸通過所述第二介電層的所述導電連接件的第一部分具有第一寬度，所述金屬間化合物具有第二寬度，並且所述第二寬度大於所述第一寬度。
  7. 如申請專利範圍第6項所述的半導體封裝，其中所述金屬化圖案具有第三寬度，且所述第二寬度小於所述第三寬度。
  8. 一種半導體封裝的製造方法，包括： 在第一介電層和第二介電層之間形成金屬化圖案； 圖案化所述第一介電層以形成穿過所述第一介電層的第一開口，所述第一開口暴露出所述金屬化圖案的第一側； 在所述第一開口中沉積晶種層； 圖案化所述第二介電層以形成穿過所述第二介電層的第二開口，所述第二開口暴露出所述金屬化圖案的第二側； 將導電連接件放置在所述金屬化圖案的所述第二側上的所述第二開口中；以及 回流所述導電連接件，藉以在所述導電連接件和所述金屬化圖案的所述界面形成金屬間化合物，所述金屬化圖案將所述金屬間化合物自所述晶種層分離。
  9. 如申請專利範圍第8項所述的半導體封裝的製造方法，更包括： 將積體電路晶粒附著於所述第一介電層。
  10. 如申請專利範圍第9項所述的半導體封裝的製造方法，更包括： 形成包封所述積體電路晶粒的模製化合物；以及 將導電材料鍍覆在所述晶種層上，所述導電材料延伸穿過所述模製化合物並至少部分地進入所述第一介電層。
  11. 如申請專利範圍第8項所述的半導體封裝的製造方法，其中所述回流所述導電連接件，以將第一基底接合至具有所述導電連接件的所述金屬化圖案的所述第二側。
  12. 如申請專利範圍第8項所述的半導體封裝的製造方法，其中在所述回流後，所述導電連接件包括焊料和銅。
  13. 如申請專利範圍第12項所述的半導體封裝的製造方法，其中所述導電連接件的銅具有梯度濃度，所述銅的所述梯度濃度沿著遠離所述金屬化圖案的方向遞減。
  14. 如申請專利範圍第12項所述的半導體封裝的製造方法，其中延伸穿過所述第二介電層的所述導電連接件的第一部分具有第一寬度，在所述第二介電層外的所述導電連接件的第二部分具有第二寬度，並且所述第二寬度對於所述第一寬度的比值小於1.53。
  15. 一種半導體封裝的製造方法，包括： 在第一介電層上形成金屬化圖案； 在所述金屬化圖案和所述第一介電層上沉積第二介電層； 形成延伸穿過所述第二介電層的穿孔以接觸所述金屬化圖案的第一側； 在所述第一介電層蝕刻出第一開口，暴露所述金屬化圖案的第二側； 在所述第一開口中印刷第一可回流材料；以及 在所述第一可回流材料上形成第二可回流材料，所述第一可回流材料和所述第二可回流材料包括不同濃度的導電材料；以及 回流所述第一可回流材料和所述第二可回流材料，以形成延伸穿過所述第一介電層的導電連接件，以及在所述金屬化圖案和所述導電連接件的所述界面的金屬間化合物。
  16. 如申請專利範圍第15項所述的半導體封裝的製造方法，其中形成所述穿孔包括： 在所述第二介電層中蝕刻出第二開口，暴露所述金屬化圖案的所述第一側； 在所述第二開口中沉積晶種層；以及 在所述晶種層上鍍覆導電材料，所述導電材料和所述晶種層形成所述穿孔。
  17. 如申請專利範圍第16項所述的半導體封裝的製造方法，更包括： 將積體電路晶粒附接到所述第二介電層，所述積體電路晶粒與所述穿孔相鄰；以及 以模製化合物包封所述穿孔和所述積體電路晶粒。
  18. 如申請專利範圍第15項所述的半導體封裝的製造方法，更包括： 以所述導電連接件將基底附接至所述金屬化圖案。
  19. 如申請專利範圍第15項所述的半導體封裝的製造方法，其中所述金屬化圖案的厚度為約6 μm至約10 μm。
  20. 如申請專利範圍第19項所述的半導體封裝的製造方法，其中所述第一開口具有第一寬度，所述導電連接件具有第二寬度，並且所述第二寬度的對於所述第一寬度比值小於1.53。
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