CN109786267A - 半导体封装件和方法 - Google Patents

半导体封装件和方法 Download PDF

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Publication number
CN109786267A
CN109786267A CN201810609924.XA CN201810609924A CN109786267A CN 109786267 A CN109786267 A CN 109786267A CN 201810609924 A CN201810609924 A CN 201810609924A CN 109786267 A CN109786267 A CN 109786267A
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China
Prior art keywords
dielectric layer
metallization pattern
layer
connecting part
conducting connecting
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CN201810609924.XA
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CN109786267B (zh
Inventor
黄子松
林修任
蔡豪益
曾明鸿
江宗宪
郭庭豪
林彦良
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

在实施例中，器件包括：背侧再分布结构，背侧再分布结构包括：金属化图案，位于第一介电层上；以及第二介电层，位于金属化图案上；通孔，穿过第一介电层延伸以接触金属化图案；集成电路管芯，邻近第一介电层上的通孔；模塑料，位于第一介电层上，模塑料密封通孔和集成电路管芯；导电连接件，穿过第二介电层延伸以接触金属化图案，导电连接件电连接至通孔；以及金属间化合物，位于导电连接件和金属化图案的界面处，金属间化合物仅部分地延伸至金属化图案内。本发明的实施例还涉及半导体封装件和方法。

Description

半导体封装件和方法
技术领域
本发明的实施例涉及半导体封装件和方法。
背景技术
由于各个电组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的持续改进，半导体工业已经经历了快速增长。对于大部分而言，集成密度的改进来自于最小部件尺寸的连续减小，这使得更多的组件集成到给定的区域。随着对缩小电子器件的需求的增长，对半导体管芯的更小且更具创造性的封装技术的需求也已经出现。这种封装系统的实例是叠层封装(PoP)技术。在PoP器件中，顶部半导体封装件堆叠在底部半导体封装件的顶部上以提供高集成度和组件密度。PoP技术通常能够在印刷电路板(PCB)上产生具有增强的功能和较小的覆盖区的半导体器件。
发明内容
本发明的实施例提供了一种半导体器件，包括：背侧再分布结构，包括：金属化图案，位于第一介电层上；和第二介电层，位于所述金属化图案上；通孔，穿过所述第一介电层延伸以接触所述金属化图案；集成电路管芯，邻近所述第一介电层上的通孔；模塑料，位于所述第一介电层上，所述模塑料密封所述通孔和所述集成电路管芯；导电连接件，穿过所述第二介电层延伸以接触所述金属化图案，所述导电连接件电连接至所述通孔；以及金属间化合物，位于所述导电连接件和所述金属化图案的界面处，所述金属间化合物仅部分地延伸至所述金属化图案内。
本发明的另一实施例提供了一种形成半导体封装件的方法，包括：在第一介电层和第二介电层之间形成金属化图案；图案化穿过所述第一介电层的第一开口，所述第一开口暴露所述金属化图案的第一侧；在所述第一开口中沉积晶种层；图案化穿过所述第二介电层的第二开口，所述第二开口暴露所述金属化图案的第二侧；将导电连接件放置在所述金属化图案的第二侧上的所述第二开口中；以及回流所述导电连接件，从而在所述导电连接件和所述金属化图案的界面处形成金属间化合物，所述金属化图案将所述金属间化合物与所述晶种层分隔开。
本发明的又一实施例提供了一种形成半导体封装件的方法，包括：在第一介电层上形成金属化图案；在所述金属化图案和所述第一介电层上沉积第二介电层；形成穿过所述第二介电层延伸的通孔以接触所述金属化图案的第一侧；在所述第一介电层中蚀刻第一开口，所述第一开口暴露所述金属化图案的第二侧；在所述第一开口中印刷第一可回流材料；以及在所述第一可回流材料上形成第二可回流材料，所述第一可回流材料和所述第二可回流材料包括不同浓度的导电材料；以及回流所述第一可回流材料和所述第二可回流材料以形成穿过所述第一介电层延伸的导电连接件，并且在所述金属化图案和所述导电连接件的界面处形成金属间化合物。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1、图2、图3、图4、图5、图6、图7、图8、图9、图10、图11、图12、图13、图14、图15和图16示出了根据一些实施例的在用于形成器件封装件的工艺期间的中间步骤的截面图。
图17、图18A、图18B、图18C、图19和图20示出了根据一些实施例的在用于形成封装结构的工艺期间的中间步骤的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
根据一些实施例，形成导电连接件以将器件封装件接合至再分布结构的金属化图案。形成暴露金属化图案的开口，并且在开口中形成导电连接件。之后，回流导电连接件以将金属化图案接合至器件封装件。通过控制开口和导电连接件的宽度，可以控制回流期间形成的IMC的厚度。具体地，IMC的厚度控制为小于金属化图案的厚度。因此，可以在随后的测试期间避免下面的晶种层的分层。
图1至图16示出了根据一些实施例的在用于形成第一封装件200的工艺期间的中间步骤的截面图。示出了第一封装区域600和第二封装区域602，并且在每个封装区域中均形成第一封装件200。第一封装件200也可以称为集成扇出(InFO)封装件。
在图1中，提供载体衬底100，并且在载体衬底100上形成释放层102。载体衬底100可以是玻璃载体衬底、陶瓷载体衬底等。载体衬底100可以是晶圆，从而使得可以同时在载体衬底100上形成多个封装件。释放层102可以由基于聚合物的材料形成，其可以与载体衬底100一起从在随后的步骤中形成的上面的结构去除。在一些实施例中，释放层102是诸如光热转换(LTHC)释放涂层的基于环氧树脂的热释放材料，该材料在加热时失去其粘合性。在其它实施例中，释放层102可以是紫外(UV)胶，当暴露于UV光时失去其粘合性。释放层102可以以液体形式分配并且被固化，可以是层压在载体衬底100上的层压膜，或可以是类似的。释放层102的顶面可以是齐平的并且可以具有高度的共面性。
在图2中，形成介电层104、金属化图案106(有时称为再分布层或再分布线)和介电层108。介电层104形成在释放层102上。介电层104的底面可以与释放层102的顶面接触。在一些实施例中，介电层104由诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的聚合物形成。在其它实施例中，介电层104由氮化物，诸如氮化硅；氧化物，诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)等；等形成。可以通过诸如旋涂、化学汽相沉积(CVD)、层压等或它们的组合的任何可接受的沉积工艺形成介电层104。
金属化图案106形成在介电层104上。作为形成金属化图案106的实例，在介电层104上方形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。之后，在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案106。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。之后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成金属化图案106。
介电层108形成在金属化图案106和介电层104上。在一些实施例中，介电层108由聚合物形成，聚合物可以是可以使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其它实施例中，介电层108由氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG；等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层108。之后，图案化介电层108以形成暴露金属化图案106的部分的开口。可以通过可接受的工艺图案化，诸如当介电层是光敏材料时通过将介电层108暴露于光或通过例如使用各向异性蚀刻的蚀刻。
介电层104和108以及金属化图案106可以称为背侧再分布结构110。在所示的实施例中，背侧再分布结构110包括两个介电层104和108以及一个金属化图案106。在其它实施例中，背侧再分布结构110可以包括任何数量的介电层、金属化图案和导电通孔。通过重复用于形成金属化图案106和介电层108的工艺，可以在背侧再分布结构110中形成一个或多个额外的金属化图案和介电层。可以在通过在下面的介电层的开口中形成金属化图案的晶种层和导电材料的金属化图案的形成期间形成导电通孔(未示出)。因此，导电通孔可以互连并且电连接各个金属化图案。
在图3中，形成通孔112。作为形成通孔112的实例，在背侧再分布结构110上方(例如，在介电层108和由开口109暴露的金属化图案106的部分上)形成晶种层113(在下面图18A至图18C中示出)。在一些实施例中，晶种层113是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层113包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层113。在晶种层113上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于通孔。图案化形成穿过光刻胶的开口以暴露晶种层113。在光刻胶的开口中和晶种层113的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。去除光刻胶和晶种层113的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层113的暴露部分。晶种层113的剩余部分和导电材料形成通孔112。
在图4中，通过粘合剂116将集成电路管芯114粘合至介电层108。集成电路管芯114可以是逻辑管芯(例如，中央处理单元、微控制器等)、存储器管芯(例如，动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯等)、电源管理管芯(例如，电源管理集成电路(PMIC)管芯)、射频(RF)管芯、传感器管芯、微电子机械系统(MEMS)管芯、信号处理管芯(例如，数字信号处理(DSP)管芯)、前端管芯(例如，模拟前端(AFE)管芯)等或它们的组合。而且，在一些实施例中，集成电路管芯114可以具有不同的尺寸(例如，不同的高度和/或表面积)，并且在其它实施例中，集成电路管芯114可以具有相同的尺寸(例如，相同的高度和/或表面积)。
在粘合至介电层108之前，可以根据可应用的制造工艺处理集成电路管芯114以在集成电路管芯114中形成集成电路。例如，集成电路管芯114每个均包括半导体衬底118，半导体衬底118诸如掺杂或未掺杂的硅或绝缘体上半导体(SOI)衬底的有源层。半导体衬底可以包括其它半导体材料，诸如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。也可以使用诸如多层衬底或梯度衬底的其它衬底。诸如晶体管、二极管、电容器、电阻器等的器件可以形成在半导体衬底118中和/或上，并且可以通过互连结构120互连以形成集成电路，互连结构120由例如半导体衬底118上的一个或多个介电层中的金属化图案形成。
集成电路管芯114还包括制成外部连接的焊盘122，诸如铝焊盘。焊盘122位于可以称为集成电路管芯114的相应的有源侧的位置上。钝化膜124位于集成电路管芯114上并且位于焊盘122的部分上。开口穿过钝化膜124至焊盘122。诸如导电柱(例如，包括诸如铜的金属)的管芯连接件126位于穿过钝化膜124的开口中并且机械地和电连接至相应的焊盘122。可以通过例如镀等形成管芯连接件126。管芯连接件126电连接集成电路管芯114的相应的集成电路。
介电材料128位于集成电路管芯114的有源侧上，诸如位于钝化膜124和管芯连接件126上。介电材料128横向密封管芯连接件126，并且介电材料128与相应的集成电路管芯114横向共末端。介电材料128可以是聚合物，诸如PBO、聚酰亚胺、BCB等；氮化物，诸如氮化硅等；氧化物，诸如氧化硅、PSG、BSG、BPSG等；等或它们的组合，并且可以例如通过旋涂、层压、CVD等形成。
粘合剂116位于集成电路管芯114的背侧上并且将集成电路管芯114粘合至背侧再分布结构110，诸如介电层108。粘合剂116可以是任何合适的粘合剂、环氧树脂、管芯附着膜(DAF)等。粘合剂116可以施加至集成电路管芯114的背侧(诸如相应的半导体晶圆的背侧)或可以施加在载体衬底100的表面上方。集成电路管芯114可以诸如通过锯切或切割被分割并且使用例如拾取和放置工具通过粘合剂116粘合至介电层108。
虽然在第一封装区域600和第二封装区域602的每个中示出为粘合两个集成电路管芯114，但是应该理解，可以在每个封装区域中粘合更多或更少的集成电路管芯114。例如，可以在每个区域中仅粘合一个集成电路管芯114。此外，集成电路管芯114的尺寸可以不同。在一些实施例中，集成电路管芯114可以是具有较大的覆盖区的管芯，诸如片上系统(SoC)器件。在集成电路管芯114具有较大的覆盖区的实施例中，可用于封装区域中的通孔112的空间可能受到限制。当封装区域具有可用于通孔112的有限空间时，使用背侧再分布结构110允许改进互连布置。
在图5中，在各种组件上形成密封剂130。密封剂130可以是模塑料、环氧树脂等，并且可以通过压缩模塑、转移模塑等施加。密封剂130可以形成在载体衬底100上方，从而掩埋或覆盖通孔112和/或集成电路管芯114的管芯连接件126。之后，固化密封剂130。
在图6中，对密封剂130实施平坦化工艺以暴露通孔112和管芯连接件126。平坦化工艺也可以研磨介电材料128。在平坦化工艺之后，通孔112、管芯连接件126、介电材料128和密封剂130的顶面共面。平坦化工艺可以是例如化学机械抛光(CMP)、研磨工艺等。在一些实施例中，例如，如果已经暴露通孔112和管芯连接件126，则可以省略平坦化。
在图7至图14中，形成前侧再分布结构132。如将示出的，前侧再分布结构132包括介电层134、140、146和152，并且也包括金属化图案138、144和150。金属化图案也可以称为再分布层或再分布线并且包括导电通孔和导线(未单独标记)。
在图7中，可以在密封剂130、通孔112和管芯连接件126上沉积介电层134。在一些实施例中，介电层134由聚合物形成，聚合物可以是可以使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其它实施例中，介电层134由氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG；等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层134。
之后，图案化介电层134。图案化形成暴露通孔112和管芯连接件126的部分的开口136。可以通过可接受的工艺图案化，诸如当介电层134是光敏材料时通过将介电层134暴露于光或通过例如使用各向异性蚀刻的蚀刻。如果介电层134是光敏材料，则可以在曝光之后显影介电层134。
在图8中，在介电层134上形成具有通孔的金属化图案138。作为形成金属化图案138的实例，在介电层134上方和穿过介电层134的开口136中形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。之后，在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案138。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。之后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成金属化图案138和通孔。在穿过介电层134至例如通孔112和/或管芯连接件126的开口136中形成通孔。
在图9中，在金属化图案138和介电层134上沉积介电层140。在一些实施例中，介电层140由聚合物形成，聚合物可以是可以使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其它实施例中，介电层140由氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG；等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层140。
之后，图案化介电层140。图案化形成暴露金属化图案138的部分的开口142。可以通过可接受的工艺图案化，诸如当介电层140是光敏材料时通过将介电层140暴露于光或通过例如使用各向异性蚀刻的蚀刻。如果介电层140是光敏材料，则可以在曝光之后显影介电层140。
在图10中，在介电层140上形成具有通孔的金属化图案144。作为形成金属化图案144的实例，在介电层140上方和穿过介电层140的开口142中形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。之后，在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案144。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。之后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成金属化图案144和通孔。在穿过介电层140至例如金属化图案138的部分的开口142中形成通孔。
在图11中，在金属化图案144和介电层140上沉积介电层146。在一些实施例中，介电层146由聚合物形成，聚合物可以是可以使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其它实施例中，介电层146由氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG；等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层146。
之后，图案化介电层146。图案化形成暴露金属化图案144的部分的开口148。可以通过可接受的工艺图案化，诸如当介电层146是光敏材料时通过将介电层146暴露于光或通过例如使用各向异性蚀刻的蚀刻。如果介电层146是光敏材料，则可以在曝光之后显影介电层146。
在图12中，在介电层146上形成具有通孔的金属化图案150。作为形成金属化图案150的实例，在介电层146上方和穿过介电层146的开口148中形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。之后，在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案150。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。之后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成金属化图案150和通孔。在穿过介电层146至例如金属化图案144的部分的开口中形成通孔。
在图13中，在金属化图案150和介电层146上沉积介电层152。在一些实施例中，介电层152由聚合物形成，聚合物可以是可以使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其它实施例中，介电层152由氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG；等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层152。
之后，图案化介电层152。图案化形成暴露金属化图案150的部分的开口154。可以通过可接受的工艺图案化，诸如当介电层152是光敏材料时通过将介电层152暴露于光或通过例如使用各向异性蚀刻的蚀刻。如果介电层152是光敏材料，则可以在曝光之后显影介电层152。开口154可以宽于开口136、142、148。
在图14中，在介电层152上形成凸块下金属(UBM)156。在示出的实施例中，UBM 156形成为穿过开口154，开口154穿过介电层152至金属化图案150。作为形成UBM 156的实例，在介电层152上方形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。之后，在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于UBM156。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。之后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成UBM 156。在不同地形成UBM 156的实施例中，可以利用更多的光刻胶和图案化步骤。
前侧再分布结构132示出为实例。可以在前侧再分布结构132中形成更多或更少的介电层和金属化图案。如果要形成更少的介电层和金属化图案，则可以省略以上讨论的步骤和工艺。如果要形成更多的介电层和金属化图案，则可以重复以上讨论的步骤和工艺。本领域普通技术人员将容易理解，可以省略或重复哪些步骤和工艺。
在图15中，在UBM 156上形成导电连接件158。导电连接件158可以是BGA连接件、焊球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯浸金技术(ENEPIG)形成的凸块等。导电连接件158可以包括诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合的导电材料。在一些实施例中，可以通过首先由诸如蒸发、电镀、印刷、焊料转移、球植等常用的方法形成焊料层来形成导电连接件158。一旦已经在结构上形成焊料层，则可以实施回流以将材料成形为期望的凸块形状。在另一实施例中，导电连接件158是通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如铜柱)。金属柱可以是无焊料的并且具有基本垂直的侧壁。在一些实施例中，在金属柱的顶部上形成金属覆盖层(未示出)。金属覆盖层可以包括镍、锡、锡铅、金、银、钯、铟、镍-钯-金、镍-金等或它们的组合，并且可以通过镀工艺形成。
在图16中，实施载体衬底脱粘以将载体衬底100从背侧再分布结构110(例如，介电层104)分离(脱粘)。从而在第一封装区域600和第二封装区域602的每个中形成第一封装件200。根据一些实施例，脱粘包括将诸如激光或UV光的光投射到释放层102上，使得释放层102在光的热量下分解，并且可以去除载体衬底100。之后，翻转该结构并且放置在带160上。此外，穿过介电层104形成暴露金属化图案106的部分的开口162。可以例如使用激光钻孔、蚀刻等形成开口162。
图17至图20示出了根据一些实施例的在用于形成封装结构500的工艺期间的中间步骤的截面图。封装结构500可以称为叠层封装(PoP)结构。
在图17中，将第二封装件300附接至第一封装件200。第二封装件300包括衬底302和连接至衬底302的一个或多个堆叠管芯308(308A和308B)。虽然示出了管芯308(308A和308B)的单个堆叠件，但是在其它实施例中，多个堆叠管芯308(每个均具有一个或多个堆叠管芯)可以并排设置为连接至衬底302的同一表面。衬底302可以由诸如硅、锗、金刚石等的半导体材料制成。在一些实施例中，也可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化镓铟、这些的组合等的化合物材料。此外，衬底302可以是绝缘体上硅(SOI)衬底。通常，SOI衬底包括诸如外延硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)或它们的组合的半导体材料层。在一个可选实施例中，衬底302是基于诸如玻璃纤维增强树脂芯的绝缘芯。芯材料的一个实例是诸如FR4的玻璃纤维树脂。芯材料的可选物质包括双马来酰亚胺-三嗪(BT)树脂或者其它印刷电路板(PCB)材料或薄膜。对于衬底302，可以使用诸如味之素积聚膜(ABF)或其它层压材料的积聚膜。
衬底302可以包括有源和无源器件(未示出)。如本领域普通技术人员将意识到，诸如晶体管、电容器、电阻器、这些的组合等的多种器件可以用于生成用于第二封装件300的设计的结构和功能需求。可以使用任何合适的方法形成该器件。
衬底302也可以包括金属化层(未示出)和通孔306。金属化层可以形成在有源和无源器件上方并且被设计为连接各个器件以形成功能电路。金属化层可以由电介质(例如，低k介电材料)和导电材料(例如，铜)(其具有互连导电材料层的通孔)的交替层形成，并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成。在一些实施例中，衬底302基本没有有源和无源器件。
衬底302可以具有位于衬底302的第一侧上以连接至堆叠管芯308的接合焊盘303，以及位于衬底302的第二侧上以连接至导电连接件314的接合焊盘304，第二侧与衬底302的第一侧相对。在一些实施例中，通过在衬底302的第一侧和第二侧上的介电层(未示出)中形成凹槽(未示出)来形成接合焊盘303和304。凹槽可以形成为允许接合焊盘303和304嵌入至介电层内。在其它实施例中，由于接合焊盘303和304可以形成在介电层上，因此省略凹槽。在一些实施例中，接合焊盘303和304包括由铜、钛、镍、金、钯等或它们的组合制成的薄晶种层(未示出)。可以在薄晶种层上方沉积接合焊盘303和304的导电材料。可以通过电化学镀工艺、化学镀工艺、CVD、ALD、PVD等或它们的组合来形成导电材料。在实施例中，接合焊盘303和304的导电材料是铜、钨、铝、银、金等或它们的组合。
在实施例中，接合焊盘303和304是UBM，其包括三个导电材料层，诸如钛层、铜层和镍层。例如，接合焊盘304可以由铜形成，可以形成在钛层(未示出)上，并且具有镍饰面层305。镍饰面层305可以改进器件封装件300的储存寿命，当器件封装件300是诸如DRAM模块的存储器器件时，这可能是特别有利的。然而，本领域普通技术人员将意识到，存在适合于形成接合焊盘303和304的许多合适的材料和层布置，诸如铬/铬-铜合金/铜/金的布置、钛/钛钨/铜的布置或铜/镍/金的布置。可以用于接合焊盘303和304的任何合适的材料或材料层均完全旨在包括在本申请的范围内。在一些实施例中，通孔306穿过衬底302延伸并且将至少一个接合焊盘303连接至至少一个接合焊盘304。
在示出的实施例中，通过引线接合310将堆叠管芯308连接至衬底302，但是也可以使用诸如导电凸块的其它连接。在实施例中，堆叠管芯308是堆叠的存储器管芯。例如，堆叠管芯308可以是诸如低功率(LP)双数据率(DDR)存储器模块(诸如LPDDR1、LPDDR2、LPDDR3、LPDDR4等存储器模块)的存储器管芯。如上所述，在这种实施例中，接合焊盘304可以具有镍饰面层305。
堆叠管芯308和引线接合310可以由模塑材料312密封。可以例如使用压缩模塑将模塑材料312模塑在堆叠管芯308和引线接合310上。在一些实施例中，模塑材料312是模塑料、聚合物、环氧树脂、氧化硅填充材料等或它们的组合。可以实施固化步骤以固化模塑材料312；固化工艺可以是热固化、UV固化等或它们的组合。
在一些实施例中，将堆叠管芯308和引线接合310埋在模塑材料312中，并且在模塑材料312的固化之后，实施诸如研磨的平坦化步骤以去除模塑材料312的过量部分并且为第二封装件300提供基本平坦的表面。
在形成第二封装件300之后，通过导电连接件314、接合焊盘304和金属化图案106将第二封装件300机械和电接合至第一封装件200。在一些实施例中，可以通过引线接合310、接合焊盘303和304、通孔306、导电连接件314和通孔112将堆叠管芯308连接至集成电路管芯114。图18A至图18C是示出在用导电连接件314接合第一封装件200和第二封装件300的工艺期间的区域650的更多细节的截面图。
在图18A中，在开口162中的每个暴露的金属化图案106上形成可回流层402。可回流层402可以是焊料层(有时称为预焊料层)、焊膏等。在实施例中，可回流层402是含Cu的预焊料材料，诸如SnCu、SnAgCu等或它们的组合，并且可以印刷至暴露的金属化图案106上，但是可以利用诸如电镀或化学镀的其它工艺。可回流层402的Cu浓度可以在从约5％至约10％。在一些实施例中，可回流层402完全填充或过填充开口162，并且在其它实施例中，可回流层402仅部分地填充开口162。开口162形成为宽度W1在从约230μm至约260μm，诸如约250μm。因此，每个开口162中的可回流层402的部分也具有宽度W1。
在图18B中，在背侧再分布结构110的背侧上方、可回流层402上形成可回流连接件404。可回流连接件404可以与导电连接件158类似。例如，可以通过首先由诸如蒸发、电镀、印刷、焊料转移、球植等常用的方法形成焊料层来形成可回流连接件404。一旦已经在结构上形成焊料层，则可以实施回流以将材料成形为期望的凸块形状。可回流连接件404基本不含Cu或非常少的Cu。具体地，可回流层402的Cu浓度大于可流动连接件404的Cu浓度。在形成之后，可回流连接件404具有在从约250μm至约320μm(诸如约300μm)的宽度W2。
在一些实施例中，在形成之后，可回流连接件404涂覆有焊剂(未示出)，诸如免洗焊剂。可以将可回流连接件404浸入焊剂中，或可以将焊剂喷射至可回流焊连接件404上。在另一实施例中，可以将焊剂施加至金属化图案106的表面。
在图18C中，实施回流工艺以通过例如焊料接合将第二封装件300接合至第一封装件200。在该回流工艺期间，回流可回流层402和可回流连接件404以形成导电连接件314。在回流工艺之后，可回流层402和可回流连接件404可以混合并且不能作为单独的结构明显可见。在该回流工艺期间，导电连接件314与接合焊盘304和金属化图案106接触以将第二封装件300物理和电连接至第一封装件200。导电连接件314可以设置在衬底302的与堆叠管芯308相对的一侧上、开口162中。在接合工艺之后，可以在导电连接件314和接合焊盘304之间的界面处形成金属间化合物(IMC)(未示出)。也在金属化图案106和导电连接件314的界面处形成IMC 164。在形成之后，每个IMC 164均具有在从约245μm至约275μm(诸如约255μm)的宽度W3。IMC 164的宽度W3小于导电连接件314的宽度W2，并且可以大于开口162的宽度W1。
在接合焊盘304上形成镍饰面层305的实施例中，回流工艺导致在IMC164的形成期间从金属化图案106消耗更多的Cu。此外，由于镍饰面层305用作阻挡层，因此，基本不从接合焊盘304消耗Cu。因此，根据菲克定律，在形成镍饰面层305的实施例中，导电连接件314具有渐变的Cu浓度。具体地，Cu的浓度可以在从金属化图案106延伸至镍饰面层305的方向上穿过导电连接件314减小。
IMC 164形成为厚度T1，并且背侧再分部结构110的金属化图案106形成为厚度T2。如上所述，开口162形成为宽度W1，并且可回流连接件404形成为宽度W2。形成开口162和可回流连接件404的工艺条件控制为使得宽度W2与宽度W1的比率在特定范围内。控制宽度W2与宽度W1的比率允许控制IMC 164的厚度T1。值得注意的是，宽度W2与宽度W1的比率控制为使得厚度T1小于厚度T2，厚度差为T3。在实施例中，金属化图案106的厚度T2可以在从约6μm至约10μm，诸如约7μm。在这种实施例中，将宽度W2与宽度W1的比率限制为小于约1.53允许IMC164的厚度T1小于金属化图案106的厚度T2。例如，IMC 164的厚度T1可以小于约6.5μm，诸如在从约3μm至约6μm，并且厚度差T3可以大于约0.5μm，诸如在从约1μm至约2.5μm。
在形成导电连接件314之后，可以测试第一封装件200和第二封装件300以确定封装件的可靠性。测试工艺可以使封装件经受高热量。如果IMC164形成为完全穿过金属化图案106，则在高温测试期间可能发生晶种层113的分层。因此，虽然在回流期间可能形成可靠的连接，但是该连接可能在随后的测试期间故障。
因为可回流层402的Cu浓度大于可回流连接件404的Cu浓度，并且因为可回流层402形成有在从约5％至约10％的Cu浓度，所以产生的导电连接件314可以具有在从约0.55％至0.7％的Cu重量浓度，诸如大于约0.5％的重量浓度。这种浓度允许形成IMC 164，但是减少了回流期间从金属化图案106消耗的Cu的量。减少从金属化图案106消耗的Cu的量可以允许一些纯Cu保留在金属化图案106的部分中，避免测试期间晶种层113的分层。
通过使IMC 164的厚度T1形成为小于金属化图案106的厚度T2，在回流工艺之后，一些铜保留设置在IMC 164和晶种层113之间。晶种层113和金属化图案106之间的粘合可以比晶种层113和IMC 164之间的粘合更强。因此，通过形成IMC 164，使得IMC 164不一直延伸至晶种层113，可以在测试期间避免或减少晶种层113的分层。
在一些实施例中，在衬底302的与堆叠管芯308相对的一侧上形成阻焊剂(未示出)。导电连接件314可以设置在阻焊剂中的开口中，以电和机械连接至衬底302中的导电部件(例如，接合焊盘304)。阻焊剂可以用于保护衬底302的区免受外部损坏。
在一些实施例中，导电连接件314可以具有在其上形成的环氧树脂焊剂(未示出)，然后回流在将第二封装件300附接至第一封装件200之后剩余的环氧树脂焊剂的至少一些环氧树脂部分。
在一些实施例中，在第一封装件200和第二封装件300之间以及围绕导电连接件314形成底部填充物(未示出)。底部填充物可以减小应力并且保护由导电连接件314的回流产生的接头。底部填充物可以在附接第一封装件200之后通过毛细管流动工艺形成，或可以在附接第一封装件200之前通过合适的沉积方法形成。在形成环氧树脂焊剂的实施例中，环氧树脂焊剂可以用作底部填充物。
在图19中，通过沿着划线区域(例如，在第一封装区域600和第二封装区域602之间)锯切来实施分割工艺316。锯切分割第一封装区域600与第二封装区域602。产生来自第一封装区域600或第二封装区域602的一个的分割的第一封装件200和第二封装件300。在一些实施例中，在第二封装件300附接至第一封装件200之后实施分割工艺316。在其它实施例(未示出)中，在将第二封装件300附接至第一封装件200之前，诸如在将载体衬底100脱粘并且形成开口162之后，实施分割工艺316。
在图20中，使用导电连接件158将第一封装件200安装至封装衬底400。封装衬底400可以由诸如硅、锗、金刚石等的半导体材料制成。可选地，也可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化镓铟、这些的组合等的化合物材料。此外，封装衬底400可以是SOI衬底。通常，SOI衬底包括诸如外延硅、锗、硅锗、SOI、SGOI或它们的组合的半导体材料层。在一个可选实施例中，封装衬底400是基于诸如玻璃纤维增强树脂芯的绝缘芯。芯材料的一个实例是诸如FR4的玻璃纤维树脂。芯材料的可选物质包括双马来酰亚胺-三嗪(BT)树脂或者其PCB材料或薄膜。对于封装衬底400可以使用诸如ABF或其它层压材料的积聚膜。
封装衬底400可以包括有源和无源器件(未示出)。如本领域普通技术人员将意识到，诸如晶体管、电容器、电阻器、这些的组合等的多种器件可以用于生成用于封装结构500的设计的结构和功能需求。可以使用任何合适的方法形成该器件。
封装衬底400也可以包括金属化层和通孔(未示出)以及位于金属化层和通孔上方的接合焊盘402。金属化层可以形成在有源和无源器件上方并且被设计为连接各个器件以形成功能电路。金属化层可以由电介质(例如，低k介电材料)和导电材料(例如，铜)(其具有互连导电材料层的通孔)的交替层形成，并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成。在一些实施例中，封装衬底400基本没有有源和无源器件。
在一些实施例中，回流导电连接件158以将第一封装件200附接至接合焊盘402。导电连接件158将包括封装衬底400中的金属化层的封装衬底400电和/或物理连接至第一封装件200。在一些实施例中，在安装在封装衬底400上之前，可以将无源器件(例如，未示出的表面安装器件(SMD))附接至第一封装件200(例如，接合至接合焊盘402)。在这种实施例中，无源器件可以与导电连接件158接合至第一封装件200的同一表面。
导电连接件158可以具有在其上形成的环氧树脂焊剂(未示出)，然后回流在将第一封装件200附接至封装衬底400之后剩余的环氧树脂焊剂的至少一些环氧树脂部分。该剩余的环氧树脂部分可以用作底部填充物以减小应力并且保护由导电连接件158的回流产生的接头。在一些实施例中，可以在第一封装件200和封装衬底400之间以及围绕导电连接件158形成底部填充物(未示出)。底部填充物可以在附接第一封装件200之后通过毛细管流动工艺形成，或可以在附接第一封装件200之前通过合适的沉积方法形成。
实施例可以实现许多优势。控制宽度W2与宽度W1的比率小于1.53可以允许控制IMC164的厚度。值得注意的是，通过使IMC 164的厚度形成为小于金属化图案106的厚度，一些Cu可以保留在导电连接件314和晶种层113之间的金属化图案106中。因此，可以在测试期间减少或避免晶种层113的分层。
在实施例中，器件包括：背侧再分布结构，背侧再分布结构包括：金属化图案，位于第一介电层上；以及第二介电层，位于金属化图案上；通孔，穿过第一介电层延伸以接触金属化图案；集成电路管芯，邻近第一介电层上的通孔；模塑料，位于第一介电层上，模塑料密封通孔和集成电路管芯；导电连接件，穿过第二介电层延伸以接触金属化图案，导电连接件电连接至通孔；以及金属间化合物，位于导电连接件和金属化图案的界面处，金属间化合物仅部分地延伸至金属化图案内。
在一些实施例中，金属化图案具有在从约6μm至约10μm的厚度。在一些实施例中，金属间化合物延伸至金属化图案内的距离小于约6.5m。在一些实施例中，导电连接件和通孔之间的金属化图案的部分具有大于约0.5μm的厚度。在一些实施例中，导电连接件的穿过第二介电层延伸的第一部分具有第一宽度，导电连接件的位于第二介电层外部的第二部分具有第二宽度，并且第二宽度与第一宽度的比率小于1.53。在一些实施例中，导电连接件的穿过第二介电层延伸的第一部分具有第一宽度，金属间化合物具有第二宽度，并且第二宽度大于第一宽度。在一些实施例中，金属化图案具有第三宽度，并且第二宽度小于第三宽度。
在实施例中，方法包括：在第一介电层和第二介电层之间形成金属化图案；图案化穿过第一介电层的第一开口，第一开口暴露金属化图案的第一侧；在第一开口中沉积晶种层；图案化穿过第二介电层的第二开口，第二开口暴露金属化图案的第二侧；将导电连接件放置在金属化图案的第二侧上的第二开口中；以及回流导电连接件，从而在导电连接件和金属化图案的界面处形成金属间化合物，金属化图案将金属间化合物与晶种层分隔开。
在一些实施例中，该方法还包括：将集成电路管芯附接至第一介电层。在一些实施例中，该方法还包括：形成密封集成电路管芯的模塑料；以及在晶种层上镀导电材料，导电材料穿过模塑料延伸并且至少部分地延伸至第一介电层内。在一些实施例中，回流导电连接件用导电连接件将第一衬底接合至金属化图案的第二侧。在一些实施例中，在回流之后，导电连接件包括焊料和铜。在一些实施例中，导电连接件具有渐变的铜浓度，渐变的铜浓度在远离金属化图案延伸的方向上减小。在一些实施例中，导电连接件的穿过第二介电层延伸的第一部分具有第一宽度，导电连接件的位于第二介电层外部的第二部分具有第二宽度，并且第二宽度与第一宽度的比率小于1.53。
在实施例中，方法包括：在第一介电层上形成金属化图案；在金属化图案和第一介电层上沉积第二介电层；形成穿过第二介电层延伸的通孔以接触金属化图案的第一侧；在第一介电层中蚀刻第一开口，第一开口暴露金属化图案的第二侧；在第一开口中印刷第一可回流材料；以及在第一可回流材料上形成第二可回流材料，第一可回流材料和第二可回流材料包括不同浓度的导电材料；以及回流第一可回流材料和第二可回流材料以形成穿过第一介电层延伸的导电连接件以及在金属化图案和导电连接件的界面处形成金属间化合物。
在一些实施例中，形成通孔包括：在第二介电层中蚀刻第二开口，第二开口暴露金属化图案的第一侧；在第二开口中沉积晶种层；以及在晶种层上镀导电材料，导电材料和晶种层形成通孔。在一些实施例中，该方法还包括：将集成电路管芯附接至第二介电层，集成电路管芯邻近通孔；以及用模塑料密封通孔和集成电路管芯。在一些实施例中，该方法还包括：利用导电连接件将衬底附接至金属化图案。在一些实施例中，金属化图案具有在从约6μm至约10μm的厚度。在一些实施例中，第一开口具有第一宽度，导电连接件具有第二宽度，并且第二宽度与第一宽度的比率小于1.53。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种半导体器件，包括：
背侧再分布结构，包括：
金属化图案，位于第一介电层上；和
第二介电层，位于所述金属化图案上；
通孔，穿过所述第一介电层延伸以接触所述金属化图案；
集成电路管芯，邻近所述第一介电层上的通孔；
模塑料，位于所述第一介电层上，所述模塑料密封所述通孔和所述集成电路管芯；
导电连接件，穿过所述第二介电层延伸以接触所述金属化图案，所述导电连接件电连接至所述通孔；以及
金属间化合物，位于所述导电连接件和所述金属化图案的界面处，所述金属间化合物仅部分地延伸至所述金属化图案内。
2.根据权利要求1所述的半导体器件，其中，所述金属化图案具有在从6μm至10μm的厚度。
3.根据权利要求2所述的半导体器件，其中，所述金属间化合物延伸至所述金属化图案内的距离小于6.5m。
4.根据权利要求1所述的半导体器件，其中，所述导电连接件和所述通孔之间的所述金属化图案的部分具有大于0.5μm的厚度。
5.根据权利要求1所述的半导体器件，其中，所述导电连接件的穿过所述第二介电层延伸的第一部分具有第一宽度，所述导电连接件的位于所述第二介电层外部的第二部分具有第二宽度，并且所述第二宽度与所述第一宽度的比率小于1.53。
6.根据权利要求1所述的半导体器件，其中，所述导电连接件的穿过所述第二介电层延伸的第一部分具有第一宽度，所述金属间化合物具有第二宽度，并且所述第二宽度大于所述第一宽度。
7.根据权利要求6所述的半导体器件，其中，所述金属化图案具有第三宽度，并且所述第二宽度小于所述第三宽度。
8.一种形成半导体封装件的方法，包括：
在第一介电层和第二介电层之间形成金属化图案；
图案化穿过所述第一介电层的第一开口，所述第一开口暴露所述金属化图案的第一侧；
在所述第一开口中沉积晶种层；
图案化穿过所述第二介电层的第二开口，所述第二开口暴露所述金属化图案的第二侧；
将导电连接件放置在所述金属化图案的第二侧上的所述第二开口中；以及
回流所述导电连接件，从而在所述导电连接件和所述金属化图案的界面处形成金属间化合物，所述金属化图案将所述金属间化合物与所述晶种层分隔开。
9.根据权利要求8所述的方法，还包括：
将集成电路管芯附接至所述第一介电层。
10.一种形成半导体封装件的方法，包括：
在第一介电层上形成金属化图案；
在所述金属化图案和所述第一介电层上沉积第二介电层；
形成穿过所述第二介电层延伸的通孔以接触所述金属化图案的第一侧；
在所述第一介电层中蚀刻第一开口，所述第一开口暴露所述金属化图案的第二侧；
在所述第一开口中印刷第一可回流材料；以及
在所述第一可回流材料上形成第二可回流材料，所述第一可回流材料和所述第二可回流材料包括不同浓度的导电材料；以及
回流所述第一可回流材料和所述第二可回流材料以形成穿过所述第一介电层延伸的导电连接件，并且在所述金属化图案和所述导电连接件的界面处形成金属间化合物。
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