CN112018065A - 集成电路器件及其形成方法 - Google Patents

集成电路器件及其形成方法 Download PDF

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Publication number
CN112018065A
CN112018065A CN202010485845.XA CN202010485845A CN112018065A CN 112018065 A CN112018065 A CN 112018065A CN 202010485845 A CN202010485845 A CN 202010485845A CN 112018065 A CN112018065 A CN 112018065A
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interposer
encapsulant
package
semiconductor substrate
forming
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CN112018065B (zh
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余振华
卢思维
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

形成集成电路器件的方法包括将器件管芯接合至中介层。中介层包括从中介层的半导体衬底的顶面延伸至半导体衬底的顶面和底面之间的中间层级的通孔。实施分割工艺以将中介层和器件管芯锯切成封装件。该方法还包括将封装件放置在载体上方，将封装件密封在密封剂中，减薄中介层的密封剂和半导体衬底，直至露出通孔，并且形成再分布线，其中，再分布线中的再分布线与通孔接触。本发明的实施例还涉及集成电路器件。

Description

集成电路器件及其形成方法
技术领域
本发明的实施例涉及集成电路器件及其形成方法。
背景技术
在集成电路的封装中，可以将多个管芯接合在中介层晶圆上，该中介层晶圆中包括多个中介层。在管芯的接合之后，可将底部填充物分配至管芯和中介层晶圆之间的间隙中。然后可以实施固化工艺以固化底部填充物。
底部填充物在固化后可能会收缩。因此，固化的底部填充物在管芯和中介层晶圆上施加应力，并且可能导致中介层晶圆具有翘曲。中介层晶圆的翘曲进一步使得后续工艺中的工艺困难。例如，在随后的工艺中(例如，模制、研磨、减薄等)，中介层晶圆需要通过真空固定在卡盘台上，以在其上形成金属线和焊料区域。然而，在中介层晶圆具有翘曲的情况下，可能无法将中介层晶圆固定在卡盘台上。
发明内容
本发明的实施例提供了一种形成集成电路器件的方法，包括：将器件管芯接合至中介层，其中，所述中介层包括从所述中介层的半导体衬底的顶面延伸至所述半导体衬底的所述顶面和底面之间的中间层级的通孔；实施第一分割工艺以将所述中介层和所述器件管芯锯切成第一封装件；将所述第一封装件放置在载体上方；将所述第一封装件密封在第一密封剂中；减薄所述中介层的所述第一密封剂和所述半导体衬底，直至露出所述通孔；以及形成再分布线，其中，所述再分布线中的再分布线与所述通孔接触。
本发明的另一实施例提供了一种形成集成电路器件的方法，包括：将多个中介层密封在密封剂中，其中，所述多个中介层通过所述密封剂彼此分隔开，其中，所述多个中介层包括延伸至所述多个中介层中的半导体衬底中的通孔；抛光所述中介层以去除所述半导体衬底的部分，其中，所述通孔的表面露出；在所述半导体衬底和所述多个中介层的所述通孔上方形成与所述半导体衬底和所述多个中介层的所述通孔接触的第一介电层；形成延伸至所述第一介电层中以接触所述多个中介层的所述通孔的再分布线；以及切穿所述密封剂以将所述多个中介层分成多个封装件。
本发明的又一实施例提供了一种集成电路器件，包括：封装件，包括：器件管芯；中介层，与所述器件管芯接合，其中，所述中介层包括：半导体衬底；以及通孔，穿透所述半导体衬底；第一密封剂，将所述封装件密封在所述第一密封剂中；介电层，与所述半导体衬底和所述第一密封剂接触；以及再分布线，延伸至所述介电层中，其中，所述再分布线中的再分布线与所述通孔接触。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图18是根据一些实施例的形成封装件的中间阶段的截面图。
图19至图24是根据一些实施例的形成封装件的中间阶段的截面图。
图25示出了根据一些实施例的封装件的一部分的放大图。
图26示出了根据一些实施例的用于形成封装件的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等间隔相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，间隔相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的间隔相对描述符可以同样地作出相应的解释。
根据各个实施例，提供了封装件及其形成方法。根据一些实施例示出了封装件的形成中的中间阶段。讨论了一些实施例的一些变型。贯穿各个视图和示例性实施例，相同的参考标号用于指示相同的元件。根据本发明的一些实施例，用于形成衬底上晶圆上芯片(CoWoS)封装件的工艺包括在中介层晶圆上接合器件管芯，密封器件管芯，并且然后将得到的重构晶圆锯切成离散的晶圆上芯片(CoW)封装件。然后将离散的CoW封装件放置在载体上方，并且然后密封。实施减薄/平坦化工艺以露出中介层中的通孔。使用扇出工艺形成再分布线(RDL)，其中，RDL和相应的介电层的组合用作衬底。因此，本发明的衬底从中介层开始形成，而不是预成型并且接合至CoW封装件。
将参照特定上下文(即CoWoS封装件)来描述实施例。然而，其它实施例也可以应用于其它封装件，诸如将器件管芯接合至包括有源器件(诸如晶体管)的器件晶圆(而不是中介层晶圆)，以及其它工艺。本文讨论的实施例将提供为实例以使得能够制造或使用本发明的主题，并且本领域普通技术人员将容易理解，可以进行修改同时仍在不同实施例的预期范围内。下图中相似的参考数字和字符是指相似的组件。尽管方法实施例可以讨论为以特定顺序实施，但是其它方法实施例可以以任何逻辑顺序实施。
图1至图18示出了根据本发明的一些实施例的形成封装件的中间阶段的截面图。相应的工艺也示意性地反映在图26所示的工艺流程200中。
图1示出了中介层晶圆20的截面图。中介层晶圆20可以包括衬底22。根据一些实施例，衬底22是半导体衬底，其还可以是晶体硅衬底，但是它可以包括其它半导体材料，诸如硅锗、硅碳等。根据可选实施例，衬底22是介电衬底。根据一些实施例，中介层晶圆20中不具有有源器件，诸如晶体管和二极管。在这些实施例中，中介层晶圆20可以包括或可以不包括形成在其中的无源器件，诸如电容器、电感器和电阻器。根据可选实施例，晶圆20是器件晶圆，其包括形成在半导体衬底22的顶面处的有源器件，诸如晶体管(未示出)。可以形成通孔(有时称为衬底通孔(TSV))24，以从衬底22的顶面延伸至衬底22中。当形成在硅衬底中时，TV 24有时也称为硅通孔。尽管未在图1中示出，但是每个TV 24可以由隔离衬垫26(图25)环绕，该隔离衬垫26由诸如氧化硅、氮化硅等的介电材料形成。隔离衬垫26将相应TV 24与半导体衬底22隔离。
在晶圆20是中介层晶圆的实施例中，中介层晶圆20包括可以彼此相同的多个中介层40。中介层晶圆20中的衬底22可以连续地延伸贯穿整个中介层晶圆20，并且多个中介层40中的衬底22彼此互连，而没有通过介电区域彼此分隔开。根据可选实施例，晶圆20可以包括器件管芯40(也称为芯片)，其可以是逻辑/核心管芯、存储器管芯、模拟管芯等。
互连结构28形成在半导体衬底22上方，并且用于电连接至TV 24。互连结构28可以包括多个介电层30。金属线32形成在介电层30中。在上金属线32和下金属线32之间形成互连上金属线32和下金属线32的通孔34。金属线32和通孔34有时称为再分布层(RDL)32/34。根据一些实施例，介电层30由氧化硅、氮化硅、碳化硅、氮氧化硅、它们的组合和/或它们的多层形成。可选地，介电层30可包括具有低k值的一个或多个低k介电层。例如，介电层30中的低k介电材料的k值可以小于约3.0，或者小于约2.5。
电连接件36形成在中介层晶圆20的顶面处。根据一些实施例，电连接件36包括金属柱，其中，在金属柱的顶面上可以形成或可以不形成焊料盖。根据可选实施例，电连接件36包括焊料区域。在又其它实施例中，电连接件36可以是包括铜杆、镍层、焊料盖、化学镀镍浸金(ENIG)、化学镀镍化学镀钯浸金(ENEPIG)等的复合凸块。
进一步参考图1，例如通过倒装芯片接合将封装组件42接合至中介层40。相应的工艺示出为图26所示的工艺流程200中的工艺202。电连接件38通过电连接件36将封装组件42中的电路电耦接至中介层晶圆20中的RDL 32/34和TV 24。封装组件42可以是包括逻辑电路、存储器电路等的器件管芯。因此，封装组件42在下文中可替代地称为管芯42。根据本发明的其它实施例，封装组件42包括封装件，该封装件包括接合至相应中介层、封装衬底等的管芯。在每个中介层40上，可以在其上接合一个、两个或更多的管芯42。
下一步，如图2所示，将底部填充物44分配至在管芯42和中介层晶圆20之间的间隔(间隙)中。底部填充物44可以包括作为基底材料的聚合物、树脂、环氧树脂等，并且可以在其中包括填料颗粒。填料颗粒可以由二氧化硅、氧化铝等形成，并且可以具有球形形状。然后在固化工艺中固化底部填充物44。取决于底部填充物44的类型，固化工艺可以包括热固化工艺或紫外线(UV)固化工艺。
在施加底部填充物44之后，将器件管芯42密封在密封剂46中。相应的工艺示出为图26所示的工艺流程200中的工艺204。密封剂46可以是模塑料、模制底部填充物等。密封剂46的顶面高于器件管芯42的顶面。根据可选实施例，底部填充物44和密封剂46以相同的工艺施加，例如，使用模制底部填充物。
图3示意性地示出了密封剂46的一些细节。密封剂46可以包括基底材料46A，其可以是聚合物、树脂、环氧树脂等，以及位于基底材料46A中的填料颗粒46B。填料颗粒46B可以是诸如SiO2、Al2O3、二氧化硅、铁(Fe)的介电化合物、钠(Na)的介电化合物等介电材料的颗粒，并且可以具有球形形状。而且，根据一些实例，如图3所示，球形填料颗粒46B可以具有相同或不同的直径。
再次参考图2，固化密封剂46，然后进行平坦化工艺，该平坦化工艺可以是化学机械抛光(CMP)工艺或机械抛光工艺。根据本发明的一些实施例，在平坦化工艺之后，露出一些或全部器件管芯42的顶面(其可以是半导体衬底的顶面)。根据本发明的一些实施例，在平坦化工艺之后，器件管芯42由剩余的密封剂46的层覆盖。
在整个说明书中，包括中介层晶圆20、管芯42、底部填充物44和密封剂46的结构统称为重构晶圆48。重构晶圆48也称为CoW晶圆。根据一些实施例，可以在分割工艺之前将作为粘合膜的管芯附接膜(DAF)52粘附至重构晶圆片48的顶面，并且将DAF与重构晶圆48一起锯切。
在平坦化工艺之后，实施分割工艺以将重构晶圆48分成单独的封装件54。相应的工艺示出为图26所示的工艺流程200中的工艺206。可以沿着中介层晶圆20的划线50实施分割工艺。在图3中示出了所得到的封装件54(有时称为CoW管芯或CoW封装件)中的一个。锯切的DAF 52附接至封装件54，并且可以与密封剂46和管芯42的半导体衬底(未单独示出)接触。
图3示出了封装件54的实例。由于平坦化工艺，一些填料颗粒46B被部分地抛光，从而使得一些填料颗粒46B的一些部分被去除(图3中的底部)，并且顶部保留。因此，所得的部分填料颗粒46B将具有平坦的底面，该平坦的底面与基底材料46A的底面和器件管芯42的半导体衬底共面。此外，由于分割工艺，锯切了一些填料颗粒46B，使得一些填料颗粒46B的一些部分(诸如图3所示的最左侧的填料颗粒46B的左侧部分)被去除。因此，所得的部分填料颗粒46B将具有平坦的左侧或右侧表面(侧壁)，该平坦的表面与基底材料46A的侧壁共面(齐平)。
图4至图20示出了扇出封装件的形成，其中，封装件54封装在其中。参考图4，提供了载体60，并且释放膜62涂覆在载体60上。载体60由透明材料形成，并且可以是玻璃载体、陶瓷载体等。载体60可以具有圆形的俯视形状，并且可以具有硅晶圆的尺寸。释放膜62可以由光热转换(LTHC)涂层材料形成。可以通过涂覆将释放膜62施加到载体60上。根据本发明的一些实施例，LTHC涂层材料能够在光/辐射(诸如激光)的热量下分解，并且因此可以从形成在其上的结构释放载体60。
根据一些实施例，如图4所示，缓冲层64形成在释放膜62上。聚合物缓冲层64可以由介电材料形成，该介电材料可以是诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的聚合物。在缓冲层64上方形成再分布线(RDL)66。相应的工艺示出为图26所示的工艺流程200中的工艺208。RDL 66的形成可以包括在缓冲层64上方形成晶种层(未示出)，形成图案化的掩模(未示出)，诸如在晶种层上方形成图案化的光刻胶，以及然后实施金属镀工艺以形成RDL 66。然后去除图案化的掩模和晶种层的由图案化的掩模覆盖的部分，留下如图4所示的RDL 66。根据本发明的一些实施例，晶种层包括钛层和位于钛层上方的铜层。可以使用例如物理汽相沉积(PVD)形成晶种层。可以使用例如电化学镀或化学镀来实施镀。
进一步参考图4，在RDL 66上形成介电层68。相应的工艺示出为图26所示的工艺流程200中的工艺210。介电层68的底面可以与RDL 66和缓冲层64的顶面接触。根据本发明的一些实施例，介电层68由聚合物形成，该聚合物可以是诸如PBO、聚酰亚胺等的光敏材料。根据可选实施例，介电层68由诸如氮化硅的氮化物、诸如氧化硅的氧化物等形成。然后图案化介电层68以在其中形成开口70。因此，RDL 66的一些焊盘部分通过介电层68中的开口70暴露。
参考图5，例如通过PVD形成金属晶种层72。相应的工艺示出为图26所示的工艺流程200中的工艺212。根据本发明的一些实施例，金属晶种层72包括钛层和位于钛层上方的铜层。根据本发明的可选实施例，金属晶种层72包括与缓冲层64接触的铜层。
还如图5所示，在金属晶种层72上方形成诸如光刻胶74的镀掩模。相应的工艺示出为图26所示的工艺流程200中的工艺214。然后，使用光刻掩模(未示出)对光刻胶74实施曝光工艺。在光刻胶74的后续显影工艺之后，在光刻胶74中形成开口76。金属晶种层72的一些部分通过开口76暴露。
下一步，如图6所示，通过在开口76中镀金属材料来形成金属杆78。相应的工艺示出为图26所示的工艺流程200中的工艺216。金属杆78可选地称为通孔或模制通孔，因为它们将穿透最终封装件中的随后形成的密封材料(其可以是模塑料)。镀的金属材料可以是铜或铜合金。金属杆78的顶面低于光刻胶74的顶面，使得金属杆78的形状由开口76限制。金属杆78可具有基本垂直和直的边缘。可选地，金属杆78在截面图中可以具有沙漏计时器形状，其中，金属杆78的中间部分比相应的顶部部分和底部部分窄。
在随后的步骤中，去除光刻胶74，并且暴露下面的金属晶种层72的部分。然后，在例如各向异性蚀刻步骤或各向同性蚀刻步骤的蚀刻工艺中去除金属晶种层72的暴露部分。剩余的晶种层72的边缘因此可以与相应金属杆78的上面部分共末端或基本上共末端。所得的金属杆78在图7中示出。在整个说明书中，金属晶种层72的位于镀金属杆78正下方的剩余部分被视为金属杆78的一部分。金属杆78的俯视形状包括但不限于圆形、矩形、六边形、八边形等。在形成金属杆78之后，暴露介电层68。
图8示出了CoW封装件54的放置/附接，其中，DAF 52将相应封装件54粘附至介电层68。相应的工艺示出为图26所示的工艺流程200中的工艺218。下一步，将封装件54和金属杆78密封在密封剂80中，如图9所示。相应的工艺示出为图26所示的工艺流程200中的工艺220。密封剂80填充相邻通孔78之间的间隙以及通孔78和封装件54之间的间隙。密封剂80可以包括模塑料、模制底部填充物、环氧树脂和/或树脂。密封剂80的顶面高于金属杆78的顶端和封装件54的顶面。模塑料可以包括基底材料80A(图9中未示出，参考图25)，其可以是聚合物、树脂、环氧树脂等，以及位于基底材料中的填料颗粒80B(未示出)。填料颗粒可以是SiO2、Al2O3、二氧化硅等的介电颗粒，并且可以具有球形形状。而且，球形填料颗粒可以具有相同或不同的直径。在图25中示出了基底材料80A和填料颗粒80B。
在随后的步骤中，如图10所示，实施诸如CMP工艺或机械研磨工艺的平坦化工艺以减薄中介层40中的密封剂80和衬底22。管芯40中的密封剂80和衬底22都被抛光。根据本发明的一些实施例，实施平坦化工艺，直至中介层40中的金属杆78和通孔24暴露。另外，还露出了环绕通孔24的隔离衬垫26(图25)。由于平坦化工艺，通孔24和金属杆78的顶端与密封剂80的顶面齐平(共面)。金属杆78在下文中可选地称为通孔78，因为它们穿透密封剂80。
图11至图13示出了位于封装件54和金属杆78上面并且连接至封装件54和金属杆78的再分布结构的形成。相应的工艺示出为图26所示的工艺流程200中的工艺222。图11和图12示出了RDL的第一层和相应的介电层的形成。参考图11，形成介电层82。根据本发明的一些实施例，介电层82由诸如PBO、聚酰亚胺等的聚合物形成。形成方法包括以可流动形式涂覆介电层82，以及然后固化介电层82。根据本发明的可选实施例，介电层82由诸如氮化硅、氧化硅等的无机介电材料形成。形成方法可以包括化学汽相沉积(CVD)、原子层沉积(ALD)、等离子体增强化学汽相沉积(PECVD)或其它适用的沉积方法。然后例如通过光刻工艺形成开口84。根据其中介电层82由诸如PBO或聚酰亚胺的感光材料形成的一些实施例，开口84的形成涉及使用光刻掩模(未示出)对介电层82进行的曝光工艺，以及曝光的介电层82的显影。通孔24和78通过开口84暴露。
下一步，参考图12，形成RDL 86。RDL 86包括形成在介电层82中以接触通孔24和78的通孔86A，以及位于介电层82上方的金属迹线(金属线)86B。根据本发明的一些实施例，在镀工艺中形成RDL 86，其包括沉积金属晶种层(未示出)，在金属晶种层上方形成并且图案化光刻胶(未示出)，并且在金属晶种层上方镀金属材料，诸如铜和/或铝。金属晶种层和镀金属材料可以由相同材料或不同材料形成。然后去除图案化的光刻胶，然后蚀刻金属晶种层的先前由图案化的光刻胶覆盖的部分。图25示出了RDL 86和介电层82中的一个的放大图。
参考图13，在介电层82上方形成更多的介电层，并且在RDL 86上方形成连接至RDL86的更多的RDL。在一些实例中，介电层包括介电层88、92和96。在一些实例中，RDL包括RDL90和94。可以使用选自用于形成介电层82的候选材料的相同或不同组的材料来形成介电层88、92和96，该候选材料可以包括PBO、聚酰亚胺、BCB或其它有机或无机材料。RDL 90和94的材料和形成工艺可以与RDL 86的形成相同，包括形成晶种层，形成图案化的掩模、镀RDL 90和94，并且然后去除图案化的掩模和晶种层的不期望的部分。在整个描述中，释放膜62上方的组件统称为重构晶圆100。
如图25所示，RDL 86可以包括位于介电层82中的通孔86A和位于介电层82上方的金属线86B。由开口84(图11)形成的RDL 86的一些部分的顶面可以凹进至低于位于介电层82正上面的金属线86B的顶面。在RDL86上方形成的诸如RDL 90和94的RDL可以具有相似的轮廓。
下一步，将图13所示的重构晶圆100从载体60脱离。相应的工艺示出为图26所示的工艺流程200中的工艺224。可以通过将光束(诸如激光束)投射在释放膜62上来实施脱离，使得由光束产生的热量使释放膜62分解，并且从载体60释放重构晶圆100。然后例如通过等离子体清洁步骤去除释放膜62的残留物。所得的重构晶圆100在图14中示出。
图15示出了缓冲层64中的开口102的形成。根据一些实施例，使用激光束通过激光钻孔形成开口102。相应的工艺示出为图26所示的工艺流程200中的工艺226。RDL 66用作激光束的停止层，并且RDL 66的一些部分通过开口102暴露。根据一些实施例，还形成开口103以暴露RDL 66的一些部分。根据其它实施例，不形成开口103。开口103可以用于散热。例如，在封装所得的封装件的最终结构中，可以将热界面材料(TIM)分配至开口103中以与RDL 66接触，并且TIM也与散热器接触，以将热量散发至散热器中。
图16示出了集成无源器件(IPD)104至RDL 66的接合。相应的工艺示出为图26所示的工艺流程200中的工艺228。根据一些实施例，IPD 104包括电容器、电感器、电阻器或它们的组合，其形成为离散的器件管芯。可以通过焊料区域进行接合。底部填充物108可以分配在IPD 104和重构晶圆100之间。
图17示出了根据一些示例性实施例的凸块下金属(UBM)110和电连接件112的形成。相应的工艺示出为图26所示的工艺流程200中的工艺230。根据本发明的一些实施例，UBM 110形成为延伸至介电层96中的开口中以接触RDL 94中的金属焊盘。UBM 110可以由镍、铜、钛或它们的多层形成。根据一些示例性实施例，UBM 110包括钛层和位于钛层上方的铜层。
然后形成电连接件112。电连接件112的形成可以包括将焊球放置在UBM 110的暴露部分上，并且然后使焊球回流。所得的电连接件112是焊料区域。根据本发明的可选实施例，电连接件112的形成包括实施镀步骤以在UBM 110上方形成焊料层，并且然后使焊料层回流。电连接件112还可以包括也可以通过镀形成的非焊料金属柱，或者位于非焊料金属柱上方的金属柱和焊料盖。
下一步，将重构晶圆100放置在切割带(未示出)上，该切割带附接至框架(未示出)。根据本发明的一些实施例，电连接件112或IPD 104与切割带接触。下一步，例如使用刀片在管芯锯切工艺中分割重构晶圆100。相应的工艺示出为图26所示的工艺流程200中的工艺232。切口穿过重构晶圆100的划线114，并且形成封装件116。图18示出了根据一些实施例的所得封装件116。封装件116也称为衬底上晶圆上芯片封装件或CoWoS封装件，其中，RDL86、90和94以及相应的介电层82、88、92和96共同用作衬底97。CoWoS封装件116与常规CoWoS封装件的不同之处在于，在扇出工艺中，衬底97直接由中介层40和密封剂80形成，而不是预成型(为有芯或无芯封装衬底)并且接合至中介层。
图19至图24示出了根据本发明的可选实施例的封装件的形成中的中间阶段的截面图。这些实施例类似于图1至图18所示的实施例，除了没有在与封装件54相同的层级上形成通孔之外，没有附接IPD，并且在封装件54的一侧而不是两侧上形成RDL。除非另有说明，否则这些实施例中的组件的材料和形成工艺与相同的组件基本相同，该相同的组件在图1至图18所示的实施例中由相同的参考标号表示。因此，可以在对图1至图18所示的实施例的讨论中找到关于图19至图24所示的组件的形成工艺和材料的细节。
这些实施例的初始步骤基本上与图1至图3所示的相同，其中，形成了封装件54。下一步，参考图19，将释放膜62涂覆在载体60上，并且在释放膜62上形成缓冲层64。下一步，通过DAF 52将封装件54附接至缓冲层64。根据本发明的一些实施例，在缓冲层64上没有形成金属杆。
参考图20，将封装件54和DAF 52密封在密封剂80中。根据本发明的一些实施例，封装件54被完全密封，其中，密封剂80的顶面高于封装件54的顶面。然后固化密封剂80，随后是平坦化工艺以减薄中介层40中的半导体衬底22。所得的结构如图21所示。在平坦化工艺之后，露出通孔24(以及隔离层26，如图25所示)，其中，通孔24的顶面与密封剂80的顶面共面。
图22示出了再分布结构(衬底97)的形成，该再分布结构包括例如介电层82、88、92和96以及RDL 86、90和94。在形成再分布结构之后，将所得的重构晶圆100从载体60上脱离。在随后的工艺中，如图23所示，形成UBM 110和电连接件112。然后分割重构晶圆100，并且所得的封装件116在图24中示出。
根据一些实施例，封装件116包括DAF 52，其被密封在密封剂80中。缓冲层64可以附接至DAF 52和密封剂80。根据可选实施例，可以抛光重构晶圆100以去除缓冲层64和DAF52。图24示出了虚线120，其中，当去除缓冲层64和DAF 52时，封装件116的底面可以处于由线120表示的水平面。
如图18和图24所示的封装件116可以接合至其它封装件。例如，图18和图24中的封装件116的电连接件112可以接合至另一封装组件，诸如印刷电路板、框架、封装件等。底部填充物(未示出)也可以设置在封装件116和相应的接合封装组件之间，以保护电连接件112。可以附接TIM和散热器，其中，热界面材料位于封装件116和散热器之间并且与封装件116和散热器接触。TIM也可以延伸至图15中的开口103中。
图25示出了如图18所示的封装件116的部分124的放大图。示出了环绕通孔24的隔离衬垫26。隔离衬垫26可以由诸如氧化硅、氮化硅等的介电材料形成。隔离衬垫26和通孔24的顶面共面，并且与RDL 86中的通孔86A的底面接触。取决于通孔24和通孔86A的相对尺寸，隔离衬垫26的顶面也可以与介电层82的底面接触。此外，通孔24可以与RDL 86的晶种层接触，该晶种层可以包括例如钛。图25示出了密封剂80包括与介电层82接触的一些部分填料颗粒80B。由于填料颗粒80B的这些部分在图10所示的平坦化工艺中被抛光，因此这些部分颗粒80B可具有与介电层82接触的平坦顶面。作为比较，与介电层68接触的部分填料颗粒80B是未抛光的完整球形颗粒，并且可具有圆形的底面。
此外，封装件54中的密封剂46具有接触密封剂80的左边缘。根据一些实施例，一些部分填料颗粒46B位于密封剂46和密封剂80之间的界面处，并且部分填料颗粒46B具有与密封剂80和DAF 52接触的平坦表面。
在上面示出的实施例中，根据本发明的一些实施例讨论了一些工艺和特征。也可以包括其它特征和工艺。例如，可以包括测试结构以辅助3D封装件或3DIC器件的验证测试。测试结构可以包括例如形成在再分布层中或衬底上的测试焊盘，其允许使用探针和/或探针卡等对3D封装件或3DIC测试。验证测试可以对中间结构以及最终结构实施。另外，本文公开的结构和方法可以与结合已知良好管芯的中间验证的测试方法结合使用，以增加良率并且降低成本。
本发明的实施例具有一些有利特征。一些CoW封装件(包括中介层)很大，例如，其尺寸大于约70mm x 70mm。在常规的封装工艺中，大型的CoW封装件可包括焊料区域，并且可能还包括形成在中介层的通孔上的RDL。通过焊料区域将CoW封装件接合至预成型的封装衬底(可以是有芯或无芯的衬底)。由于CoW封装件较大，并且进一步由于在中介层的热膨胀系数(CTE)和预成型的封装衬底之间存在显著差异，这些封装件遭受诸如焊点不良、底部填充物空隙、不良平面性以及可靠性降低等问题。根据本发明的实施例，集成扇出(InFO)工艺用于直接从CoW封装件形成衬底，并且因此，没有使用焊料区域将CoW封装件接合至衬底。换句话说，中介层晶圆的减薄是在锯切中介层晶圆之后而不是之前实施的。因此，提高了所得封装件的可靠性。
根据本发明的一些实施例，方法包括将器件管芯接合至中介层，其中，中介层包括从中介层的半导体衬底的顶面延伸至半导体衬底的顶面和底面之间的中间层级的通孔；实施第一分割工艺以将中介层和器件管芯锯切成第一封装件；将第一封装件放置在载体上方；将第一封装件密封在第一密封剂中；减薄中介层的第一密封剂和半导体衬底，直至露出通孔；以及形成再分布线，其中，再分布线中的再分布线与通孔接触。在实施例中，该方法还包括形成与第一封装件和第一密封剂接触的介电层，其中，再分布线延伸至介电层中，并且其中，通孔由隔离层环绕，并且隔离层与介电层和再分布线中的一个接触。在实施例中，该方法还包括：在将器件管芯接合至中介层之后，将器件管芯密封在第二密封剂中，其中，在第一分割工艺中，切穿第二密封剂。在实施例中，中介层没有有源器件。在实施例中，在减薄中介层的半导体衬底之前，半导体衬底的部分与通孔重叠，并且在减薄中去除半导体衬底的部分。在实施例中，该方法还包括在载体上方形成金属杆，其中，金属杆密封在第一密封剂中，并且其中，在减薄第一密封剂之后，露出金属杆。在实施例中，该方法还包括在载体上方形成附加再分布线，其中，将第一封装件放置在附加再分布线上方；并且将无源器件接合至其它再分布线。在实施例中，该方法还包括实施第二分割工艺以形成第二封装件，其中，第一封装件和部分第一密封剂以及部分再分布线位于第二封装件中。
根据本发明的一些实施例，方法包括：将多个中介层密封在密封剂中，其中，多个中介层通过密封剂彼此分隔开，其中，多个中介层包括延伸至多个中介层中的半导体衬底中的通孔；抛光中介层以去除半导体衬底的部分，其中，通孔的表面露出；在半导体衬底和多个中介层的通孔上方形成与半导体衬底和多个中介层的通孔接触的第一介电层；形成延伸至第一介电层中以接触多个中介层的通孔的再分布线；并且切穿密封剂以将多个中介层分成多个封装件。在实施例中，在切穿密封剂中，没有切穿中介层。在实施例中，该方法还包括接合多个器件管芯，其中，多个器件管芯中的每个都接合至多个中介层中的一个，其中，密封剂包括与多个中介层处于同一层级的第一部分，以及与多个器件管芯处于同一层级的第二部分。在实施例中，该方法还包括：将多个器件管芯中的一个密封在附加密封剂中；在将多个中介层密封在密封剂中之前，切穿附加密封剂。在实施例中，第一介电层在密封剂上方延伸，其中，第一介电层的底面与密封剂的顶面接触。在实施例中，中介层中没有有源器件和无源器件。
根据本发明的一些实施例，集成电路器件包括：封装件，该封装件包括器件管芯；与器件管芯接合的中介层，其中，中介层包括：半导体衬底；以及穿透半导体衬底的通孔；第一密封剂，将封装件密封在其中；接触半导体衬底和第一密封剂的介电层；以及延伸至介电层中的再分布线，其中，再分布线中的再分布线与通孔接触。在实施例中，中介层还包括环绕通孔的隔离衬垫，其中，隔离衬垫将通孔与半导体衬底分隔开，并且隔离衬垫与再分布线和介电层中的一个接触。在实施例中，中介层中没有有源器件。在实施例中，封装件还包括将器件管芯密封在其中的第二密封剂，其中，第二密封剂的侧壁与中介层的相应侧壁齐平。在实施例中，集成电路器件还包括穿透第一密封剂的金属杆；以及位于所述第一密封剂的与所述再分布线相对的侧上的无源器件，其中，所述无源器件电耦接至所述金属杆。在实施例中，集成电路器件还包括与封装件接触的粘合膜，其中，该粘合膜被密封在第一密封剂中。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成集成电路器件的方法，包括：
将器件管芯接合至中介层，其中，所述中介层包括从所述中介层的半导体衬底的顶面延伸至所述半导体衬底的所述顶面和底面之间的中间层级的通孔；
实施第一分割工艺以将所述中介层和所述器件管芯锯切成第一封装件；
将所述第一封装件放置在载体上方；
将所述第一封装件密封在第一密封剂中；
减薄所述中介层的所述第一密封剂和所述半导体衬底，直至露出所述通孔；以及
形成再分布线，其中，所述再分布线中的再分布线与所述通孔接触。
2.根据权利要求1所述的方法，还包括，形成与所述第一封装件和所述第一密封剂接触的介电层，其中，所述再分布线延伸至所述介电层中，并且其中，所述通孔由隔离层环绕，并且所述隔离层与所述介电层和所述再分布线中的一个接触。
3.根据权利要求1所述的方法，还包括，在将所述器件管芯接合至所述中介层之后，将所述器件管芯密封在第二密封剂中，其中，在所述第一分割工艺中，切穿所述第二密封剂。
4.根据权利要求1所述的方法，其中，所述中介层没有有源器件。
5.根据权利要求1所述的方法，其中，在减薄所述中介层的所述半导体衬底之前，所述半导体衬底的部分与所述通孔重叠，并且在所述减薄中去除所述半导体衬底的所述部分。
6.根据权利要求1所述的方法，还包括：
在所述载体上方形成金属杆，其中，将所述金属杆密封在所述第一密封剂中，并且其中，在所述减薄所述第一密封剂之后，露出所述金属杆。
7.根据权利要求1所述的方法，还包括：
在所述载体上方形成附加再分布线，其中，将所述第一封装件放置在所述附加再分布线上方；以及
将无源器件接合至所述附加再分布线。
8.根据权利要求1所述的方法，还包括，实施第二分割工艺以形成第二封装件，其中，所述第一封装件和部分所述第一密封剂以及部分所述再分布线位于所述第二封装件中。
9.一种形成集成电路器件的方法，包括：
将多个中介层密封在密封剂中，其中，所述多个中介层通过所述密封剂彼此分隔开，其中，所述多个中介层包括延伸至所述多个中介层中的半导体衬底中的通孔；
抛光所述中介层以去除所述半导体衬底的部分，其中，所述通孔的表面露出；
在所述半导体衬底和所述多个中介层的所述通孔上方形成与所述半导体衬底和所述多个中介层的所述通孔接触的第一介电层；
形成延伸至所述第一介电层中以接触所述多个中介层的所述通孔的再分布线；以及
切穿所述密封剂以将所述多个中介层分成多个封装件。
10.一种集成电路器件，包括：
封装件，包括：
器件管芯；
中介层，与所述器件管芯接合，其中，所述中介层包括：
半导体衬底；以及
通孔，穿透所述半导体衬底；
第一密封剂，将所述封装件密封在所述第一密封剂中；
介电层，与所述半导体衬底和所述第一密封剂接触；以及
再分布线，延伸至所述介电层中，其中，所述再分布线中的再分布线与所述通孔接触。
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