CN107180795A - 包括电压调节器的集成扇出封装件及其形成方法 - Google Patents

包括电压调节器的集成扇出封装件及其形成方法 Download PDF

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Publication number
CN107180795A
CN107180795A CN201611150397.8A CN201611150397A CN107180795A CN 107180795 A CN107180795 A CN 107180795A CN 201611150397 A CN201611150397 A CN 201611150397A CN 107180795 A CN107180795 A CN 107180795A
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tube core
voltage regulator
regulator tube
redistribution lines
encapsulant
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CN201611150397.8A
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CN107180795B (zh
Inventor
余振华
张智援
王垂堂
谢政宪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种方法包括通过管芯附接膜将电压调节器管芯粘附在载体上方，其中管芯附接膜位于电压调节器管芯中并环绕电压调节器管芯的金属柱，将电压调节器管芯密封在密封材料中，并且平坦化密封材料。去除电压调节器管芯的背部以暴露电压调节器管芯的半导体衬底中的通孔。该方法还包括在密封材料上方形成电连接至通孔的第一再分布线，用介电材料替代管芯附接膜，在密封材料的与第一再分布线相对的侧上形成第二再分布线，并且将额外的器件管芯接合至第二再分布线。电压调节器管芯电连接至额外的器件管芯。本发明实施例涉及包括电压调节器的集成扇出封装件及其形成方法。

Description

包括电压调节器的集成扇出封装件及其形成方法
技术领域
本发明实施例涉及包括电压调节器的集成扇出封装件及其形成方法。
背景技术
在集成电路中，诸如片上系统(SOC)管芯和中央处理单元(CPU)的一些电路组件对输入/输出(IO)和功率消耗具有高要求。例如，CPU可包括多个核心，并且需要消耗相当多的功率。另一方面，对提供的功率的要求也高。例如，电源电压需要非常稳定。因此，多个电压调节器可被连接至CPU芯片和SOC管芯，以提供功率。
发明内容
根据本发明的一些实施例，提供了一种形成封装件的方法，包括：通过管芯附接膜将电压调节器管芯粘附至载体上方，所述管芯附接膜位于所述电压调节器管芯中并且环绕所述电压调节器管芯的金属柱；将所述电压调节器管芯密封在密封材料中；平坦化所述密封材料，其中，去除所述电压调节器管芯的背部以暴露位于所述电压调节器管芯的半导体衬底中的通孔；在所述电压调节器管芯和所述密封材料上方形成第一介电层；在所述第一介电层中形成第一再分布线，其中，所述第一再分布线的部分电连接至所述通孔；用介电材料替代所述管芯附接膜；形成第二介电层，其中，所述第一介电层和所述第二介电层位于所述电压调节器管芯的相对两侧上；在所述第二介电层中形成第二再分布线；以及将额外的器件管芯接合至所述第二再分布线，并且将所述电压调节器管芯电连接至所述额外的器件管芯。
根据本发明的另一些实施例，还提供了一种形成封装件的方法，包括：在载体上方形成基底层；在所述基底层上方形成导电柱；将电压调节器管芯粘附至所述基底层，其中，所述电压调节器管芯包括管芯附接膜，并且所述管芯附接膜粘附至所述基底层；将所述电压调节器管芯和所述导电柱密封在密封材料中；平坦化所述密封材料，直到暴露出所述电压调节器管芯和所述导电柱；在所述电压调节器管芯和所述密封材料上方形成第一介电层；在所述第一介电层中形成第一再分布线，其中，所述第一再分布线的部分电连接至所述导电柱；用介电材料替代所述管芯附接膜；形成第二介电层，其中，所述第一介电层和所述第二介电层位于所述电压调节器管芯的相对两侧上；在所述第二介电层中形成第二再分布线；以及将额外的器件管芯接合至所述第二再分布线。
根据本发明的又一些实施例，还提供了一种封装件，包括：电压调节器管芯，包括：半导体衬底；通孔，穿透所述半导体衬底；以及金属柱，位于所述电压调节器管芯的顶面处；第一密封材料，将所述电压调节器管芯密封在所述密封材料中；多个第一再分布线，位于所述电压调节器管芯和所述第一密封材料上方，其中，多个所述第一再分布线的部分与所述通孔和所述金属柱物理接触；器件管芯，接合至所述多个第一再分布线；以及多个第二再分布线，位于所述第一密封材料的下面，其中，所述多个第二再分布线电连接至所述多个第一再分布线。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳地理解本发明的各个方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或减小。
图1至图20示出根据一些实施例的形成包括电压调节器的封装件的中间阶段的截面图。
图21至图30示出根据一些实施例的形成包括电压调节器的封装件的中间阶段的截面图。
图31示出根据一些实施例的用于形成封装件的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且还可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，并且在此使用的空间相对描述符可以同样地作出相应的解释。
根据各个示例性实施例，提供了集成扇出(InFO)封装件及其形成方法。InFO封装件可用于改进电源的性能。根据一些实施例示出形成封装件的中间阶段。讨论了一些实施例的一些变化。贯穿各个视图和示例性实施例，相同的参考标号用于指定相同的元件。
图1至图20示出根据一些实施例的形成多层级封装件的中间阶段的截面图。图1至图20中示出的步骤还在图31中示出的工艺流程图200中示意性地示出。
参照图1，提供了载体20，并且在载体20上方设置基底层22。载体20可以是空白玻璃载体、空白陶瓷载体、有机载体等并且可具有带有圆形顶视图形状的半导体晶圆的形状。载体20有时称为载体晶圆。根据一些实施例，存在位于基底层22和载体20之间的光热转换(LTHC)层(未示出)。LTHC能够在光的热下分解，并且因此在后续步骤中可用于从载体20分离基底层22。根据本发明的一些实施例，基底层22由诸如聚酰亚胺、聚苯并恶唑(PBO)等的树脂基和/或聚合物基材料形成。
图2至图3示出根据本发明的一些实施例形成导电柱。对应的步骤是在图31示出的工艺中示出为步骤202。参照图2，例如通过物理汽相沉积(PVD)或金属箔层压在基底层22上形成晶种层24。晶种层24可以由铜、铝、钛或它们的多层形成。根据本发明的一些实施例，晶种层24包括钛层(未单独示出)和位于钛层上方的铜层(未单独示出)。根据可选实施例，晶种层24包括单个铜层。
在晶种层24上方施加光刻胶26并且然后图案化光刻胶，并且通过曝光和显影步骤在光刻胶26中形成开口28。结果，通过开口28暴露晶种层24的一些部分。
接下来，如图3所示，通过镀(可以是电镀或化学镀)在开口28中形成导电柱30。在图2中，在晶种层24的暴露的部分上镀导电柱30。导电柱30可包括铜、铝、钨、镍或它们的合金。导电柱30的顶视图形状包括，并且不限制于，螺旋形、环形、矩形、正方形、圆形等，这取决于导电柱30的预期功能和可用空间。通过后续放置的集成电路芯片的厚度来确定导电柱30的高度。
在镀导电柱30之后，去除光刻胶26(图2)，并且在图3中示出所得到的结构。暴露晶种层24的先前通过光刻胶26覆盖的部分(图2)。然后实施蚀刻步骤以去除晶种层24的暴露部分，其中蚀刻可以是各向异性或各向同性蚀刻。另一方面，晶种层24的与导电柱30重叠的部分保持不被蚀刻。在整个说明书中，剩余的下面部分的晶种层24被认为是导电柱30的底部。当晶种层24由与对应的上面的导电柱30类似或相同的材料形成时，晶种层24可以与导电柱30合并而在它们之间没有可辨别的界面。因此，在后续的图中未示出晶种层24。根据本发明的可选实施例，在晶种层24和上面的镀的导电柱30的部分之间存在可辨别的界面。
参照图4，在基底层22上方放置器件管芯100(包括100A、100B、100C和100D，它们统称为器件管芯100)。根据本发明的一些实施例，器件管芯100是电压调节器(VR)管芯，其包括用于调节上面的管芯的的电压供应的电压调节器。VR中的电路示意性地示出为126，其形成在半导体衬底128上。器件管芯100的放置在图31示出的工艺中示出为步骤204。应该理解，在晶圆级实施后续讨论的工艺步骤。因此，存在与包括器件管芯100A、100B、100C和100D的管芯组相同的多个管芯组。应该理解，尽管示出了4个VR，但VR管芯的数量可以是任何数量。多个管芯组可布置为包括多行和多列的阵列。在任何组合中，器件管芯100的一些或全部可以彼此相同或彼此不同。
VR电路126可包括可用于调节电压的模拟泵电路、数字控制块和其他电路。例如，模拟泵电路可用于将电流泵入上面的逻辑管芯。数字控制块具有确定模拟电路何时需要泵电流的功能。当用在高级VR中时，数字控制块可以确定需要打开多少模拟泵的相，从而优化输出至上面的器件管芯的电流。此外，器件管芯100还可包括电连接至模拟泵电路和数字控制块的内置电感器。
根据本发明的一些实施例，器件管芯100的一些或全部是独立的VR管芯，其中除了那些之外的其他逻辑电路不被内置在器件管芯100中的电压调节器电路使用。根据可选实施例，一些逻辑电路或存储器电路与电压调节器电路一起构建在一些或全部器件管芯100内部。
器件管芯100包括半导体衬底128，其可以是硅衬底、硅碳衬底、Ⅲ-Ⅴ化合物半导体衬底等。器件管芯100还包括互连结构132。根据本发明的一些实施例，互连结构132包括多个介电层135，和位于介电层135中的金属线和通孔。例如，介电层135可包括金属间介电(IMD)层，其可以由具有低于约3.5、低于约3.0或低于约2.5的介电常数(k值)的低k介电材料形成。此外，接近于器件管芯100的前表面(示出的底面)，可以存在诸如氮化硅层、氧化硅层、未掺杂硅酸盐玻璃(USG)层和/或聚合物层的非低k钝化层。此外，在互连结构132的表面处存在位于表面介电层134中的金属柱140(包括140A和140B)。金属柱140可以是含铜的柱/焊盘、含铝的柱/焊盘等。根据一些实施例，示出的介电层134的底面与金属柱140的底面共面。根据一些实施例，介电层134是管芯附接膜，其是粘合剂，器件管芯100通过该管芯附接膜粘附至基底层22。管芯附接膜134环绕金属柱140。
内置电感器(未示出，如果有的话)可以嵌入在互连结构132中，并且还是电压调节器电路的部分。电感器可以使用互连的金属线和通孔来形成以具有线圈形状。此外，根据本发明的一些实施例，电感器是与VR电路集成在相同的芯片中的芯片上电感器。根据本发明的可选实施例，电感器作为独立的电感器形成在VR管芯100的外部。
器件管芯100还包括通孔(可选地称为硅通孔或衬底通孔)136(包括136A和136B)。通孔136可以延伸至半导体衬底128的顶面和底面之间的中间水平。通孔136的每个通过环绕相应的通孔136的介电层(未示出)与相应的半导体衬底128电绝缘。
根据本发明的一些实施例，通孔136用于互连半导体衬底128的相对侧上的导电部件。根据可选实施例，没有形成贯穿半导体衬底128的通孔。当形成时，通孔136可以仅用于互连器件管芯100的相对侧上的部件，和/或用于连接器件管芯100中的电路。例如，通孔136B可以电连接至相应的器件管芯100内部的器件126(诸如，VR电路、电感器等)。通孔136B还可电连接至金属柱140B。另一方面，器件管芯100中的通孔136A仅用于将相应的器件管芯100上方的导电部件(诸如图20中的器件管芯66A、66B和66C)连接至器件管芯100下面的导电部件(诸如图20中的封装组件76中的金属焊盘)。根据一些示例性实施例，通孔136A不连接至器件管芯100内部的任何其他电路(包括诸如晶体管和二极管的有源器件和诸如电容器、电感器、电阻器等的无源器件)。因此，通孔136A仅用于互连器件管芯100的外部的部件，并且不用于器件管芯100内部的电路的内部连接。或者说，通孔136A具有与导电柱30相同的功能。有利地，在器件管芯100内部形成通孔136A不会导致额外的制造成本，因为它们与通孔136B同时形成。此外，由于使用用于形成器件管芯的技术来形成通孔136A，所以通孔136可以具有比导电柱高得多的密度和更小的尺寸，并且可以容纳在相应的封装件中的通孔136A的总数可比导电柱30高得多。因此，形成通孔136A是对导电柱30的有益补充。
通孔136A的每个连接至导电路径中的一个，该导电路径将相应的通孔136A电连接至金属柱140A。导电路径可以包括介电层中的金属线/焊盘和金属通孔。导电路径可以是没有分支/叉的单路由路径，并且不连接至相应的器件管芯100中的任何其他金属柱140B、电感器、电阻器、电容器、晶体管、二极管等。因此，虽然位于器件管芯100中，但是通孔136A不涉及与电压调节器相关的电压/信号传输。
参考图5，器件管芯100被密封在密封材料44中。相应的步骤在图31示出的工艺中示出为步骤206。例如，在热固化工艺中分配且然后固化该密封材料44。密封材料44填充器件管芯100之间的间隙，并且可以与基底层22接触。密封材料44可以包括模塑料、模制底部填充物、环氧树脂和/或树脂。在密封工艺之后，密封材料44的顶面高于器件管芯100。
接下来，实施诸如化学机械抛光(CMP)步骤或研磨步骤的平坦化步骤以平坦化密封材料44，并且以暴露导电柱30。还去除器件管芯100的衬底128的部分，直到暴露器件管芯100的通孔136。由于平坦化，通孔136的顶面与密封材料44的顶面大致齐平(共面)。
图6至图8示出在器件管芯100的背侧上形成背侧再分布线(RDL)。相应的步骤在图31示出的工艺中示出为步骤208。参照图6，形成介电层46以覆盖器件管芯100和密封材料44。接下来，如图7所示，形成RDL 48以穿透如图6所示的介电层46。还可以形成更多的介电层46。根据本发明的一些实施例，介电层46由诸如PBO、聚酰亚胺等的聚合物形成。根据本发明的一些实施例，介电层46由诸如氮化硅、氧化硅、氮氧化硅等的无机介电材料形成。
RDL 48形成为电连接至通孔136和导电柱30。RDL 48可以包括金属迹线(金属线)和通孔，该通孔位于相应的金属迹线下面并且连接至相应金属迹线。根据本发明的一些实施例，通过镀工艺形成RDL 48，其中，RDL48的每个包括晶种层(未示出)和位于晶种层上方的镀的金属材料。晶种层和镀的金属材料可以由相同材料或不同材料形成。在RDL 48的形成期间，图案化介电层46以形成通孔开口(由RDL 48占据)，并且上层级RDL48延伸到通孔开口中以接触下层级RDL 48。此外，RDL 48的一些可以与器件管芯100中的通孔136和导电柱30物理接触。
参照图8，形成凸块下金属(UBM)50(或金属焊盘)以连接至RDL 48。UBM 50可以包括钛、铜、镍等。所得到的结构包括基底层22、器件管芯100、密封材料44和上面的部件，所得到的结构在下文中称为复合晶圆52。
接下来，实施载体转换，其中载体54(图9)粘附至复合晶圆52的与载体20(图8)相对的一侧，接着卸下载体20。相应的步骤在图31所示的工艺流程中示出为步骤210。通过对LTHC投射UV光或激光束来实施复合晶圆52与载体20的脱黏。由UV光或激光产生的热使LTHC分解，并且因此载体20与复合晶圆52分离。图9中示出所得到的结构。因此暴露基底层22。可以通过粘合膜56在载体54上安装复合晶圆52。
然后去除基底层22，并且在图10中示出所得到的结构，其中暴露管芯附接膜134。接下来，图11至图13示出用介电层58替代管芯附接膜134。参考图11，例如使用湿蚀刻工艺去除管芯附接膜134(图1)。相应的步骤在图31示出的工艺流程中示出为步骤212。因此形成凹槽144。在图12中，设置介电材料58，其中介电材料58填充凹槽144，并且可以具有位于管芯100上方的一些部分。相应的步骤在图31示出的工艺流程中示出为步骤214。根据一些实施例，介电材料58由聚苯并恶唑(PBO)、聚酰亚胺等形成。在后续步骤中，如图13所示，实施诸如研磨或CMP的平坦化以去除多余的介电材料58。保留的介电材料58的顶面与密封材料44的顶面和导电柱30的顶面大致共面。保留的介电材料58(其现在成为器件管芯100的部分)还具有与器件管芯100的下面的部分的相应边缘相邻(垂直对准)的边缘。
图14示出在介电层60中形成介电层60和RDL 62。相应的步骤在图31示出的工艺流程中示出为步骤216。材料和形成方法基本上类似于介电层46和RDL48的材料和形成方法，因此在此不再重复。在后续步骤中，如图15所示，形成UBM 64，其可以由与UBM 50类似的材料形成。
图16示出将封装组件66(包括66A、66B和66C，统称为封装组件66)接合到RDL 62中暴露的金属焊盘上。相应的步骤在图31示出的工艺流程中示出为步骤218。封装组件66可以通过焊料区68接合至UBM64。还可以通过金属到金属的直接接合(例如，通过微凸块)、混合接合、熔融接合等来实现接合。封装组件66的每个可以是封装件、器件管芯或管芯堆叠件。例如，封装组件66B可以是片上系统(SOC)管芯，并且封装组件66A和66C可以是中央处理单元(CPU)管芯、图形处理单元(GPU)管芯、移动应用管芯、存储器管芯或管芯堆叠件。存储器管芯可以是高带宽存储器(HBM)立方体的形式。封装组件66可具有位于相应的管芯中的相应的半导体衬底(未示出)，其中半导体衬底的背面朝上。封装组件66还包括在相应的半导体衬底的正面(朝下的表面)处的集成电路器件(诸如有源器件，例如，包括晶体管，未示出)。
根据一些实施例，封装组件66的每个电连接至VR管芯100的一个并且通过VR管芯100的一个提供电压。根据一些实施例，封装组件66可以直接与供应电压的相应的VR管芯100重叠。例如，如图16所示，器件管芯100A为封装组件66A供应和调节电压，器件管芯100B和100C为封装组件66B供应和调节电压，并且器件管芯100D为封装组件66C供应和调节电压。器件管芯100A、100B/100C和100D的一些或全部可以分别单独地供应和调节封装组件66A、66B、66C的电压，并且不供应和调节其他封装组件的电压。通过使封装组件66直接位于其电压供应器上，有利地最小化用于将VR管芯100连接至相应的电压用户66的金属线(RDL62)的长度，并且有利地最小化由金属线的电阻导致的电压降。
参照图17，在封装组件66上密封密封材料69。密封材料69可以包括模塑料、模制底部填充物、环氧树脂或树脂。密封材料69的底面物理地接触顶部介电层60的顶面。在分配之后，例如，在热固化工艺中固化密封材料69。根据本发明的一些实施例，实施平坦化步骤以平坦化密封材料69，直到密封材料69的顶面与封装组件66的顶面共面。相应的步骤在图31示出的工艺流程中示出为步骤220。
接下来，复合晶圆52从载体54脱粘。图18中示出所得到的结构。例如，可以通过焊料滴落和回流在UBM 50上形成焊料区70。
在后续步骤中，实施管芯锯切以将复合晶圆52锯切成彼此相同的离散的封装件72，其中在图19中示出的离散的封装件72的一个。相应的步骤在图31示出的工艺流程中示出为步骤222。由于封装件72是从复合晶圆52(图18)锯切的，所以密封材料44的边缘与相应的密封材料69的相应的边缘垂直对准(共边界)。此外，密封材料44的边缘也与介电层46和60的相应的边缘垂直地对准。
又参考图19，将封装件72接合至封装组件76。相应的步骤在图31示出的工艺流程图中示出为步骤222。根据一些示例性实施例，通过焊料区70实施接合。封装组件76具有构建在其中的金属线和通孔(未示出)以互连位于封装组件76的相对侧上的部件。封装组件76可以是封装衬底，其是层压衬底(无核心)或可具有核心。封装组件76还可以是中介层，其包括形成在半导体衬底上的RDL，具有穿透半导体衬底的通孔(未示出)。封装组件76中的导电迹线和/或核心(未示出)电连接到焊料区70和71。然后分配底部填充物74以保护接合。
参考图20，散热器78通过热界面材料(TIM)82粘附至封装组件72，所述热界面材料(TIM)82是粘合剂，并且具有的热导率高于典型粘合剂的热导率。相应的步骤在图31出示的工艺流程中示出为步骤224。散热器78还可以通过粘合剂80固定到封装组件76上。
图21至图30示出根据本发明的一些实施例的形成扇出封装件的中间阶段的截面图。除非另有声明，这些实施例中的组件的材料和形成方法与相同的组件基本上相同，相同的组件由图1至图20中示出的实施例中的相同的参考标号表示。因此，关于图21至图30中示出的组件的形成工艺和材料的细节可以在图1至图21中示出的实施例的讨论中找到。除了没有在器件管芯100中预先形成金属柱140(参照图20中的140A和140B)之外，图21至30中示出的工艺类似于图1至图20中示出工艺。相反，在封装器件管芯100之后形成金属柱140。
这些实施例的初始步骤与图1至图3中示出的步骤基本相同。接下来，如图21所示，将器件管芯100粘附至基底层22。除了没有在如图21所示在器件管芯100中形成金属柱140(包括图20中的140A和140B)之外，图21所示的器件管芯100与图4所示的基本相同。因此，图21中的管芯附接膜134是毯状膜，并且没有暴露诸如金属焊盘146的非导电部件以接触基底层22。图22至图27示出的后续工艺步骤与图5至图10中示出的工艺步骤基本相同。例如，图22示出密封材料44的分配和平坦化。图23至25示出介电层46、RDL 48和UBM 50的形成。图26示出载流子转换，接着去除基底层22，其中在图27中示出所得到的结构。
接下来，去除管芯附接膜134，形成如图28所示的凹槽137。将介电层148和金属焊盘146的中心部分暴露于凹槽137。通过介电层148覆盖金属焊盘146的边缘部分。在图29中，形成并图案化光刻胶86，其中金属焊盘146暴露于形成在光刻胶86中的开口88。接下来，实施镀步骤以形成金属柱140(包括140A和140B)，接着去除光刻胶86，并且在图30中示出所得到的结构。后续步骤与图12至图20中示出的基本相同，并且因此本文中不再重复。
本发明的实施例具有一些有利特征。通过将VR管芯直接放置在相应的供应有电压的器件管芯(诸如66A)的下面，使得从器件管芯至它们的电压调节器的距离最小化。减小了金属线的电阻，并且改进了功率效率。作为对比，如果VR管芯放置在核心芯片的旁边，金属线会长得多，并且由于金属线的电阻引起的电压降较高。此外，布局是不平衡的，因为VR管芯更接近于一些电压用户并且远离其他电压用户。根据本发明的实施例，VR管芯被直接放置在VR管芯100所服务的器件管芯的下面，因此布局是平衡的。
根据本发明的一些实施例，方法包括通过管芯附接膜将电压调节器芯片粘附在载体上方，其中管芯附接膜位于电压调节器管芯中并环绕电压调节器管芯的金属柱，将电压调节器管芯密封在密封材料中，并且平坦化密封材料。去除电压调节器管芯的背部以暴露电压调节器管芯的半导体衬底中的通孔。该方法还包括在电压调节器管芯和密封材料上方形成第一介电层，在第一介电层中形成第一再分布线，其中第一再分布线的部分电连接至通孔，用介电材料替代管芯附接膜，形成第二介电层，其中第一和第二介电层位于电压调节器管芯的相对侧上，在第二介电层中形成第二再分布线，以及将额外的器件管芯接合至第二再分布线，其中电压调节器管芯电连接至额外的器件管芯。
根据本发明的一些实施例，方法包括在载体上方形成基底层，在基底层上方形成导电柱，并且将导电调节器管芯粘附至基底层。电压调节器管芯包括管芯附接膜，并且管芯附接膜粘附至基底层。该方法还包括将电压调节器管芯和导电柱密封在密封材料中，平坦化密封材料直到暴露电压调节器管芯和导电柱，在电压调节器管芯和密封材料上方形成第一介电层，在第一介电层中形成第一再分布线，其中第一再分布线的部分电连接至导电柱，并且用介电材料替代管芯附接膜，形成第二介电层。第一和第二介电层位于电压调节器管芯的相对侧上。在第二介电层中形成第二再分布线。将额外的器件管芯接合至第二再分布线。
根据本发明的一些实施例，封装件包括电压调节器管芯，其还包括半导体衬底，穿透半导体衬底的通孔，和位于电压调节器管芯的顶面处的金属柱。封装件还包括将电压调节器管芯密封在其中的第一密封材料，以及位于电压调节器管芯和第一密封材料上方的多个第一再分布线。多个第一再分布线的部分与通孔和金属柱物理接触。器件管芯接合至多个第一再分布线。多个第二再分布线位于第一密封材料下面。多个第二再分布线电连接至多个第一再分布线。
根据本发明的一些实施例，提供了一种形成封装件的方法，包括：通过管芯附接膜将电压调节器管芯粘附至载体上方，所述管芯附接膜位于所述电压调节器管芯中并且环绕所述电压调节器管芯的金属柱；将所述电压调节器管芯密封在密封材料中；平坦化所述密封材料，其中，去除所述电压调节器管芯的背部以暴露位于所述电压调节器管芯的半导体衬底中的通孔；在所述电压调节器管芯和所述密封材料上方形成第一介电层；在所述第一介电层中形成第一再分布线，其中，所述第一再分布线的部分电连接至所述通孔；用介电材料替代所述管芯附接膜；形成第二介电层，其中，所述第一介电层和所述第二介电层位于所述电压调节器管芯的相对两侧上；在所述第二介电层中形成第二再分布线；以及将额外的器件管芯接合至所述第二再分布线，并且将所述电压调节器管芯电连接至所述额外的器件管芯。
在上述方法中，还包括：在所述载体上方形成导电柱，其中，所述导电柱被所述密封材料密封，并且所述导电柱将所述第一再分布线电互连至所述第二再分布线。
在上述方法中，替代所述管芯附接膜包括：蚀刻所述管芯附接膜以在所述密封材料中形成凹槽；在所述凹槽内填充所述介电材料；以及实施额外的平坦化以去除所述介电材料的多余部分，直到暴露所述电压调节器管芯中的金属柱。
在上述方法中，还包括：将所述额外的器件管芯密封在额外的密封材料中。
在上述方法中，将所述通孔与所述电压调节器管芯中的所有电路电断开。
在上述方法中，当所述电压调节器管芯粘附至所述载体时，所述管芯附接膜环绕所述电压调节器管芯的金属柱，并且所述金属柱的表面与所述管芯附接膜的朝向所述载体的表面共面。
在上述方法中，用所述介电材料替代所述管芯附接膜包括：蚀刻所述管芯附接膜以在所述密封材料中形成凹槽；在所述电压调节器管芯中从金属焊盘形成所述金属柱；在所述凹槽内填充所述介电材料；以及实施额外的平坦化以去除所述介电材料的多余部分，直到暴露所述金属柱。
根据本发明的另一些实施例，还提供了一种形成封装件的方法，包括：在载体上方形成基底层；在所述基底层上方形成导电柱；
将电压调节器管芯粘附至所述基底层，其中，所述电压调节器管芯包括管芯附接膜，并且所述管芯附接膜粘附至所述基底层；将所述电压调节器管芯和所述导电柱密封在密封材料中；平坦化所述密封材料，直到暴露出所述电压调节器管芯和所述导电柱；在所述电压调节器管芯和所述密封材料上方形成第一介电层；在所述第一介电层中形成第一再分布线，其中，所述第一再分布线的部分电连接至所述导电柱；用介电材料替代所述管芯附接膜；形成第二介电层，其中，所述第一介电层和所述第二介电层位于所述电压调节器管芯的相对两侧上；在所述第二介电层中形成第二再分布线；以及将额外的器件管芯接合至所述第二再分布线。
在上述方法中，当平坦化所述密封材料时，去除所述电压调节器管芯的背部以暴露所述电压调节器管芯的半导体衬底中的通孔，并且其中，所述通孔将所述第一再分布线电连接至所述第二再分布线。
在上述方法中，将所述通孔与所述电压调节器管芯中的所有有源电路电断开。
在上述方法中，替代所述管芯附接膜包括：蚀刻所述管芯附接膜以在所述密封材料中形成凹槽；在所述凹槽内填充所述介电材料；以及实施额外的平坦化以去除所述介电材料的多余部分，直到暴露所述电压调节器管芯中的金属柱。
在上述方法中，当所述电压调节器管芯粘附至所述基底层时，所述管芯附接膜环绕所述电压调节器管芯的金属柱，并且所述金属柱的表面与所述基底层接触。
在上述方法中，用所述介电材料替代所述管芯附接膜包括：蚀刻所述管芯附接膜以在所述密封材料中形成凹槽；在所述电压调节器管芯中从金属焊盘形成金属柱；在所述凹槽内填充所述介电材料；以及实施额外的平坦化以去除所述介电材料的多余部分，直到暴露所述金属柱。
在上述方法中，还包括将所述额外的器件管芯密封在额外的密封材料中。
根据本发明的又一些实施例，还提供了一种封装件，包括：电压调节器管芯，包括：半导体衬底；通孔，穿透所述半导体衬底；以及金属柱，位于所述电压调节器管芯的顶面处；第一密封材料，将所述电压调节器管芯密封在所述密封材料中；多个第一再分布线，位于所述电压调节器管芯和所述第一密封材料上方，其中，多个所述第一再分布线的部分与所述通孔和所述金属柱物理接触；器件管芯，接合至所述多个第一再分布线；以及多个第二再分布线，位于所述第一密封材料的下面，其中，所述多个第二再分布线电连接至所述多个第一再分布线。
在上述封装件中，还包括：导电柱，穿透所述第一密封材料。
在上述封装件中，所述通孔的表面，所述导电柱的表面和所述第一密封材料的表面彼此共面。
在上述封装件中，所述器件管芯包括片上系统管芯。
在上述封装件中，还包括第二密封材料，将所述器件管芯密封在所述第二密封材料中，其中，所述第一密封材料的边缘与所述第二密封材料的相应的边缘彼此垂直地对准。
在上述封装件中，所述器件管芯与所述电压调节器管芯直接重叠。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成封装件的方法，包括：
通过管芯附接膜将电压调节器管芯粘附至载体上方，所述管芯附接膜位于所述电压调节器管芯中并且环绕所述电压调节器管芯的金属柱；
将所述电压调节器管芯密封在密封材料中；
平坦化所述密封材料，其中，去除所述电压调节器管芯的背部以暴露位于所述电压调节器管芯的半导体衬底中的通孔；
在所述电压调节器管芯和所述密封材料上方形成第一介电层；
在所述第一介电层中形成第一再分布线，其中，所述第一再分布线的部分电连接至所述通孔；
用介电材料替代所述管芯附接膜；
形成第二介电层，其中，所述第一介电层和所述第二介电层位于所述电压调节器管芯的相对两侧上；
在所述第二介电层中形成第二再分布线；以及
将额外的器件管芯接合至所述第二再分布线，并且将所述电压调节器管芯电连接至所述额外的器件管芯。
2.根据权利要求1所述的方法，还包括：在所述载体上方形成导电柱，其中，所述导电柱被所述密封材料密封，并且所述导电柱将所述第一再分布线电互连至所述第二再分布线。
3.根据权利要求1所述的方法，其中，替代所述管芯附接膜包括：
蚀刻所述管芯附接膜以在所述密封材料中形成凹槽；
在所述凹槽内填充所述介电材料；以及
实施额外的平坦化以去除所述介电材料的多余部分，直到暴露所述电压调节器管芯中的金属柱。
4.根据权利要求1所述的方法，还包括：将所述额外的器件管芯密封在额外的密封材料中。
5.根据权利要求1所述的方法，其中，将所述通孔与所述电压调节器管芯中的所有电路电断开。
6.根据权利要求1所述的方法，其中，当所述电压调节器管芯粘附至所述载体时，所述管芯附接膜环绕所述电压调节器管芯的金属柱，并且所述金属柱的表面与所述管芯附接膜的朝向所述载体的表面共面。
7.根据权利要求1所述的方法，其中，用所述介电材料替代所述管芯附接膜包括：
蚀刻所述管芯附接膜以在所述密封材料中形成凹槽；
在所述电压调节器管芯中从金属焊盘形成所述金属柱；
在所述凹槽内填充所述介电材料；以及
实施额外的平坦化以去除所述介电材料的多余部分，直到暴露所述金属柱。
8.一种形成封装件的方法，包括：
在载体上方形成基底层；
在所述基底层上方形成导电柱；
将电压调节器管芯粘附至所述基底层，其中，所述电压调节器管芯包括管芯附接膜，并且所述管芯附接膜粘附至所述基底层；
将所述电压调节器管芯和所述导电柱密封在密封材料中；
平坦化所述密封材料，直到暴露出所述电压调节器管芯和所述导电柱；
在所述电压调节器管芯和所述密封材料上方形成第一介电层；
在所述第一介电层中形成第一再分布线，其中，所述第一再分布线的部分电连接至所述导电柱；
用介电材料替代所述管芯附接膜；
形成第二介电层，其中，所述第一介电层和所述第二介电层位于所述电压调节器管芯的相对两侧上；
在所述第二介电层中形成第二再分布线；以及
将额外的器件管芯接合至所述第二再分布线。
9.根据权利要求8所述的方法，其中，当平坦化所述密封材料时，去除所述电压调节器管芯的背部以暴露所述电压调节器管芯的半导体衬底中的通孔，并且其中，所述通孔将所述第一再分布线电连接至所述第二再分布线。
10.一种封装件，包括：
电压调节器管芯，包括：
半导体衬底；
通孔，穿透所述半导体衬底；以及
金属柱，位于所述电压调节器管芯的顶面处；
第一密封材料，将所述电压调节器管芯密封在所述密封材料中；
多个第一再分布线，位于所述电压调节器管芯和所述第一密封材料上方，其中，多个所述第一再分布线的部分与所述通孔和所述金属柱物理接触；
器件管芯，接合至所述多个第一再分布线；以及
多个第二再分布线，位于所述第一密封材料的下面，其中，所述多个第二再分布线电连接至所述多个第一再分布线。
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