CN104752367B - 晶圆级封装结构及其形成方法 - Google Patents

晶圆级封装结构及其形成方法 Download PDF

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Publication number
CN104752367B
CN104752367B CN201410848007.9A CN201410848007A CN104752367B CN 104752367 B CN104752367 B CN 104752367B CN 201410848007 A CN201410848007 A CN 201410848007A CN 104752367 B CN104752367 B CN 104752367B
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Prior art keywords
interconnection structure
die
electrical connector
hole
tube core
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CN104752367A (zh
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余振华
余国宠
李明机
李建勋
吴俊毅
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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Abstract

本发明的一个实施例是一种封装件，该封装件包括第一封装组件。第一封装组件包括附接至第一互连结构的第一侧的第一管芯；围绕第一管芯的模制材料；以及位于模制材料和第一管芯上方的第二互连结构，第二互连结构的第一侧通过第一电连接件连接至第一管芯。第一封装组件还包括延伸穿过模制材料的多个模制通孔(TMV)，多个TMV将第一互连结构连接至第二互连结构；以及通过第二电连接件附接至第二互连结构的第二侧的第二管芯，第二互连结构的第二侧与第二互连结构的第一侧相对。本发明还涉及晶圆级封装结构及其形成方法。

Description

晶圆级封装结构及其形成方法
技术领域
本发明涉及集成电路器件，更具体地，涉及晶圆级封装结构及其形成方法。
背景技术
半导体器件用于各种电子应用中，诸如个人计算机、手机、数码相机和其他电子设备。通常通过在半导体衬底上方依次地沉积绝缘或介电层、导电层和半导体材料层以及使用光刻来图案化各个材料层以在各个材料层上形成电路组件和元件。
通过不断减小最小部件尺寸，半导体工业不断地提高各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成度，这允许更多的组件集成到给定区域内。在一些情况下，这些较小的电子组件也需要比先前的封装件利用更小的面积的较小的封装件。
由于叠层封装(PoP)技术具有允许集成电路较密集地集成到较小整体封装件的能力，叠层封装(PoP)技术正变得越来越流行。在诸如智能手机的许多先进的手持设备中采用PoP技术。虽然PoP技术已经允许较小的封装件轮廓，但是总厚度的减小当前受到焊料球接合点高度以及邻近的接合点之间的距离(称为间距)的限制。有时使用诸如球栅阵列、连接盘栅格阵列、引脚阵列等的导电安装结构将管芯安装至中介板衬底或其他封装载体。
发明内容
为了解决现有技术中存在的问题，本发明提供了一种方法，包括：将第一管芯的背侧表面附接至第一互连结构的第一侧；在所述第一互连结构的第一侧上方形成第一通孔，所述第一通孔连接至所述第一互连结构；在所述第一管芯的有源表面上形成第一电连接件，所述有源表面与所述背侧表面相对；用模制材料包封所述第一管芯和所述第一通孔；在所述模制材料、所述第一电连接件和所述第一通孔上方形成第二互连结构，所述第一电连接件和所述第一通孔连接至所述第二互连结构的第一侧；以及使用第二电连接件将第二管芯附接至所述第二互连结构的第二侧，所述第二互连结构的第二侧与所述第二互连结构的第一侧相对。
在上述方法中，其中，所述第一管芯是逻辑管芯，并且其中，所述第二管芯是宽输入/输出(I/O)管芯。
在上述方法中，其中，在所述第一互连结构的第一侧上方形成所述第一通孔包括：将导电引线的第一端接合至所述第一互连结构的第一侧；以及将所述导电引线切割为第一长度以形成所述第一通孔，切割的所述导电引线具有与所述第一端相对的第二端，所述第二端连接至所述第二互连结构的第一侧。
在上述方法中，其中，在所述第一互连结构的第一侧上方形成所述第一通孔包括：将导电引线的第一端接合至所述第一互连结构的第一侧；以及将所述导电引线切割为第一长度以形成所述第一通孔，切割的所述导电引线具有与所述第一端相对的第二端，所述第二端连接至所述第二互连结构的第一侧，其中，所述导电引线包括选自基本由铜、铝、镍、金、银、钯或它们的组合组成的组中的导电材料。
在上述方法中，其中，所述方法还包括：在用所述模制材料包封所述第一管芯和所述第一通孔之前，在所述第一电连接件和所述第一管芯的所述有源表面上方形成离型膜；以及在用所述模制材料包封所述第一管芯和所述第一通孔之后，去除所述离型膜以暴露所述第一电连接件和所述第一管芯的所述有源表面。
在上述方法中，其中，所述方法还包括：使用第三电连接件将封装件附接至所述第二互连结构的第二侧。
在上述方法中，其中，所述方法还包括：使用第三电连接件将封装件附接至所述第二互连结构的第二侧，其中，所述封装件包括一个或多个存储管芯的堆叠件，所述存储管芯通过所述第三电连接件和所述第二互连结构连接至所述第二管芯。
在上述方法中，其中，所述方法还包括：使用第三电连接件将封装件附接至所述第二互连结构的第二侧，其中，所述封装件包括一个或多个存储管芯的堆叠件，所述存储管芯通过所述第三电连接件和所述第二互连结构连接至所述第二管芯，其中，所述存储管芯包括低功耗双倍数据速率存储模块。
在上述方法中，其中，所述方法还包括：在所述第一互连结构的第二侧上形成第四电连接件，所述第一互连结构的第二侧与所述第一互连结构的第一侧相对。
根据本发明的另一方面，提供了一种方法，包括：形成第一封装件，形成所述第一封装件包括：将第一管芯附接至第一互连结构；在所述第一管芯的有源表面上形成第一组电连接件；形成邻近所述第一管芯的多个通孔，所述多个通孔中的每个均具有邻接所述第一互连结构的第一端和在远离所述第一互连结构的方向上延伸的第二端；用模制材料包封所述第一管芯和所述多个通孔；平坦化所述模制材料以暴露所述第一组电连接件的顶面和所述多个通孔的第二端；在所述模制材料、所述第一组电连接件和所述多个通孔上方形成第二互连结构，所述第二互连结构连接至所述第一组电连接件和所述多个通孔；以及使用第二组电连接件将第二管芯附接至所述第二互连结构。
在上述方法中，其中，所述方法还包括：使用第三组电连接件将第二封装件附接至所述第一封装件。
在上述方法中，其中，所述方法还包括：使用第三组电连接件将第二封装件附接至所述第一封装件，其中，所述第一管芯是逻辑管芯，所述第二管芯是宽输入/输出(I/O)管芯，并且其中，所述第二封装件包括多于一个的存储管芯，所述多于一个的存储管芯连接至所述第二管芯。
在上述方法中，其中，形成邻近所述第一管芯的所述多个通孔包括实施引线接合。
在上述方法中，其中，形成邻近所述第一管芯的所述多个通孔包括电镀。
根据本发明的又一方面，提供了一种封装件，包括：第一封装组件，包括：第一管芯，附接至第一互连结构的第一侧；模制材料，围绕所述第一管芯；第二互连结构，位于所述模制材料和所述第一管芯上方，所述第二互连结构的第一侧通过第一电连接件连接至所述第一管芯；多个模制通孔(TMV)，延伸穿过所述模制材料，所述多个TMV将所述第一互连结构连接至所述第二互连结构；以及第二管芯，通过第二电连接件附接至所述第二互连结构的第二侧，所述第二互连结构的第二侧与所述第二互连结构的第一侧相对。
在上述封装件中，其中，所述多个模制通孔中的每个均包括导电引线，所述导电引线具有连接至所述第一互连结构的第一端和连接至所述第二互连结构的第二端。
在上述封装件中，其中，所述多个模制通孔中的每个均包括导电引线，所述导电引线具有连接至所述第一互连结构的第一端和连接至所述第二互连结构的第二端，其中，所述导电引线包括选自基本由铜、铝、镍、金、银、钯或它们的组合组成的组中的导电材料。
在上述封装件中，其中，所述封装件还包括：第二封装组件，附接至所述第一封装组件，所述第二封装组件包括：一个或多个堆叠管芯，连接至衬底；以及第三电连接件，将所述衬底附接至所述第二互连结构的第二侧。
在上述封装件中，其中，所述封装件还包括：第二封装组件，附接至所述第一封装组件，所述第二封装组件包括：一个或多个堆叠管芯，连接至衬底；以及第三电连接件，将所述衬底附接至所述第二互连结构的第二侧，其中，所述第一管芯是逻辑管芯，所述第二管芯是宽输入/输出(I/O)管芯，并且其中，所述一个或多个堆叠管芯是一个或多个堆叠存储管芯。
在上述封装件中，其中，所述模制材料的顶面与所述第一电连接件的顶面以及所述多个TMV的顶面基本共面。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1A至图1J示出了根据一些实施例的在形成晶圆级封装件(WLP)中的中间步骤的截面图。
图2A至图2G示出了根据一些实施例的在形成WLP中的中间步骤的截面图。
图3是根据一些实施例的示出形成WLP的方法的流程图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语，以便于描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而在此使用的空间相对描述符可以同样地作相应的解释。
将结合具体上下文描述实施例，即制造和使用晶圆级封装(WLP)组件。然而，其他实施例也可以应用于其他电连接的组件，包括但不限于叠层封装组件、管芯至管芯组件、晶圆至晶圆组件、管芯至衬底组件、组装封装中的组件、处理衬底中的组件、中介板、衬底等，或安装输入组件、板件、管芯或其他组件，或用于任何类型的集成电路或电子组件的连接封装或安装组合。
图1A至图1J示出了在形成WLP组件中的示例工艺中的截面图，并且图3示出了该示例工艺的流程图。
图1A示出了在载体衬底102上方形成互连结构104(步骤602)。载体衬底102可以在后续处理步骤期间提供临时的机械和结构支撑。在载体衬底102的表面上方形成互连结构104，互连结构104包括一个或多个介电层和相应的金属化图案。介电层中的金属化图案可以诸如通过使用通孔和/或迹线在器件之间路由电信号，并且也可以包含诸如电容器、电阻器、电感器等的各种电器件。金属化图案有时称为再分布线(RDL)。可以互连各种器件和金属化图案以执行一个或多个功能。该功能可以包括存储结构、处理结构、传感器、放大器、功率分布、输入/输出电路等。此外，在互连结构104中和/或上形成接合焊盘以提供至电路和/或器件的外部电连接。本领域普通技术人员将理解，以上实例提供用于说明的目的。其他电路可以适当地用于给定应用。
更具体地，可以在互连结构104中形成一个或多个金属间介电(IMD)层。例如，IMD层可以通过诸如旋压、化学汽相沉积(CVD)、等离子体增强CVD(PECVD)、高密度等离子体化学汽相沉积(HDP-CVD)等的本领域已知的任何合适的方法由诸如磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟硅酸盐玻璃(FSG)、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、它们的化合物、它们的复合物、它们的组合等的低K介电材料形成。例如，可以通过使用光刻技术以在IMD层上沉积并图案化光刻胶材料以暴露将成为金属化图案的IMD层的部分而在IMD层中形成金属化图案。诸如各向异性干蚀刻工艺的蚀刻工艺可以用于在IMD层中产生与IMD层的暴露部分相应的凹槽和/或开口。在一些实施例中，通过激光图案化形成开口或凹槽。凹槽和/或开口可以内衬有扩散阻挡层并且填充有导电材料。扩散阻挡层可以包括通过原子层沉积(ALD)等沉积的TaN、Ta、TiN、Ti、CoW等的一个或多个层，并且导电材料可以由通过CVD、物理汽相沉积(PVD)等沉积的铜、铝、钨、银和它们的组合等制成。可以通过诸如使用化学机械抛光(CMP)去除IMD层上的任何过量的扩散阻挡层和/或导电材料。
图1B示出了在互连结构104的第一侧上方形成电连接件108(步骤604)。电连接件108可以是柱凸块，该柱凸块通过在互连结构104的接合焊盘上接合引线并且切割接合引线，使得留下附接至相应的接合球的接合引线的部分来形成。例如，在图1B中，电连接件108包括下部和上部，其中，下部可以是形成在接合引线中的接合球，并且上部可以是剩余的接合引线。电连接件108的上部可以具有均匀贯穿上部的顶部、中间部分和底部的均匀的宽度和均匀的形状。电连接件108由可以通过引线接合件接合的非焊料金属材料形成。在一些实施例中，电连接件108由铜引线、金引线等或它们的组合制成并且可以具有包括多个层的复合结构。
在可选实施例中，通过电镀形成电连接件108。在这些实施例中，电连接件108由铜、铝、镍、金、银、钯等或它们的组合制成，并且可以具有包括多个层的复合结构。在这些实施例中，在互连结构104上方形成牺牲层(未示出)。在牺牲层中形成多个开口以暴露下面的互连结构104中的接合焊盘。然后实施镀步骤以镀电连接件108。在形成电连接件108之后，然后去除牺牲层。
图1C示出了在互连结构104上方附接第一管芯110(步骤606)，其中第一管芯110的背侧表面邻接互连结构104。第一管芯110可以是诸如中央处理单元(CPU)、图形处理单元(GPU)等或它们的组合的逻辑管芯。在一些实施例中，第一管芯110包括可以包含逻辑管芯和存储管芯的管芯堆叠件(未示出)。
在第一管芯110的有源表面上形成电连接件112，该有源表面与背侧表面相对。电连接件112允许第一管芯110连接至随后形成的互连结构116(见图1F)。在一些实施例中，电连接件112是诸如可控塌陷芯片连接(C4)的焊料球和/或凸块。在其他实施例中，电连接件112是金属柱，其中，在金属柱的顶面上形成焊帽。在又其他实施例中，电连接件112是包括铜柱、镍层、焊帽、化学镀镍浸金(ENIG)、化学镀镍钯浸金(ENEPIG)等的复合凸块。
图1D示出了包封第一管芯110以及电连接件108和112(步骤608)。在一些实施例中，由模制材料114包封第一管芯110以及电连接件108和112。例如，可以使用压缩模制在第一管芯110以及电连接件108和112上模制模制材料114。在一些实施例中，模制材料114由模塑料、聚合物、环氧化物、氧化硅填充材料等或它们的组合制成。可以实施固化步骤以固化模制材料114，其中，固化可以是热固化、紫外(UV)固化等。
如图1E所示，在一些实施例中，第一管芯110以及电连接件108和112掩埋在模制材料114中，并且在固化模制材料114之后，实施诸如研磨的平坦化步骤以去除模制材料114的过量部分，其中过量部分位于电连接件108和112的顶面上方。在一些实施例中，电连接件112的顶面112A和电连接件108的顶面108A暴露并且与模制材料114的顶面114A齐平。电连接件108可以称为模制通孔(TMV)并且将在下文中称为TMV 108。
图1F示出了在第一管芯110、TMV 108和电连接件112上方形成互连结构116(步骤610)，并且在互连结构116上方形成电连接件118。在模制材料114的顶面114A上方形成互连结构116，互连结构116包括一个或多个介电层和相应的金属化图案，并且互连结构的第一侧直接连接至电连接件112和TMV 108。
介电层中的金属化图案可以通过诸如使用通孔和/或迹线在电连接件112和TMV108之间路由电信号，并且也可以包含诸如电容器、电阻器、电感器等的各种电器件。金属化图案也可以称为RDL。可以互连各种器件和金属化图案以执行一种或多种功能。该功能可以包括存储结构、处理结构、传感器、放大器、功率分布、输入/输出电路等。此外，在互连结构116中和/或上形成接合焊盘以提供至电路和/或器件的外部电连接。本领域普通技术人员将理解，以上实例提供用于说明的目的。其他电路可以适当地用于给定应用。
更具体地，可以在互连结构116中形成一个或多个IMD层。例如，IMD层可以通过诸如旋压、CVD、PECVD、HDP-CVD等的本领域已知的任何合适的方法由诸如PSG、BPSG、FSG、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、它们的化合物、它们的复合物、它们的组合等的低K介电材料形成。例如，可以通过使用光刻技术以在IMD层上沉积并图案化光刻胶材料以暴露将成为金属化图案的IMD层的部分而在IMD层中形成金属化图案。诸如各向异性干蚀刻工艺的蚀刻工艺可以用于在IMD层中产生与IMD层的暴露部分相应的凹槽和/或开口。在一些实施例中，通过激光图案化形成开口或凹槽。凹槽和/或开口可以内衬有扩散阻挡层并且填充有导电材料。扩散阻挡层可以包括通过ALD等沉积的TaN、Ta、TiN、Ti、CoW等的一个或多个层，并且导电材料可以由通过CVD、物理汽相沉积(PVD)等沉积的铜、铝、钨、银和它们的组合等制成。可以通过诸如使用CMP去除IMD层上的任何过量的扩散阻挡层和/或导电材料。
在互连结构116的第二侧上方形成电连接件118，并且电连接件118连接至互连结构116的第二侧，互连结构116的第二侧与互连结构116的第一侧相对。电连接件118允许第二管芯120(见图1G)附接并且连接至互连结构116。在一些实施例中，电连接件118是微凸块、C4凸块、焊料球等。在其他实施例中，电连接件118是金属柱，其中，在金属柱的顶面上形成焊帽。在又其他实施例中，电连接件118是包括铜柱、镍层、焊帽、化学镀镍浸金(ENIG)、化学镀镍钯浸金(ENEPIG)等的复合凸块。
图1G示出了使用电连接件118将第二管芯120附接在互连结构116上方(步骤612)。第二管芯120可以是提供第一管芯110和随后附接的第二封装件200(见图1J)之间的连接的宽输入/输出(I/O)管芯。在一些实施例中，第一管芯110和第二管芯120不包含任何通孔。在实施例中，第二管芯是管芯堆叠件并且可以包括宽I/O管芯和一个或多个存储管芯。
图1H示出了从互连结构104的第二侧去除载体衬底102，互连结构104的第二侧与互连结构104的第一侧相对。互连结构104和116、TMV 108、第一管芯110和第二管芯120形成第一封装件100。在实施例中，第一封装件100包括逻辑管芯110和宽I/O管芯120，并且可以进一步附接至第二封装件(见图1J)，第二封装件包括一个或多个存储管芯。宽I/O管芯120允许逻辑管芯110在逻辑管芯110和宽I/O管芯120之间的布线最小的情况下访问第二封装件中的存储管芯，这可以提高半导体器件的速度并且降低半导体器件的功率需求。
图1I示出了在互连结构104的第二侧上形成电连接件126，电连接件126电连接至互连结构104。在一些实施例中，电连接件126是焊料球。在其他实施例中，电连接件126可以包括金属焊盘、金属凸块、焊帽等。电连接件126可以用于将第一封装件100接合至额外的电子组件，该额外的电子组件可以是半导体衬底、印刷电路板(PCB)等。
如图1I所示，TMV 108具有间距P1，电连接件118具有间距P2，并且电连接件126具有间距P3。在一些实施例中，间距P1为从约100μm至约500μm，间距P2为从约30μm至约100μm，并且间距P3为从约250μm至约500μm。第二管芯120可以具有厚度T1，第一管芯110可以具有厚度T2，并且电连接件118可以具有从互连结构116的第二侧至第二管芯120的有源表面的相隔高度H1。在一些实施例中，厚度T1为从约40μm至约300μm，厚度T2为从约40μm至约300μm，并且高度H1为从约30μm至约100μm。
图1J示出了使用电连接件204将第二封装件200附接至第一封装件100的互连结构116的第二侧，以形成半导体器件300。第二封装件200包括衬底202和连接至衬底202的一个或多个堆叠管芯206。
衬底202可以具有位于衬底202的第一侧上的接合区域203以连接至电连接件204。此外，衬底202可以具有位于衬底202的第二侧上的接合区域(未示出)以连接至堆叠管芯206，衬底202的第二侧与第一侧相对。在实施例中，衬底202是硅衬底、硅或玻璃中介板、PCB、有机层压衬底等。在一些实施例中，衬底202可以包括形成在其上的电子组件和元件，或者可选地，衬底202可以不包括电子组件和元件。
在示出的实施例中，堆叠管芯206通过引线接合件208连接至衬底202，但是可以使用诸如接触凸块的其他连接件。在实施例中，堆叠管芯206是堆叠存储管芯206。例如，堆叠存储管芯206可以包括诸如LPDDR1、LPDDR2、LPDDR3等存储模块的低功耗(LP)双倍数据速率(DDR)存储模块。堆叠存储管芯206可以通过电连接件204和引线接合件208连接至第一封装件100。
在一些实施例中，可以由模制材料210包封堆叠管芯206和引线接合件208。例如，可以使用压缩模制在堆叠管芯206和引线接合件208上模制模制材料210。在一些实施例中，模制材料210是模塑料、聚合物、环氧化物等或它们的组合。可以实施固化步骤以固化模制材料210，其中，固化可以是热固化、UV固化等。
在一些实施例中，堆叠管芯206和引线接合件208掩埋在模制材料210中，并且在固化模制材料210之后，实施诸如研磨的平坦化步骤以去除模制材料210的过量部分并且为第二封装件200提供基本平坦的表面。
可以通过在互连结构116的第二侧和/或衬底202的接合区域203上形成焊料球来形成电连接件204。可以使第一封装件100和第二封装件200拼拢在一起，直到衬底202和互连结构116通过焊料球连接，并且回流焊料球以形成电连接件204。电连接件204可以称为焊料接合件204。在一些实施例中，电连接件在截面图中具有基本为桶形的形状。
图2A至图2G示出了在形成WLP组件中的另一示例工艺中的截面图。本文中不重复关于该实施例的与先前描述的实施例的那些类似的细节。
图2A示出了载体衬底102，其中，互连结构104和电连接件108位于载体衬底102上方。图2A中的中间结构类似于图1B中的上述结构并且本文中不重复该描述。
图2B示出了将第一管芯110附接在互连结构104上方，其中第一管芯110的背侧表面邻接互连结构104。该步骤类似于图1C中的上述步骤，除了以下之外，图2B中的第一管芯110包括位于第一管芯110的有源表面上方的UBM 111和位于UBM 111和第一管芯110的有源表面上方的离型膜113，而不包括位于第一管芯110上方的电连接件112。
UBM 111可以包括一个或多个导电材料层。存在适合于形成UBM 111的许多材料和层的布置，诸如铬/铬-铜合金/铜/金的布置、钛/钛钨/铜的布置或铜/镍/金的布置。可以形成和图案化光刻胶(未示出)，从而使得暴露第一管芯110的有源表面的一些部分，而覆盖一些其他部分。可以实施镀工艺以在第一管芯110的有源表面的暴露部分上镀材料和层，从而形成UBM 111。可以用于UBM 111的任何合适的材料或材料层完全旨在包括在本申请的范围内。在镀工艺之后，可以去除光刻胶。在一些实施例中，UBM 111可以是接触焊盘111。
在形成UBM 111之后，在UBM 111和第一管芯110的有源表面上方施加离型膜113以防止随后形成的模制材料114粘附至UBM 111和第一管芯110的有源表面。在实施例中，离型膜113由乙烯-四氟乙烯共聚物(ETFE)、聚四氟乙烯(PTFE)等或它们的组合制成。
图2C示出了用模制材料114包封第一管芯110、离型膜113和TMV 108。例如，可以使用压缩模制在第一管芯110、离型膜113和TMV 108上模制模制材料114。在一些实施例中，模制材料114是模塑料、聚合物、环氧化物等或它们的组合。可以实施固化步骤以固化模制材料114，其中，固化可以是热固化、UV固化等。
如图2D所示，在一些实施例中，第一管芯110、离型膜113和TMV 108掩埋在模制材料114中，并且在固化模制材料114之后，实施诸如研磨的平坦化步骤以去除模制材料114的过量部分，其中过量部分位于离型膜113和TMV 108的顶面上方。在一些实施例中，离型膜113的顶面113A和TMV 108的顶面108A暴露并且与模制材料114的顶面114A齐平。
图2E示出了去除离型膜113以暴露UBM 111和第一管芯110的有源表面。图2F示出了在UBM 111上方形成电连接件115，并且电连接件115连接至UBM 111；在电连接件115和TMV 108上方形成互连结构116，并且互连结构116连接至电连接件115和TMV 108；以及在互连结构116上方形成电连接件118。在实施例中，电连接件115是焊料球和/或凸块，诸如C4凸块。在其他实施例中，电连接件115是金属柱，其中，在金属柱的顶面上形成焊帽。在又其他实施例中，电连接件115是包括铜柱、镍层、焊帽、ENIG、ENEPIG等的复合凸块。互连结构116和电连接件118类似于图1F中的上述互连结构116和电连接件118，并且本文中不重复描述。
图2G示出了在若干处理步骤之后的包括第一封装件100和第二封装件200的半导体器件500。半导体器件500类似于图1J中的上述半导体器件300，除了半导体器件500中的电连接件115代替半导体器件300中的电连接件112之外，并且本文中不重复半导体器件500中的其他组件的描述。
通过使TMV 108与互连结构104和116的扇出结构互连第一管芯110和第二管芯120，第一管芯110和第二管芯120能够不包括任何通孔。这允许半导体器件300是更有成本效益的并且具有简化的处理。此外，由于逻辑管芯和宽I/O管芯均在第一封装件100中，所以可以在几乎不改变第一封装件100的情况下使用第二封装件200的许多变化(例如，存储器的各种类型和容量)。此外，由于用最小布线互连宽I/O管芯120和逻辑管芯110，所以可以提高半导体器件的速度，同时也减小半导体器件的功率需求和整体厚度。
一个实施例是一种方法，该方法包括：将第一管芯的背侧表面附接至第一互连结构的第一侧，在第一互连结构的第一侧上方形成第一通孔，第一通孔连接至第一互连结构，以及在第一管芯的有源表面上形成第一电连接件，有源表面与背侧表面相对。该方法还包括：用模制材料包封第一管芯和第一通孔，在模制材料、第一电连接件和第一通孔上方形成第二互连结构，第一电连接件和第一通孔连接至第二互连结构的第一侧，以及使用第二电连接件将第二管芯附接至第二互连结构的第二侧，第二互连结构的第二侧与第二互连结构的第一侧相对。
另一实施例是一种方法，该方法包括形成第一封装件。形成第一封装件包括：将第一管芯附接至第一互连结构，在第一管芯的有源表面上形成第一组电连接件，形成邻近第一管芯的多个通孔，多个通孔中的每个均具有邻接第一互连结构的第一端和在远离第一互连结构的方向上延伸的第二端，以及用模制材料包封第一管芯和多个通孔。该方法还包括：平坦化模制材料以暴露第一组电连接件的顶面和多个通孔的第二端，在模制材料、第一组电连接件和多个通孔上方形成第二互连结构，第二互连结构连接至第一组电连接件和多个通孔，以及使用第二组电连接件将第二管芯附接至第二互连结构。
又一实施例是一种封装件，该封装件包括第一封装组件。第一封装组件包括附接至第一互连结构的第一侧的第一管芯；围绕第一管芯的模制材料；以及位于模制材料和第一管芯上方的第二互连结构，第二互连结构的第一侧通过第一电连接件连接至第一管芯。第一封装组件还包括延伸穿过模制材料的多个模制通孔(TMV)，多个TMV将第一互连结构连接至第二互连结构；以及通过第二电连接件附接至第二互连结构的第二侧的第二管芯，第二互连结构的第二侧与第二互连结构的第一侧相对。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (19)

1.一种形成封装件的方法，包括：
将第一管芯的背侧表面附接至第一互连结构的第一侧；
在所述第一互连结构的第一侧上方形成第一通孔，所述第一通孔连接至所述第一互连结构；
在所述第一管芯的有源表面上形成第一电连接件，所述有源表面与所述背侧表面相对；
用模制材料包封所述第一管芯和所述第一通孔；
在所述模制材料、所述第一电连接件和所述第一通孔上方形成第二互连结构，所述第一电连接件和所述第一通孔连接至所述第二互连结构的第一侧；
使用第二电连接件将第二管芯附接至所述第二互连结构的第二侧，所述第二互连结构的第二侧与所述第二互连结构的第一侧相对；
在用所述模制材料包封所述第一管芯和所述第一通孔之前，在所述第一电连接件和所述第一管芯的所述有源表面上方形成离型膜；以及在用所述模制材料包封所述第一管芯和所述第一通孔之后，去除所述离型膜以暴露所述第一电连接件和所述第一管芯的所述有源表面。
2.根据权利要求1所述的方法，其中，所述第一管芯是逻辑管芯，并且其中，所述第二管芯是宽输入/输出(I/O)管芯。
3.根据权利要求1所述的方法，其中，在所述第一互连结构的第一侧上方形成所述第一通孔包括：
将导电引线的第一端接合至所述第一互连结构的第一侧；以及
将所述导电引线切割为第一长度以形成所述第一通孔，切割的所述导电引线具有与所述第一端相对的第二端，所述第二端连接至所述第二互连结构的第一侧。
4.根据权利要求3所述的方法，其中，所述导电引线包括选自由铜、铝、镍、金、银、钯或它们的组合组成的组中的导电材料。
5.根据权利要求1所述的方法，还包括：
使用第三电连接件将封装件附接至所述第二互连结构的第二侧。
6.根据权利要求5所述的方法，其中，所述封装件包括一个或多个存储管芯的堆叠件，所述存储管芯通过所述第三电连接件和所述第二互连结构连接至所述第二管芯。
7.根据权利要求6所述的方法，其中，所述存储管芯包括低功耗双倍数据速率存储模块。
8.根据权利要求1所述的方法，还包括：
在所述第一互连结构的第二侧上形成第四电连接件，所述第一互连结构的第二侧与所述第一互连结构的第一侧相对。
9.一种形成封装件的方法，包括：
形成第一封装件，形成所述第一封装件包括：
将第一管芯附接至第一互连结构；
在所述第一管芯的有源表面上形成第一组电连接件；
形成邻近所述第一管芯的多个通孔，所述多个通孔中的每个均具有邻接所述第一互连结构的第一端和在远离所述第一互连结构的方向上延伸的第二端；
用模制材料包封所述第一管芯和所述多个通孔；
平坦化所述模制材料以暴露所述第一组电连接件的顶面和所述多个通孔的第二端；
在所述模制材料、所述第一组电连接件和所述多个通孔上方形成第二互连结构，所述第二互连结构连接至所述第一组电连接件和所述多个通孔；以及
使用第二组电连接件将第二管芯附接至所述第二互连结构；
在用所述模制材料包封所述第一管芯和所述多个通孔之前，在所述第一组电连接件和所述第一管芯的所述有源表面上方形成离型膜；以及
在用所述模制材料包封所述第一管芯和所述多个通孔之后，去除所述离型膜以暴露所述第一组电连接件和所述第一管芯的所述有源表面。
10.根据权利要求9所述的方法，还包括：
使用第三组电连接件将第二封装件附接至所述第一封装件。
11.根据权利要求10所述的方法，其中，所述第一管芯是逻辑管芯，所述第二管芯是宽输入/输出(I/O)管芯，并且其中，所述第二封装件包括多于一个的存储管芯，所述多于一个的存储管芯连接至所述第二管芯。
12.根据权利要求9所述的方法，其中，形成邻近所述第一管芯的所述多个通孔包括实施引线接合。
13.根据权利要求9所述的方法，其中，形成邻近所述第一管芯的所述多个通孔包括电镀。
14.一种封装件，包括：
第一封装组件，包括：
第一管芯，附接至第一互连结构的第一侧；
模制材料，围绕所述第一管芯；
第二互连结构，位于所述模制材料和所述第一管芯上方，所述第二互连结构的第一侧通过第一电连接件连接至所述第一管芯；
多个模制通孔(TMV)，延伸穿过所述模制材料，所述多个模制通孔将所述第一互连结构连接至所述第二互连结构；以及
第二管芯，通过第二电连接件附接至所述第二互连结构的第二侧，所述第二互连结构的第二侧与所述第二互连结构的第一侧相对；
第二封装组件，附接至所述第一封装组件；
其中，所述第一管芯是逻辑管芯，所述第二管芯是宽输入/输出(I/O)管芯，所述逻辑管芯和所述宽输入/输出管芯位于与所述第二封装组件不同的所述第一封装组件中。
15.根据权利要求14所述的封装件，其中，所述多个模制通孔中的每个均包括导电引线，所述导电引线具有连接至所述第一互连结构的第一端和连接至所述第二互连结构的第二端。
16.根据权利要求15所述的封装件，其中，所述导电引线包括选自由铜、铝、镍、金、银、钯或它们的组合组成的组中的导电材料。
17.根据权利要求14所述的封装件，所述第二封装组件包括：
一个或多个堆叠管芯，连接至衬底；以及
第三电连接件，将所述衬底附接至所述第二互连结构的第二侧。
18.根据权利要求17所述的封装件，其中，所述一个或多个堆叠管芯是一个或多个堆叠存储管芯。
19.根据权利要求14所述的封装件，其中，所述模制材料的顶面与所述第一电连接件的顶面以及所述多个模制通孔的顶面共面。
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