CN107833864A - 封装结构及其形成方法 - Google Patents
封装结构及其形成方法 Download PDFInfo
- Publication number
- CN107833864A CN107833864A CN201710617523.4A CN201710617523A CN107833864A CN 107833864 A CN107833864 A CN 107833864A CN 201710617523 A CN201710617523 A CN 201710617523A CN 107833864 A CN107833864 A CN 107833864A
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- Prior art keywords
- packaging
- packaging part
- die
- bottom filler
- conducting connecting
- Prior art date
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- Granted
Links
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Classifications
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- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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Abstract
实施例是一种结构,该结构包括:第一封装件,第一封装件包括第一管芯和至少横向包封第一管芯的模塑料;通过第一组导电连接件接合至第一封装件的第二封装件,第二封装件包括第二管芯和位于第一封装件和第二封装件之间并且围绕第一组导电连接件的底部填充物,底部填充物具有沿着第二封装件的侧壁向上延伸的第一部分,该第一部分具有第一侧壁,该第一侧壁具有弯曲部分和平坦部分。发明实施例涉及封装结构及其形成方法。
Description
技术领域
发明实施例涉及封装结构及其形成方法。
背景技术
由于许多电子组件(例如,晶体管、二极管、电阻器、电容器等)的集成度的不断提高,半导体工业经历了快速发展。对于大部分而言,最小部件尺寸的连续减小导致了集成密度的改进,这使得更多的组件集成到给定的区域。随着近来对小型化电子器件的需求的增长,也产生了对于半导体管芯的更小且更具创造性的封装技术的需求。这种封装系统的实例是堆叠封装(PoP)技术。在PoP器件中,顶部半导体封装件堆叠在底部半导体封装件110的顶部上以提供高整合度和高元件密度。通常地,PoP技术实现了在印刷电路板(PCB)上生产具有增强功能和较小的覆盖区的半导体器件。
发明内容
根据本发明的一个实施例,提供了一种封装结构,包括:第一封装件,包括:第一管芯;和模塑料,至少横向包封所述第一管芯;第二封装件,通过第一组导电连接件接合至所述第一封装件,所述第二封装件包括第二管芯;以及底部填充物,位于所述第一封装件和所述第二封装件之间并且围绕所述第一组导电连接件,所述底部填充物具有沿着所述第二封装件的侧壁向上延伸的第一部分,所述第一部分具有第一侧壁,所述第一侧壁具有弯曲部分和平坦部分。
根据本发明的另一实施例,还提供了一种形成封装结构的方法,包括:形成多个第一封装件,多个所述第一封装件的每个均包括被模塑料围绕的第一管芯和位于所述第一管芯的第一侧和所述模塑料上的再分布结构,所述再分布结构包括金属化图案;将包括凸块下金属的第一组导电连接件连接至所述再分布结构的第一金属化图案;使用第二组导电连接件将多个第二封装件接合至多个所述第一封装件,所述第二封装件邻近所述第一管芯的第二侧,所述第二侧与所述第一侧相对;以及在位于邻近的所述第二封装件之间的划线区中以及所述第一封装件和所述第二封装件之间以及围绕所述第二组导电连接件分配底部填充物,所述底部填充物沿着多个所述第二封装件的侧壁向上延伸,所述底部填充物在邻近的所述第二封装件之间具有弯曲的凹顶面。
根据本发明的又一实施例,还提供了一种形成封装结构的方法,包括:形成多个第一封装件,形成所述第一封装件的每个均包括:在载体衬底上方形成电连接件;将第一管芯附接至所述载体衬底,所述电连接件从所述第一管芯的第二侧延伸至所述第一管芯的第一侧,所述第二侧与所述第一侧相对;用模塑料包封所述第一管芯和所述电连接件,所述电连接件延伸穿过所述模塑料;在所述第一管芯的所述第一侧和所述模塑料上方形成再分布结构;将第一组导电连接件连接至所述再分布结构;邻近所述第一组导电连接件将无源组件接合至所述再分布结构;以及去除所述载体衬底;使用第二组导电连接件将多个第二封装件接合至多个所述第一封装件,所述第二封装件邻近所述第一管芯的所述第二侧;在所述第一封装件和所述第二封装件之间以及围绕所述第二组导电连接件分配底部填充物,所述底部填充物沿着多个所述第二封装件的侧壁向上延伸,所述底部填充物在邻近的第二封装件之间具有凹顶面;以及分割多个所述第一封装件和多个所述第二封装件以形成封装结构,所述分割在所述凹顶面处切割穿过所述底部填充物以形成底部填充物的侧壁,所述底部填充物的侧壁具有凹部分和平坦部分。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各个方面。应当注意,根据工业中的标准实践,各个部件并非按比例绘制。事实上,为了清楚讨论,各个部件的尺寸可以任意增大或减小。
图1至图28示出了根据一些实施例的在用于形成封装结构的工艺期间的中间步骤的截面图。
具体实施方式
为了实施本发明的不同部件,以下公开提供了许多不同的实施例或实例。在下面描述元件和布置的特定实例以简化本发明。当然这些仅仅是实例并不旨在限定本发明。例如,在以下描述中,在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例,也可以包括在第一部件和第二部件之间形成额外的部件使得第一部件和第二部件可以不直接接触的实施例。而且,本发明在各个实例中可重复参考数字和/或字母。这种重复仅是为了简明和清楚,其自身并不表示所论述的各个实施例和/或配置之间的关系。
此外,为便于描述,在此可以使用诸如“在...之下”、“在...下方”、“下部”、“在...之上”、“上部”等的空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。空间相对术语旨在包括除了附图中所示的方位之外,在使用中或操作中的器件的不同方位。装置可以以其他方式定位(旋转90度或在其他方位),并且通过在本文中使用的空间关系描述符可同样地作相应地解释。
可以在具体上下文中讨论本文中讨论的实施例,即封装结构,该封装结构包括全覆盖底部填充工艺,全覆盖底部填充工艺提高封装件侧壁的保护,提高封装件侧壁的保护提高了封装结构的稳定性和产量。所公开的全覆盖底部填充工艺也已经提高了底部填充物流速并且能够简化封装件的分割工艺。可以在比其他底部填充工艺更高的压力下固化底部填充物。在固化工艺期间,压力的增加可以加速填充物中的空隙的移动,这将增加用于封装件的工艺的产量。该封装结构可以包括扇出或扇入封装件并且可以包括一个或多个再分布层(RDL)。
此外,本发明的技术可应用于包括底部填充工艺的任何封装结构。其他实施例预期其他应用,诸如不同的封装类型或不同的配置对阅读本发明的本领域普通技术人员而言将是显而易见的。应该注意,本文讨论的实施例不必示出可能存在于结构中的每一个元件或部件。例如,可从附图中省略多个部件,诸如当讨论一个元件可能足以表达实施例的各个方面时。此外,可将本文讨论的方法实施例讨论为按特殊顺序实施;然而,可按任何逻辑顺序实施其他方法实施例。
图1至图28示出了根据一些实施例的在用于形成封装结构的工艺期间的中间步骤的截面图。图1示出了载体衬底100和形成在载体衬底100上的释放层102。分别示出用于形成第一封装件和第二封装件的第一封装件区域600和第二封装件区域602。
载体衬底100可以是玻璃载体衬底、陶瓷载体衬底等。载体衬底100可以是晶圆,从而使得多个封装件可以同时形成在载体衬底100上。释放层102可以由聚合物基材料形成,释放层可以与载体衬底100一起从在随后步骤中将要形成的上面的结构中去除。在一些实施例中,释放层102是诸如光热转换(LTHC)释放涂层的环氧树脂基热释放材料,该材料在被加热时失去其粘性。在其他实施例中,释放层102可为紫外光(UV)胶,其在暴露于UV光时丧失它的粘合性能。释放层102可以以液体形式进行分配并且被固化,释放层102可以是层压在载体衬底100上的层压膜等。释放层102的顶面可以是齐平的并且可具有高度的共面性。
在图2中,形成介电层104和金属化图案106。如图2所示,在释放层102上形成介电层104。介电层104的底面可以与释放层102的顶面接触。在一些实施例中,介电层104由诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的聚合物形成。在其他的实施例中,介电材料104由以下材料形成:氮化物,诸如氮化硅;氧化物,诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺杂硼的磷硅酸盐玻璃(BPSG)等。介电层104可以通过任何可接受的沉积工艺来形成,诸如旋涂、化学汽相沉积(CVD)、层压等或它们的组合。
在介电层104上形成金属化图案106。作为实例,为了形成金属化图案106,在介电层104上方形成晶种层(未示出)。在一些实施例中,晶种层为金属层,其可为单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和钛层上方的铜层。例如,可以使用PVD等形成晶种层。然后在晶种层上形成并且图案化光刻胶。该光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案106。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中以及在晶种层的暴露的部分上形成导电材料。可通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括金属,如铜、钛、钨、铝等。然后,去除光刻胶以及晶种层的其上未形成导电材料的部分。可通过可接受的灰化或剥离工艺去除光刻胶,诸如使用氧等离子体等。一旦去除光刻胶,就诸如通过使用可接受的蚀刻工艺去除晶种层的暴露的部分,诸如通过湿蚀刻或干蚀刻。晶种层的剩余部分和导电材料形成金属化图案106。
在图3中,介电层108形成在金属化图案106和介电层104上。在一些实施例中,介电层108由聚合物形成,聚合物可以是使用光刻掩模可以图案化的诸如PBO、聚酰亚胺、BCB等的感光材料。在其他实施例中,介电层108由氮化物(诸如氮化硅)、氧化物(诸如氧化硅、PSG、BSG、BPSG)等形成。可通过旋转涂布、层压、CVD等或其组合形成介电层108。然后,图案化介电层108以形成开口来暴露金属化图案106的一部分。当介电层为感光材料时,诸如通过将介电层108暴露于光的可接受的工艺实施图案化,或者例如,通过使用各向异性蚀刻的蚀刻实施图案化。
介电层104和介电层108以及金属化图案106可以称为背侧再分布结构110。如示出的,背侧再分布结构110包括两个介电层104和108以及一个金属化图案106。在其他实施例中,背侧再分布结构110可以包括任意数量的介电层、金属化图案和通孔。通过重复用于形成金属化图案106和介电层108的工艺可以在背侧再分布结构110中形成一个或多个额外的金属化图案和介电层。可以在通过在下面的介电层的开口中形成晶种层和金属化图案的导电材料的期间形成通孔。因此,通孔可以互连和电连接各个金属化图案。
进一步在图3中,形成通孔112。作为形成通孔112的实例,晶种层216形成在背侧再分布层上方,例如,形成在介电层108和金属化图案106的暴露部分上方。在一些实施例中,晶种层为金属层,其可为单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和钛层上方的铜层。例如,可以使用PVD等形成晶种层。将光刻胶形成并图案化在晶种层上。该光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于通孔。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中以及在晶种层的暴露的部分上形成导电材料。可通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括金属,如铜、钛、钨、铝等。去除光刻胶以及晶种层的其上未形成导电材料的部分。可通过可接受的灰化或剥离工艺去除光刻胶,诸如使用氧等离子体等。一旦去除光刻胶,就诸如通过使用可接受的蚀刻工艺去除晶种层的暴露的部分,诸如通过湿或干蚀刻。晶种层的剩余部分和导电材料形成通孔112。
在图4中,通过粘合剂116将集成电路管芯114粘合至介电层108。如图4所示,在第一封装件区域600和第二封装件区域602的每一个中均粘合两个集成电路管芯114,并且在其他的实施例中,可以在每一个区域中粘合更多或更少的集成电路管芯。集成电路管芯114可以是逻辑管芯(例如,中央处理单元、微控制器等)、存储器管芯(例如,动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯等)、电源管理管芯(例如,电源管理集成电路(PMIC)管芯)、射频(RF)管芯、传感器管芯、微机电系统(MEMS)管芯、信号处理管芯(例如数字信号处理(DSP)管芯)、前端管芯(例如,模拟前端(AFE)管芯)或它们的组合等。此外,在一些实施例中,集成电路管芯114可以是不同的尺寸(例如,不同的高度和/或表面积),以及在其他实施例中,集成电路管芯114可以是相同的尺寸(例如,相同的高度和/或表面积)。
在粘附至介电层108之间,集成电路管芯114可以根据可接受的制造工艺来处理以在集成电路管芯114中形成集成电路。例如,每个集成电路管芯114包括半导体衬底118,诸如掺杂或未掺杂的硅或绝缘体上半导体(SOI)衬底的有源层。半导体衬底可以包括其他半导体材料,诸如锗;化合物半导体,包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟;合金半导体,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP;或它们的组合。也可以使用诸如多层或梯度衬底的其他衬底。诸如晶体管、二极管、电容器、电阻器等的器件可以形成在半导体衬底118中和/或上,并且可以由例如半导体衬底118上的一个或多个介电层中的金属化图案形成的互连结构120互连,以形成集成电路。
集成电路管芯114还包括诸如铝焊盘的焊盘122(制造外部连接件至该焊盘)。焊盘122位于可以集成电路管芯114的被称为相应的有源侧上。钝化膜124位于集成电路管芯114上并且位于部分焊盘122上。开口穿过钝化膜124至焊盘122。诸如导电柱(例如,包括诸如铜的金属)的管芯连接件126位于穿过钝化膜124的开口中并且机械和电连接至相应的焊盘122。例如,可以通过电镀等形成管芯连接件126。管芯连接件126电连接集成电路管芯114的相应的集成电路。
介电材料128位于集成电路管芯114的有源侧上,诸如位于钝化膜124和管芯连接件126上。介电材料128横向包封管芯连接件126,并且介电材料128与相应的集成电路管芯114横向相连。介电材料128可以是诸如PBO、聚酰亚胺、BCB等的聚合物;诸如氮化硅等的氮化物;诸如氧化硅、PSG、BSG、BPSG等的氧化物;或它们的组合,并且可以例如通过旋涂、层压、CVD等形成。
粘合剂116位于集成电路管芯114的背侧上并且将集成电路管芯114粘合至背侧再分布结构110,诸如示出的介电层108。粘合剂116可以是任何适当的粘合剂、环氧树脂、管芯附接膜(DAF)等。可将粘合剂116应用于集成电路管芯114的背面,诸如应用于相应的半导体晶圆的背面,或者应用于载体衬底100的表面上方。可以通过诸如锯或切来切割集成电路管芯114,并且例如,使用拾放工具通过粘合剂116将集成电路管芯114粘附至介电层108。
在图5中,在各个组件上形成包封剂130。包封剂130可以是模塑料、环氧树脂等,并且可以通过压缩模塑、传递模塑等来应用包封剂130。在固化之后,包封剂130可以经受研磨工艺以暴露通孔112和管芯连接件126。在研磨工艺之后,通孔112、管芯连接件126和包封剂130的顶面可以共面。在一些实施例中,例如,如果通孔112和管芯连接件126已经暴露,则可以省略研磨。
在图6至图16中,形成前侧再分布结构160。如图16将要示出的,前侧再分布结构160包括介电层132、140、148和156以及金属化图案138、146和154。
在图6中,在包封剂130、通孔112和管芯连接件126上沉积介电层132。在一些实施例中,介电层132由聚合物形成,聚合物可以是使用光刻掩模可以图案化的诸如PBO、聚酰亚胺、BCB等的感光材料。在其他实施例中,介电层132由氮化物(诸如氮化硅)、氧化物(诸如氧化硅、PSG、BSG、BPSG)等形成。可通过旋转涂布、层压、CVD等或其组合形成介电层132。
然后,在图7中,图案化介电层132。图案化形成开口以暴露通孔112的部分和管芯连接件126的部分。当介电层132为感光材料时,诸如通过将介电层132暴露于光的可接受的工艺实施图案化,或者例如,通过使用各向异性蚀刻的蚀刻实施图案化。如果介电层132是感光材料,可以在曝光之后显影介电层132。
在图8中,具有通孔的金属化图案138形成在介电层132上。作为形成金属化图案138的实例,晶种层(未示出)形成在介电层132上方以及穿过介电层132的开口中。在一些实施例中,晶种层为金属层,其可为单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和钛层上方的铜层。例如,可以使用PVD等形成晶种层。然后在晶种层上形成并且图案化光刻胶。该光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案138。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中以及在晶种层的暴露的部分上形成导电材料。可通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括金属,如铜、钛、钨、铝等。然后,去除光刻胶以及晶种层的其上未形成导电材料的部分。可通过可接受的灰化或剥离工艺去除光刻胶,诸如使用氧等离子体等。一旦去除光刻胶,就诸如通过使用可接受的蚀刻工艺去除晶种层的暴露的部分,诸如通过湿或干蚀刻。晶种层的剩余部分和导电材料形成金属化图案138和通孔。在穿过介电层132至例如通孔112和/或管芯连接件126的开口中形成通孔。
在图9中,在金属化图案138和介电层132上沉积介电层140。在一些实施例中,介电层140由聚合物形成,聚合物可以是使用光刻掩模可以图案化的诸如PBO、聚酰亚胺、BCB等的感光材料。在其他实施例中,介电层140由氮化物(诸如氮化硅)、氧化物(诸如氧化硅、PSG、BSG、BPSG)等形成。可通过旋转涂布、层压、CVD等或其组合形成介电层140。
然后,在图10中,图案化介电层140。图案化形成开口以暴露金属化图案138的部分。当介电层为感光材料时,诸如通过将介电层140暴露于光的可接受的工艺实施图案化,或者例如,通过使用各向异性蚀刻的蚀刻实施图案化。如果介电层140是感光材料,可以在曝光之后显影介电层140。
在图11中,具有通孔的金属化图案146形成在介电层140上。作为形成金属化图案146的实例,晶种层(未示出)形成在介电层140上方以及穿过介电层140的开口中。在一些实施例中,晶种层为金属层,其可为单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和钛层上方的铜层。例如,可以使用PVD等形成晶种层。然后在晶种层上形成并且图案化光刻胶。该光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案146。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中以及在晶种层的暴露的部分上形成导电材料。可通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括金属,如铜、钛、钨、铝等。然后,去除光刻胶以及晶种层的其上未形成导电材料的部分。可通过可接受的灰化或剥离工艺去除光刻胶,诸如使用氧等离子体等。一旦去除光刻胶,就诸如通过使用可接受的蚀刻工艺去除晶种层的暴露的部分,诸如通过湿或干蚀刻。晶种层的剩余部分和导电材料形成金属化图案146和通孔。例如,在穿过介电层140的至金属化图案138的部分的开口中形成通孔。
在图12中,在金属化图案146和介电层140上沉积介电层148。在一些实施例中,介电层148由聚合物形成,聚合物可以是使用光刻掩模可以图案化的诸如PBO、聚酰亚胺、BCB等的感光材料。在其他实施例中,介电层148由氮化物(诸如氮化硅)、氧化物(诸如氧化硅、PSG、BSG、BPSG)等形成。可通过旋转涂布、层压、CVD等或其组合形成介电层148。
然后,在图13中,图案化介电层148。图案化形成开口以暴露金属化图案146的部分。当介电层为感光材料时,诸如通过将介电层148暴露于光的可接受的工艺实施图案化,或者例如,通过使用各向异性蚀刻的蚀刻实施图案化。如果介电层148是感光材料,可以在曝光之后显影介电层148。
在图14中,具有通孔的金属化图案154形成在介电层148上。作为形成金属化图案154的实例,晶种层(未示出)形成在介电层148上方以及穿过介电层148的开口中。在一些实施例中,晶种层为金属层,其可为单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和钛层上方的铜层。例如,可以使用PVD等形成晶种层。然后在晶种层上形成并且图案化光刻胶。该光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案154。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中以及在晶种层的暴露的部分上形成导电材料。可通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括金属,如铜、钛、钨、铝等。然后,去除光刻胶以及晶种层的其上未形成导电材料的部分。可通过可接受的灰化或剥离工艺去除光刻胶,诸如使用氧等离子体等。一旦去除光刻胶,就诸如通过使用可接受的蚀刻工艺去除晶种层的暴露的部分,诸如通过湿或干蚀刻。晶种层的剩余部分和导电材料形成金属化图案154和通孔。例如,在穿过介电层148至金属化图案146的部分的开口中形成通孔。
在图15中,在金属化图案154和介电层148上沉积介电层156。在一些实施例中,介电层156由聚合物形成,聚合物可以是使用光刻掩模可以图案化的诸如PBO、聚酰亚胺、BCB等的感光材料。在其他实施例中,介电层156由氮化物(诸如氮化硅)、氧化物(诸如氧化硅、PSG、BSG、BPSG)等形成。可通过旋转涂布、层压、CVD等或其组合形成介电层156。
然后,在图16中,图案化介电层156。图案化形成开口以暴露金属化图案154的随后用于形成焊盘162的部分。当介电层为感光材料时,诸如通过将介电层156暴露于光的可接受的工艺实施图案化,或者例如,通过使用各向异性蚀刻的蚀刻实施图案化。如果介电层156是感光材料,可以在曝光之后显影介电层156。
作为实例示出了前侧再分布结构160。更多或更少的介电层和金属化图案可以形成在前侧再分布结构160中。如果将要形成更少的介电层和金属化图案,那么可以省略以上所讨论的步骤和工艺。如果将要形成更多的介电层和金属化图案,那么可以重复以上所讨论的步骤和工艺。本领域的普通技术人员将容易理解,会省略或重复哪些步骤和工艺。
在图17中,在前侧再分布结构160的外侧上形成焊盘162。焊盘162用于连接至导电连接件166和无源器件170(见图18),并且焊盘162可以被称为凸块下金属(UBM)162。在示出的实施例中,焊盘162形成为穿过开口,该开口穿过介电层156至金属化图案154。作为形成焊盘162的实例,在第一介电层156上方形成晶种层(未示出)。在一些实施例中,晶种层为金属层,其可为单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和钛层上方的铜层。例如,可以使用PVD等形成晶种层。然后在晶种层上形成并且图案化光刻胶。该光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于焊盘162。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中以及在晶种层的暴露的部分上形成导电材料。可通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括金属,如铜、钛、钨、铝等。然后,去除光刻胶以及晶种层的其上未形成导电材料的部分。可通过可接受的灰化或剥离工艺去除光刻胶,诸如使用氧等离子体等。一旦去除光刻胶,就诸如通过使用可接受的蚀刻工艺去除晶种层的暴露的部分,诸如通过湿或干蚀刻。晶种层的剩余部分和导电材料形成焊盘162。在实施例中,当不同地形成焊盘162时,可以使用更多的光刻胶和图案化步骤。
在图18中,导电连接件166形成在焊盘162上并且IPD部件170连接至金属化图案焊盘162。可以使用具有焊料层的微凸块将IPD部件连接至UBM 162。在一些实施例中,在将IPD部件连接并安装到焊盘162之前,可以将导电连接件166安装到焊盘162上。在一些实施例中,在将IPD部件连接并安装到焊盘162之后,可以将导电连接件166安装到焊盘162上。
在将IPD部件170连接至焊盘162之前,可根据合适的制造工艺处理IPD部件170以在IPD部件170中形成无源器件。例如,在IPD部件170的主要结构172中,每个IPD部件均包括一个或多个无源器件。主要结构172可以包括衬底和/或包封剂。在包括衬底的实施例中,衬底可以是半导体衬底,诸如掺杂或未掺杂的硅、或SOI衬底的有源层。半导体衬底可以包括其他半导体材料,诸如锗;化合物半导体,包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟;合金半导体,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP;或它们的组合。也可以使用其他衬底,诸如多层或梯度衬底。无源器件可以包括电容器、电阻器、电感器等或它们的组合。可以在半导体衬底中和/或半导体衬底上、和/或包封剂内形成无源器件,并且可以通过例如主要结构172上的一个或多个介电层中的金属化图案形成的互连结构174互连无源器件,以形成集成无源器件170。
IPD组件170还包括形成并连接至互连结构174的微凸块176,形成至该微凸块的外部连接件。微凸块176具有位于形成在微凸块一端上的焊料层或凸块178,该焊料层或凸块178在前侧再分布结构160和IPD组件170之间形成焊料结合点。与诸如在球栅阵列(BGA)连接件(见导电连接件166)中使用的传统的焊料球(可以具有从约150μm至约300μm的范围内的直径)相比,微凸块176具有更小的直径,例如,在从约10μm至约40μm的范围内。在一些实施例中,微凸块176的间距可以为大约40μm或更大。
在一些实施例中,在接合工艺期间,不能将IPD组件170压至再分布结构160上。在这些实施例中,例如,可以通过使用拾放工具将IPD部件170放置在导电连接件166的水平处,开始IPD部件170的接合。然后,拾放工具将IPD部件170降落至开口上以及前侧再分布结构160的暴露的金属化图案154上。在随后的接合工艺中,通过例如回流工艺将微凸块176接合至金属化图案154上,结果,形成焊料结合点,该焊料结合点将IPD部件170的微凸块176与封装件的焊盘162电连接和机械连接。微凸块176的小尺寸允许微凸块176之间的细小间距并且使高密度连接成为可能。
导电连接件166可以是BGA连接件、焊球、金属柱、可控坍塌芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯浸金技术(ENEPIG)形成的凸块等。导电连接件166可以包括导电材料,诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合。在一些实施例中,通过最初由诸如蒸发、电镀、印刷、焊料转移、植球等常用的方法形成焊料层来形成导电连接件166。一旦在结构上形成焊料层,就可以执行回流,以将材料成形为期望的凸块形状。在另一个实施例中,导电连接件166是通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如铜柱)。金属支柱可以没有焊料并且具有基本上垂直的侧壁。在一些实施例中,在金属柱连接件166的顶部上形成金属覆盖层(未示出)。金属覆盖层可以包括通过电镀工艺形成的镍、锡、锡-铅、金、银、钯、铟、镍钯金、镍金等或它们组合。
图19和图20示出了用于封装结构的切割工艺的预切割工艺。在第一区域600和第二区域602之间的划线区中,切割装置182部分地切入再分布结构160内以在再分布结构160中形成凹槽184。在一些实施例中,用于预切割工艺的切割装置182是激光。预切割工艺可以在随后的切割工艺中防止再分布结构和它的层分层(例如,见图24)。
在图21中,实施载体衬底脱粘以使载体衬底100从背侧再分布结构(例如,介电层104)分离(脱粘)。根据一些实施例,脱粘包括将诸如激光或UV光的光投射到释放层102上,使得释放层102在光的热量下分解,并且可以去除载体衬底100。然后翻转该结构并且放置在带190上。
如图21中进一步所示,穿过介电层104形成开口以暴露金属化图案106的部分。例如,使用激光钻孔、蚀刻等形成开口。
在图22中,使用延伸穿过介电层104中的开口的导电连接件314将第二封装件300接合至形成的第一封装件200。第二封装件300与第一封装件200之间的接合可以是焊料接合或直接金属至金属(诸如铜至铜或锡至锡)接合。在一个实施例中,通过回流工艺将第二封装件300接合至第一封装件200。在该回流工艺中,导电连接件314与接合焊盘304和金属化图案106接触从而将第二封装件300物理且电连接至第一封装件200。在接合工艺之后,可以在金属化图案106和导电连接件314的界面处并且也在导电连接件314和接合焊盘304(未示出)之间的界面处形成IMC(未示出)。
在接合至第一封装件200之前,可根据合适的制造工艺处理第二封装件300以形成第二封装件300。例如,第二封装件300的每个均包括衬底302和连接至衬底302的一个或多个堆叠管芯308(308A和308B)。可以由诸如硅、锗、金刚石等的半导体材料制造衬底302。在一些实施例中,也可以使用化合物材料,诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷化砷镓、磷化镓铟、它们的组合等。此外,衬底302可以是SOI衬底。通常,SOI衬底包括半导体材料层,诸如外延生长的硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)或它们的组合。在可选地实施例中,衬底302是基于诸如玻璃纤维增强树脂核芯的绝缘核芯。核芯材料的实例是诸如FR4的玻璃纤维树脂。用于核芯材料的替代选择包括双马来酰亚胺-三嗪(BT)树脂、或可选地,其他印刷电路板(PCB)材料或薄膜。诸如味之素构建膜(ABF)的构建膜或其他层压膜可以用于衬底302。
衬底302可以包括有源器件或无源器件(未示出)。作为本领域的普通技术人员将会意识到,可以使用各种器件(诸如晶体管、电容器、电阻器、它们的组合等)来满足用于半导体封装件300的设计的结构和功能的需求。可以使用任何合适的方法来形成器件。
衬底302也可以包括金属化层(未示出)和贯通孔306。金属化层可以形成在有源器件和无源器件上方并且设计为连接各个器件以形成功能电路。金属化层可以由介电材料(例如,低k介电材料)和导电材料(例如,铜)的交替层形成并通过通孔将导电材料层互连,并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成金属化层。在一些实施例中,衬底302基本不含有源器件和无源器件。
衬底302可以具有位于衬底302的第一侧上的接合焊盘303以连接至堆叠管芯308,以及位于衬底302的第二侧上的接合焊盘304(衬底302的第二侧与第一侧相对)以连接至导电连接件314。在一些实施例中,通过在衬底302的第一侧和第二侧上的介电层(未示出)内形成凹槽(未示出)来形成接合焊盘303和304。凹槽可以形成为允许接合焊盘303和304嵌入在介电层内。在其他实施例中,由于接合焊盘303和304可以形成在介电层上,所以省略了凹槽。在一些实施例中,接合焊盘303和304包括由铜、钛、镍、金、钯等或它们的组合制成的薄晶种层(未示出)。接合焊盘303和304的导电材料可以沉积在薄晶种层上方。可以使用电化学镀工艺、化学镀工艺、CVD、ALD、PVD等或它们的组合形成导电材料。在实施例中,接合焊盘303和304的导电材料是铜、钨、铝、银、金等或它们的组合。
在实施例中,接合焊盘303和304是包括三个导电材料层(诸如钛层、铜层和镍层)的UBM。然而,本领域技术人员将认识到,有适于形成UBM303和304的材料和层的许多适当布置,诸如铬/铬-铜合金/铜/金的布置、钛/钛钨/铜的布置或铜/镍/金的布置。可用于UBM303和304的任何适当的材料或材料层完全旨在包括在本申请的范围内。在一些实施例中,贯通孔306穿过衬底302延伸,并且将至少一个接合焊盘303连接到至少一个接合焊盘304。
在所示出的实施例中,尽管可以使用诸如导电凸块的其他连接件,堆叠管芯308通过接合线310连接至衬底302。在实施例中,堆叠管芯308是堆叠存储管芯。例如,堆叠存储管芯308可以包括低功率(LP)双数据率(DDR)存储器模块,诸如LPDDR1、LPDDR2、LPDDR3、LPDDR4等存储器模块。
在一些实施例中,堆叠管芯308和接合线310由模制材料312包封。例如,可以使用压缩模制将模制材料312模制在堆叠管芯308和接合线310上。在一些实施例中,模制材料312是模塑料、聚合物、环氧树脂、氧化硅填充材料等或它们的组合。执行固化步骤以固化成型材料312,其中固化可以是热固化、UV固化等或它们的组合。
在一些实施例中,堆叠管芯308和接合线310掩埋在模制材料312中,并且在固化模制材料312之后,对模制材料312执行诸如研磨的平坦化步骤以去除模制材料312的多余部分并且为第二封装件300提供基本平坦的表面。
在形成第二封装件300之后,通过导电连接件314、接合焊盘304和金属化图案106的方式将封装件300接合至第一封装件200。在一些实施例中,堆叠存储管芯308可以通过接合线310、接合焊盘303和304、贯通孔306、导电连接件314和贯通孔112连接至集成电路管芯114。
尽管导电连接件314和166不需要相同,导电连接件314可能与上文描述的导电连接件166类似并且此处不重复描述。在一些实施例中,在接合至导电连接件314之前,将导电连接件314涂覆助焊剂(未示出),诸如免清洗助焊剂。可以将导电连接件314浸入助焊剂或者可以将助焊剂喷射到导电连接件314上。在另一实施例中,助焊剂可以应用于金属化图案106的表面上。
在一些实施例中,在导电连接件314与至少一些在第二封装将300附接至第一封装件200之后留下的环氧助焊剂的环氧部分回流之前,导电连接件314可以具有形成于其上的环氧助焊剂(未示出)。
图23示出了第一封装件200和第二封装将300之间的底部填充物322的分配。底部填充物322可以是具有填充物或助焊剂的环氧化物或聚合物。使用喷头320分配底部填充物322,并且底部填充物322在邻近的第二封装件300之间分配以在第一封装件200和第二封装件300之间以及围绕导电连接件314流动。如图23中所示,位于划线区中的底部填充物322的一个分配点可以在两个区域600和602中的第一封装件200和第二封装件(300)之间形成底部填充物322。这增加了底部填充工艺的产量。可以通过沉积或印刷方法形成底部填充物322,也可以应用任何合适的工艺。在一些实施例中,可以通过毛细管流动工艺使底部填充物322在第一封装件200和第二封装件300之间流动。在一些实施例中,可以在高于环境大气压的压力下,将底部填充物分配/注入室或箱中。
在图24中,底部填充物322形成在两个区域600和602中的第一封装件200和第二封装件300之间,并且沿着第二封装件300的侧壁向上延伸。全覆盖底部填充工艺可以通过在分配步骤期间增加额外的底部填充物322和通过在较高的压力环境中固化底部填充物来实现。
在分配底部填充物322之后,在固化操作中将底部填充物322固化。可以在高于环境大气压的压力下,在室或箱中实施固化操作。在一些实施例中,在底部填充物固化工艺期间,室的压力在从约3kg/cm2至约20kg/cm2的范围内。在固化工艺期间,更高的压力可以加速底部填充物322中的空隙的移,这可以促进或增加底部填充物322的流动速度(例如,底部填充物322在第一封装件200和第二封装件300之间的流动速度)。在固化操作之后,底部填充物322的顶面322A可以是弯曲的。在一些实施例中,弯曲的上表面322A是凹形表面。在一些实施例中,由于省去了多余的底部填充物322,底部填充物322可以延伸至第二封装件300的顶面(并且有时候沿着一些顶面延伸)。
在图25中,通过沿着例如,在邻近的区域600和602之间的划线区的分割186来实施分割工艺。在一些实施例中,分割(工艺)186包括锯切工艺、激光工艺或它们的组合。分割(工艺)186将第一封装件区域600从第二封装件区域602或其他邻近的区域(未示出)分割。
图26示出了结果,所得到的单个封装结构包括可以来自第一封装区600或第二封装区602的一个中的第一封装件200和第二封装件300。封装件200可以称为集成扇出(InFO)封装件200。
图27示出了图26中示出的封装结构的部分的具体细节。具体地,图27示出了分割工艺之后底部填充物322的侧壁的具体细节。底部填充物322包括具有弯曲侧壁(被切割的先前的弯曲顶面322A)的部分和具有基本平坦部分的部分。在一些实施例中,弯曲的侧壁是凹形表面。
弯曲部分到平坦部分的转变点从第二封装件300的顶部(例如,模制材料312的顶部)是距离A,距离A是在垂直于衬底302的主表面的方向测量。在一些实施例中,距离A在从约100nm至约150nm的范围内。
如图27所示,平坦部分的高度是距离B+C。距离B是在沿着垂直于衬底302的主表面的方向从第二封装件300(例如,衬底302的底部)的底部到转变点测量的。在一些实施例中,距离B在从约300nm至约400nm的范围内。
距离C是第一封装件200和第二封装将300之间的沿着垂直于衬底302的主表面的方向的间隙高度。在一些实施例中,距离C在从约50nm至约150nm的范围内。在一些实施例中,C/(B+C)的比率在从约0.14至约0.27的范围内。
在图27中,第二封装件300的侧壁上的底部填充322的厚度示为距离D。可以从第二封装件300的侧壁(例如,模制材料312的侧壁)到再分布结构160中的包封环(图27中未示出)的外边界测量距离D。在一些实施例中,距离D在从约50nm至约100nm的范围内。
在图27中,底部填充物322的位于弯曲表面至平坦表面的转变点处的弯曲表面的夹角示为角α。在一些实施例中,角α在从约30度到约80度的范围内。
图28示出了包括第一封装件200、第二封装件300和衬底400的封装结构500。半导体封装件500包括安装到衬底400的封装件200和300。衬底400可以称为封装件衬底400。通过连接件166将封装件200安装至封装件衬底400。随着将封装件200安装到衬底400,IPD组件170置于封装件200的再分布结构160和衬底400之间。
可以由诸如硅、锗、金刚石等的半导体材料制造封装件衬底400。可选地,也可以使用化合物材料,诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷化砷镓、磷化镓铟、它们的组合等。此外,封装件衬底400可以是SOI衬底。通常,SOI衬底包括半导体材料层,诸如外延生长的硅、锗、硅锗、SOI、SGOI或它们的组合。在可选地实施例中,封装件衬底400是基于诸如玻璃纤维增强树脂核芯的绝缘核芯。核芯材料的实例是诸如FR4的玻璃纤维树脂。用于核芯材料的替代选择包括双马来酰亚胺-三嗪(BT)树脂、或可选地,其他PCB材料或薄膜。诸如ABF或其他层压膜的积层膜可以用于封装件衬底400。
封装件衬底400可以包括有源或无源器件(图22中未示出)。作为本领域的普通技术人员将会意识到,可以使用各种器件(诸如晶体管、电容器、电阻器、它们的组合等)来满足用于半导体封装件500的设计的结构和功能的需求。可以使用任何合适的方法来形成器件。
封装件衬底400也可以包括金属化层和通孔(未示出)以及位于金属化层和通孔上方的接合焊盘402。金属化层可以形成在有源和无源器件上方并且设计为连接各个器件以形成功能电路。金属化层可以由介电材料(例如,低k介电材料)和导电材料(例如,铜)的交替层形成并通过通孔将导电材料层互连,并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成。在一些实施例中,封装件衬底400基本不含有源和无源器件。
在一些实施例中,可以回流导电连接件166以将封装件200附接至接合焊盘402。导电连接件166将衬底400(包括衬底400中的金属化层)电连接和/或机械连接至第一封装件200。
在导电连接件166与在封装将200附接至衬底400之后留下的环氧助焊剂的环氧部分的至少一些回流之前,导电连接件166可以具有形成于其上的环氧助焊剂(未示出)。剩余的环氧部分可以用作底部填充物以减小应力和保护由于回流导电连接件166而形成的结合点。在一些实施例中,底部填充物(未示出)可以形成在第一封装件200和衬底400之间,并且围绕导电连接件166和IPD组件170。可以在接附封装件200之前或之后,通过毛细管流动工艺或合适的沉积方法形成底部填充物。
本发明的实施例包括封装结构,该封装结构包括全覆盖底部填充工艺,全覆盖底部填充工艺提高封装件侧壁的保护,提高封装件侧壁的保护提高了封装结构的稳定性和产量。所公开的全覆盖底部填充工艺也已经提高了底部填充物流速并且能够简化封装件的分割工艺。可以在比其他底部填充工艺更高的压力下固化底部填充物。在固化工艺期间,压力的增加可以加速底部填充物中的空隙的移动。
一个实施例是一种结构,该结构包括:第一封装件,第一封装件包括第一管芯和至少横向包封第一管芯的模塑料;通过第一组导电连接件接合至第一封装件的第二封装件,第二封装件包括第二管芯和位于第一封装件和第二封装件之间并且围绕第一组导电连接件的底部填充物,底部填充物具有沿着第二封装件的侧壁向上延伸的第一部分,该第一部分具有第一侧壁,该第一侧壁具有弯曲部分和平坦部分。
另一个实施例是一种方法,包括:形成多个第一封装件,多个第一封装件的每个均包括被模塑料围绕的第一管芯和位于第一管芯的第一侧和模塑料上的再分布结构,该再分布结构包括金属化图案;将包括凸块下金属的第一组导电连接件连接至再分布结构的第一金属化图案;使用第二组导电连接件将多个第二封装件接合至多个第一封装件;第二封装件邻近第一管芯的第二侧,第二侧与第一侧相对;在邻近的第二封装件之间、第一封装件和第二封装件之间以及围绕第二组导电连接件的划线区分配底部填充物,该底部填充物沿着多个第二封装件的侧壁向上延伸,在邻近的第二封装件之间,该底部填充物具有弯曲的凹顶面。
另一个实施例是一种方法,包括形成多个第一封装件,形成多个第一封装件的每一个包括:在载体衬底上方形成电连接件,附接第一管芯至载体衬底,电连接件从第一管芯的第二侧向第一管芯的第一侧延伸,第二侧与第一侧相对,使用模塑料包封第一管芯和电连接件,电连接件穿过模塑料延伸,在第一管芯的第一侧和模塑料上方形成再分布结构,将第一组导电连接件连接至再分布结构,邻近第一组导电连接件将无源组件接合至再分布结构,去除载体衬底。该方法还包括使用第二组导电连接件将多个第二封装件接合至多个第一封装件,第二封装件邻近第一管芯的第二侧,在第一封装件和第二封装件之间以及围绕第二组导电连接件分配底部填充物,底部填充物沿着多个第二封装件的侧壁向上延伸,在邻近的第二封装件之间,该底部填充物具有凹顶面,以及分割多个第一封装件以形成封装结构,在凹顶面切穿底部填充物以形成具有凹部分和平坦部分的底部填充物的侧壁。
根据本发明的一个实施例,提供了一种封装结构,包括:第一封装件,包括:第一管芯;和模塑料,至少横向包封所述第一管芯;第二封装件,通过第一组导电连接件接合至所述第一封装件,所述第二封装件包括第二管芯;以及底部填充物,位于所述第一封装件和所述第二封装件之间并且围绕所述第一组导电连接件,所述底部填充物具有沿着所述第二封装件的侧壁向上延伸的第一部分,所述第一部分具有第一侧壁,所述第一侧壁具有弯曲部分和平坦部分。
在上述结构中,所述底部填充物的所述第一侧壁的所述弯曲部分是弯曲的凹面。
在上述结构中,所述第一侧壁的所述平坦部分插入在所述第一侧壁的所述弯曲部分和所述第一封装件之间。
在上述结构中,所述底部填充物延伸至所述第二封装件的顶面。
在上述结构中,所述第二封装件包括管芯的堆叠件。
在上述结构中,所述第一管芯包括逻辑管芯以及所述管芯的堆叠件包括存储器管芯。
在上述结构中,所述第一封装件包括位于所述第一封装件的第一侧上的第一再分布结构,所述第二封装件接合至所述第一封装件的第二侧,所述第二侧与所述第一侧相对。
在上述结构中,还包括:集成无源器件(IPD)组件,接合至所述第一再分布结构;以及多个导电连接件,接合至所述第一再分布结构。
根据本发明的另一实施例,还提供了一种形成封装结构的方法,包括:形成多个第一封装件,多个所述第一封装件的每个均包括被模塑料围绕的第一管芯和位于所述第一管芯的第一侧和所述模塑料上的再分布结构,所述再分布结构包括金属化图案;将包括凸块下金属的第一组导电连接件连接至所述再分布结构的第一金属化图案;使用第二组导电连接件将多个第二封装件接合至多个所述第一封装件,所述第二封装件邻近所述第一管芯的第二侧,所述第二侧与所述第一侧相对;以及在位于邻近的所述第二封装件之间的划线区中以及所述第一封装件和所述第二封装件之间以及围绕所述第二组导电连接件分配底部填充物,所述底部填充物沿着多个所述第二封装件的侧壁向上延伸,所述底部填充物在邻近的所述第二封装件之间具有弯曲的凹顶面。
在上述方法中,还包括:分割多个所述第一封装件和多个所述第二封装件以形成封装结构,所述分割在所述弯曲的凹顶面处切割穿过所述底部填充物以形成底部填充物的侧壁,所述底部填充物的侧壁具有弯曲的凹部分和平坦部分。
在上述方法中,分割多个所述第一封装件和多个所述第二封装件以形成封装结构包括:在将多个所述第二封装件接合至多个所述第一封装件之前,通过部分地切割至所述再分布结构内来预切割多个所述第一封装件;以及在将多个所述第二封装件接合至多个所述第一封装件并且形成所述底部填充物之后,切割穿过所述底部填充物和多个所述第一封装件以形成所述封装结构。
在上述方法中,预切割多个所述第一封装件包括使用激光,以及其中,切割穿过所述底部填充物和多个所述第一封装件使用管芯锯切。
在上述方法中,所述底部填充物的所述侧壁的所述平坦部分插入在所述侧壁的所述弯曲的凹部分和所述第一封装件之间。
在上述方法中,还包括:将集成无源器件组件接合至位于所述再分布结构的所述第一金属化图案上的凸块下金属,所述集成无源器件组件邻近所述第一组导电连接件;以及使用所述第一组导电连接件将所述封装结构接合至衬底,所述集成无源器件组件插入在所述衬底和所述第一封装件的所述再分布结构之间。
在上述方法中,还包括:在高于环境大气压的压力下,固化分配的所述底部填充物。
在上述方法中,形成多个所述第一封装件的每个均包括:在载体衬底上方形成电连接件;将第一管芯附接至所述载体衬底,所述电连接件从所述第一管芯的第二侧延伸至所述第一管芯的所述第一侧,所述电连接件邻近所述第一管芯;使用模塑料包封所述第一管芯和所述电连接件;以及在所述第一管芯的所述第一侧和所述模塑料上面形成所述再分布结构。
根据本发明的又一实施例,还提供了一种形成封装结构的方法,包括:形成多个第一封装件,形成所述第一封装件的每个均包括:在载体衬底上方形成电连接件;将第一管芯附接至所述载体衬底,所述电连接件从所述第一管芯的第二侧延伸至所述第一管芯的第一侧,所述第二侧与所述第一侧相对;用模塑料包封所述第一管芯和所述电连接件,所述电连接件延伸穿过所述模塑料;在所述第一管芯的所述第一侧和所述模塑料上方形成再分布结构;将第一组导电连接件连接至所述再分布结构;邻近所述第一组导电连接件将无源组件接合至所述再分布结构;以及去除所述载体衬底;使用第二组导电连接件将多个第二封装件接合至多个所述第一封装件,所述第二封装件邻近所述第一管芯的所述第二侧;在所述第一封装件和所述第二封装件之间以及围绕所述第二组导电连接件分配底部填充物,所述底部填充物沿着多个所述第二封装件的侧壁向上延伸,所述底部填充物在邻近的第二封装件之间具有凹顶面;以及分割多个所述第一封装件和多个所述第二封装件以形成封装结构,所述分割在所述凹顶面处切割穿过所述底部填充物以形成底部填充物的侧壁,所述底部填充物的侧壁具有凹部分和平坦部分。
在上述方法中,所述底部填充物的所述侧壁的所述平坦部分插入在所述侧壁的所述凹部分和所述第一封装件之间。
在上述方法中,所述底部填充物延伸至所述第二封装件的顶面。
在上述方法中,分割多个所述第一封装件和多个所述第二封装件以形成所述封装结构包括:在将多个所述第二封装件接合至多个所述第一封装件之前,通过部分地切割至所述再分布结构内来预切割多个所述第一封装件;以及在将多个所述第二封装件接合至多个所述第一封装件以及分配所述底部填充物之后,切割穿过所述底部填充物和多个所述第一封装件以形成所述封装结构。
上述内容概括了几个实施例的特征使得本领域技术人员可更好地理解本发明的各个方面。本领域技术人员应该理解,可以很容易地使用本发明作为基础来设计或更改其他的处理和结构以用于达到与本发明所介绍实施例相同的目的和/或实现相同优点。本领域技术人员也应该意识到,这些等效结构并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,可以进行多种变化、替换以及改变。
Claims (10)
1.一种封装结构,包括:
第一封装件,包括:
第一管芯;和
模塑料,至少横向包封所述第一管芯;
第二封装件,通过第一组导电连接件接合至所述第一封装件,所述第二封装件包括第二管芯;以及
底部填充物,位于所述第一封装件和所述第二封装件之间并且围绕所述第一组导电连接件,所述底部填充物具有沿着所述第二封装件的侧壁向上延伸的第一部分,所述第一部分具有第一侧壁,所述第一侧壁具有弯曲部分和平坦部分。
2.根据权利要求1所述的结构,其中,所述底部填充物的所述第一侧壁的所述弯曲部分是弯曲的凹面。
3.根据权利要求1所述的结构,其中,所述第一侧壁的所述平坦部分插入在所述第一侧壁的所述弯曲部分和所述第一封装件之间。
4.根据权利要求1所述的封装件,其中,所述底部填充物延伸至所述第二封装件的顶面。
5.根据权利要求1所述的结构,其中,所述第二封装件包括管芯的堆叠件。
6.根据权利要求5所述的结构,其中,所述第一管芯包括逻辑管芯以及所述管芯的堆叠件包括存储器管芯。
7.根据权利要求1所述的结构,其中,所述第一封装件包括位于所述第一封装件的第一侧上的第一再分布结构,所述第二封装件接合至所述第一封装件的第二侧,所述第二侧与所述第一侧相对。
8.根据权利要求7所述的结构,还包括:
集成无源器件(IPD)组件,接合至所述第一再分布结构;以及
多个导电连接件,接合至所述第一再分布结构。
9.一种形成封装结构的方法,包括:
形成多个第一封装件,多个所述第一封装件的每个均包括被模塑料围绕的第一管芯和位于所述第一管芯的第一侧和所述模塑料上的再分布结构,所述再分布结构包括金属化图案;
将包括凸块下金属的第一组导电连接件连接至所述再分布结构的第一金属化图案;
使用第二组导电连接件将多个第二封装件接合至多个所述第一封装件,所述第二封装件邻近所述第一管芯的第二侧,所述第二侧与所述第一侧相对;以及
在位于邻近的所述第二封装件之间的划线区中以及所述第一封装件和所述第二封装件之间以及围绕所述第二组导电连接件分配底部填充物,所述底部填充物沿着多个所述第二封装件的侧壁向上延伸,所述底部填充物在邻近的所述第二封装件之间具有弯曲的凹顶面。
10.一种形成封装结构的方法,包括:
形成多个第一封装件,形成所述第一封装件的每个均包括:
在载体衬底上方形成电连接件;
将第一管芯附接至所述载体衬底,所述电连接件从所述第一管芯的第二侧延伸至所述第一管芯的第一侧,所述第二侧与所述第一侧相对;
用模塑料包封所述第一管芯和所述电连接件,所述电连接件延伸穿过所述模塑料;
在所述第一管芯的所述第一侧和所述模塑料上方形成再分布结构;
将第一组导电连接件连接至所述再分布结构;
邻近所述第一组导电连接件将无源组件接合至所述再分布结构;以及
去除所述载体衬底;
使用第二组导电连接件将多个第二封装件接合至多个所述第一封装件,所述第二封装件邻近所述第一管芯的所述第二侧;
在所述第一封装件和所述第二封装件之间以及围绕所述第二组导电连接件分配底部填充物,所述底部填充物沿着多个所述第二封装件的侧壁向上延伸,所述底部填充物在邻近的第二封装件之间具有凹顶面;以及
分割多个所述第一封装件和多个所述第二封装件以形成封装结构,所述分割在所述凹顶面处切割穿过所述底部填充物以形成底部填充物的侧壁,所述底部填充物的侧壁具有凹部分和平坦部分。
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TWI685927B (zh) | 2020-02-21 |
KR20180030755A (ko) | 2018-03-26 |
US20180350784A1 (en) | 2018-12-06 |
US20180082988A1 (en) | 2018-03-22 |
US10867973B2 (en) | 2020-12-15 |
KR102069256B1 (ko) | 2020-01-22 |
CN107833864B (zh) | 2020-03-31 |
US11990454B2 (en) | 2024-05-21 |
US20210098434A1 (en) | 2021-04-01 |
TW201814850A (zh) | 2018-04-16 |
US10529697B2 (en) | 2020-01-07 |
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