CN108010854A - 封装件及其形成方法 - Google Patents

封装件及其形成方法 Download PDF

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Publication number
CN108010854A
CN108010854A CN201710681961.7A CN201710681961A CN108010854A CN 108010854 A CN108010854 A CN 108010854A CN 201710681961 A CN201710681961 A CN 201710681961A CN 108010854 A CN108010854 A CN 108010854A
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China
Prior art keywords
integrated circuit
hole
segment
circuit lead
conductive
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CN201710681961.7A
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CN108010854B (zh
Inventor
黄立贤
苏安治
吴集锡
余振华
叶德强
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

实施例的封装件包括第一集成电路管芯、第一集成电路管芯周围的密封剂、将第一导电通孔电连接至第二导电通孔的导线，该导线包括位于第一集成电路管芯上方并且具有第一宽度的第一段，以及位于第一集成电路管芯上方具有大于第一宽度的第二宽度的第二段，第二段在第一集成电路管芯和密封剂之间的第一边界上方延伸。本发明的实施例还涉及形成封装件的方法。

Description

封装件及其形成方法
技术领域
本发明的实施例涉及封装件及其形成方法。
背景技术
由于各个电组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的持续改进，半导体工业已经经历了快速增长。对于大部分而言，这种集成密度的改进来自于最小部件尺寸的反复减小，这允许更多的组件集成至给定的区域。随着对缩小电子器件的需求的增长，已经出现了对更小和更具创造性的半导体管芯的封装技术的需求。这种封装系统的实例为堆叠式封装(PoP)技术。在PoP器件中，顶部半导体封装件堆叠在底部半导体封装件的顶面上以提供高水平的集成和组件密度。PoP技术通常使得能够在印刷电路板(PCB)上生产具有增强的功能和小的覆盖区的半导体器件。
发明内容
本发明的实施例提供了一种封装件，包括：第一集成电路管芯；密封剂，位于所述第一集成电路管芯周围；导线，将第一导电通孔电连接至第二导电通孔，所述导线包括：第一段，位于所述第一集成电路管芯上方并且具有第一宽度；以及第二段，位于所述第一集成电路管芯上方并且具有大于所述第一宽度的第二宽度，所述第二段在所述第一集成电路管芯和所述密封剂之间的第一边界上方延伸。
本发明的另一实施例提供了一种形成封装件的方法，包括：将第一集成电路管芯包封在密封剂中；在所述第一集成电路管芯和所述密封剂上方形成再分布层(RDL)，其中，所述再分布层包括：第一导电通孔，位于所述第一集成电路管芯上方；以及导线，将所述第一导电通孔电连接至第二导电通孔，所述导线包括：第一段，位于所述第一集成电路管芯上方并且具有第一宽度；和第二段，在所述第一集成电路管芯和所述密封剂之间的边界上方延伸，所述第二段具有大于所述第一宽度的第二宽度。
本发明的又一实施例提供了一种形成封装件的方法，包括：形成第一封装件，包括：在载体衬底上方形成电连接器；将第一管芯和第二管芯附接至所述载体衬底，所述电连接器从所述第一管芯的背侧延伸至所述第一管芯的有源侧，所述有源侧与所述背侧相对，所述电连接器邻近所述第一管芯和所述第二管芯；用模塑料包封所述第一管芯、所述第二管芯和所述电连接器；以及在所述第一管芯和所述第二管芯的有源侧以及所述模塑料上面形成再分布结构，形成所述再分布结构包括：在所述第一管芯的所述有源侧上方形成第一导电通孔；在所述第二管芯的所述有源侧上方形成第二导电通孔；和形成将所述第一导电通孔电连接至所述第二导电通孔的导线，所述导线包括第一段、第二段和第三段，所述第一段位于所述第一管芯上方并且具有第一宽度，所述第二段在所述第一管芯和所述模塑料之间的第一边界上方延伸并且在所述第二管芯和所述模塑料之间的第二边界上方延伸，所述第二段具有大于所述第一宽度的第二宽度，所述第三段位于所述第二管芯上方并且具有小于所述第二宽度的第三宽度。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图15示出了根据一些实施例的用于形成第一封装结构的工艺期间的中间步骤的截面图。
图16至图18示出了根据一些实施例的导电层路由的平面图。
图19至图24示出了根据一些实施例的用于进一步形成第一封装件并且将其它封装结构附接至第一封装件的工艺期间的中间步骤的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
此处讨论的实施例可以在特定的上下文中讨论，即，包括再分布层(RDL)路由设计的封装结构，该结构使得半导体密封剂边界(例如，硅/模塑料(Si/MC)边界)处具有更可靠的鲁棒性。该封装结构可以包括扇出封装件或扇入封装件并且可以包括一个或多个RDL。例如，将晶圆形式的封装件从室温加热至220℃，由于热膨胀系数(CTE)失配使得曲率变化，引起半导体密封剂边界处的RDL上的高弯曲应力。该半导体可以是管芯/芯片。跨越这种边界传递的应力可能引起RDL破裂。因此，在一些实施例中，RDL路由设计可以根据这种CTE失配来配置，并且用于改进的可靠性的鲁棒性和更少的制造缺陷。在一些实施例中，可以使在半导体-密封剂边界的预定距离内横穿的RDL宽于正常的RDL，使得它们不太可能破裂。此外，RDL可以是边界和与边界的预定距离之外的正常宽度，从而使得对RDL的更宽的迹线没有路由损失。
此外，本发明的教导适用于横穿在具有不同CTE的不同材料上方的一个或多个导电层的任何封装结构。其它实施例考虑了其它应用，诸如本领域普通技术人员在阅读本发明之后显而易见的不同封装件类型或不同配置。应该注意，此处讨论的实施例可以不必示出可能存在于结构中的每个组件或部件。例如，诸如当讨论一个组件可能足以表达实施例的方面时，可以从附图中省略多个组件。此外，此处讨论的方法实施例可能讨论为以特定顺序实施；然而，可以以任何逻辑顺序实施其它方法实施例。
图1至图15示出了根据一些实施例的用于形成第一封装结构的工艺期间的中间步骤的截面图。图1示出了载体衬底100和在载体衬底100上形成的释放层102。分别示出了用于形成第一封装件和第二封装件的第一封装区域600和第二封装区域602。
载体衬底100可以是玻璃载体衬底、陶瓷载体衬底等。载体衬底100可以是晶圆，从而使得可以在载体衬底100上同时形成多个封装件。释放层102可以由聚合物基材料形成，释放层可以与载体衬底100一起从将在随后步骤中形成的上面的结构去除。在一些实施例中，释放层102是环氧基热释放材料，在加热时该材料失去其粘合性，诸如光热转换(LTHC)释放涂层。在其他实施例中，释放层102可以是紫外(UV)胶，当暴露于UV光时失去其粘合性。释放层102可以以液体分配并且被固化，可以是层压至载体衬底100上的层压膜，或者可以是类似物。可以使释放层102的顶面齐平并且释放层102的顶面可以具有高度的共面性。
在图2中，形成介电层104和金属化图案106。如图2所示，在释放层102上形成介电层104。介电层104的底面可以与释放层102的顶面接触。在一些实施例中，介电层104由聚合物形成，诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等。在其他的实施例中，介电层104由诸如氮化硅的氮化物；诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺杂硼的磷硅酸盐玻璃(BPSG)等的氧化物等形成。可以通过任何可接受的沉积工艺形成介电层104，诸如旋涂、化学气相沉积(CVD)、层压等或它们的组合。
在介电层104上形成金属化图案106。以形成金属化图案106为例，在介电层104上方形成晶种层(未示出)。在一些实施例中，晶种层是金属层，该层可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和钛层上方的铜层。例如，可以使用PVD等形成晶种层。之后，在晶种层上形成光刻胶并且图案化光刻胶。该光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案106。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中以及晶种层的暴露的部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括金属，如铜、钛、钨、铝等。之后，去除光刻胶以及其上未形成导电材料的晶种层的部分。可以通过可接受的灰化或剥离工艺去除光刻胶，诸如使用氧等离子体等。一旦去除光刻胶，诸如通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)去除晶种层的暴露的部分。晶种层的剩余部分和导电材料形成金属化图案106。
在图3中，在金属化图案106和介电层104上形成介电层108。在一些实施例中，介电层108由聚合物形成，该聚合物可以是诸如PBO、聚酰亚胺、BCB等可以使用光刻掩模图案化的感光材料。在其他实施例中，介电层108由诸如氮化硅的氮化物；诸如氧化硅、PSG、BSG、BPSG的氧化物等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层108。之后，图案化介电层108以形成开口以暴露部分金属化图案106。当介电层为感光材料时，诸如通过将介电层108暴露于光的可接受的工艺或通过使用例如各向异性蚀刻的蚀刻进行图案化。
介电层104和108以及金属化图案106可以称为背侧再分布结构110。如示出的，背侧再分布结构110包括两个介电层104和108以及一个金属化图案106。在其它实施例中，背侧再分布结构110可以包括任何数量的介电层、金属化图案和通孔。通过重复用于形成金属化图案106和介电层108的工艺可以在背侧再分布结构110中形成一个或多个额外的金属化图案和介电层。可以通过在下面的介电层的开口中形成金属化图案的晶种层和导电材料来在金属化图案的形成期间形成通孔。因此，该通孔可以互连并且电连接各个金属化图案。
进一步在图3中，形成贯通孔112。以形成贯通孔112为例，在背侧再分布结构110(例如，如图示出的介电层108和金属化图案106的暴露的部分)上方形成晶种层。在一些实施例中，晶种层是金属层，该层可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和钛层上方的铜层。例如，可以使用PVD等形成晶种层。之后，在晶种层上形成光刻胶并且图案化光刻胶。该光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于贯通孔。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中以及晶种层的暴露的部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括金属，如铜、钛、钨、铝等。去除光刻胶以及其上未形成导电材料的晶种层的部分。可以通过可接受的灰化或剥离工艺去除光刻胶，诸如使用氧等离子体等。一旦去除光刻胶，诸如通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)去除晶种层的暴露的部分。晶种层的剩余部分和导电材料形成贯通孔112。
在图4中，集成电路管芯114通过粘合剂116粘合至介电层108。如图4示出的，在第一封装区域600和第二封装区域602的每个中均粘合两个集成电路管芯114，并且在其它的实施例中，可以在每个区域中粘合更多或更少的集成电路管芯114。例如，在实施例中，可以在每个区域中仅粘合一个集成电路管芯114。集成电路管芯114可以是逻辑管芯(例如，中央处理单元，微控制器等)、存储器管芯(例如，动态随机存取存储器(DRAM)管芯，静态随机存取存储器(SRAM)管芯等)、电源管理管芯(例如，电源管理集成电路(PMIC)管芯)、射频(RF)管芯、传感器管芯、微电子机械系统(MEMS)管芯、信号处理管芯(例如，数字信号处理(DSP)管芯)、前端管芯(例如，模拟前端(AFE)管芯)等或它们的组合。同样，在一些实施例中，集成电路管芯114可以是不同的尺寸(例如，不同的高度和/或不同的表面面积)，并且在其它实施例中，集成电路管芯114可以是相同的尺寸(例如，相同的高度和/或表面面积)。
在粘合至介电层108之前，可以根据适当的制造工艺处理集成电路管芯114以在集成电路管芯114中形成集成电路。例如，每个集成电路管芯114均包括半导体衬底118，诸如掺杂或未掺杂的硅或绝缘体上半导体(SOI)衬底的有源层。半导体衬底可以包括其它半导体材料，诸如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。也可以使用诸如多层的或梯度衬底的其它衬底。诸如晶体管、二极管、电容器、电阻器等的器件可以形成在半导体衬底118中和/或上并且可以通过互连结构120(例如，由半导体衬底118上的一个或多个介电层中的金属化图案形成)互连以形成集成电路。
集成电路管芯114还包括诸如铝焊盘的焊盘122，制造至该焊盘的外部连接。焊盘122位于可以称为集成电路管芯114的相应的有源侧上。钝化膜124位于集成电路管芯114上并且位于部分焊盘122上。开口穿过钝化膜124至焊盘122。诸如导电柱(例如，包括诸如铜的金属)的管芯连接器126位于穿过钝化膜124的开口中并且机械和电连接至相应的焊盘122。例如，可以通过镀等形成管芯连接器126。管芯连接器126电连接集成电路管芯114的相应的集成电路。
介电材料128位于集成电路管芯114的有源侧上，诸如位于钝化膜124和管芯连接器126上。介电材料128横向包封管芯连接器126，并且介电材料128与相应的集成电路管芯114横向有共同边界。介电材料128可以是诸如PBO、聚酰亚胺、BCB等的聚合物；诸如氮化硅等的氮化物；诸如氧化硅、PSG、BSG、BPSG等的氧化物；等或它们的组合并且例如，可以通过旋涂、层压、CVD等形成。
粘合剂116位于集成电路管芯114的背侧上并且将集成电路管芯114粘合至背侧再分布结构110，诸如图中的介电层108。粘合剂116可以是任何合适的粘合剂、环氧树脂、管芯附接膜(DAF)等。粘合剂116可以施加至集成电路管芯114的背侧，诸如至相应的半导体晶圆的背侧，或可以施加在载体衬底100的表面上方。集成电路管芯114可以是锯切的，诸如通过割锯或切割，并且可以使用例如拾取和放置工具通过粘合剂116粘合至介电层108。
在图5中，在各个组件上形成密封剂130。密封剂130可以是模塑料、环氧树脂等，并且可以通过压缩模制、转移模制等施加。在固化之后，密封剂130可以经受研磨工艺以暴露贯通孔112和管芯连接器126。在研磨工艺之后，贯通孔112、管芯连接器126和密封剂130的顶面共面。在一些实施例中，可以省略研磨，例如，如果贯通孔112和管芯连接器126已经暴露。
在图6至图15和图19中，形成前侧再分布结构160。如将在图19中示出的，前侧再分布结构160包括介电层132、140、148和156以及金属化图案138、146和154。
在图6中，介电层132沉积在密封剂130、贯通孔112和管芯连接器126上。在一些实施例中，介电层132由聚合物形成，该聚合物可以是诸如PBO、聚酰亚胺、BCB等可以使用光刻掩模图案化的感光材料。在其它实施例中，介电层132由诸如氮化硅的氮化物；诸如氧化硅、PSG、BSG、BPSG的氧化物等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层132。
在图7中，之后，图案化介电层132。该图案化形成开口以暴露贯通孔112和管芯连接器126的部分。可以通过可接受的工艺进行图案化，诸如通过将介电层132(当介电层132是感光材料时)暴露于光或通过使用例如各向异性蚀刻的蚀刻。如果介电层132是感光材料，则在曝光之后，可以显影介电层132。
在图8中，在介电层132上形成具有通孔的金属化图案138。以形成金属化图案138为例，在介电层132上方和穿过介电层132的开口中形成晶种层(未示出)。在一些实施例中，晶种层是金属层，该层可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和钛层上方的铜层。例如，可以使用PVD等形成晶种层。之后，在晶种层上形成光刻胶并且图案化光刻胶。该光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案138。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中以及晶种层的暴露的部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括金属，如铜、钛、钨、铝等。之后，去除光刻胶以及其上未形成导电材料的晶种层的部分。可以通过可接受的灰化或剥离工艺去除光刻胶，诸如使用氧等离子体等。一旦去除光刻胶，诸如通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)去除晶种层的暴露的部分。晶种层的剩余部分和导电材料形成金属化图案138和通孔。该通孔形成在穿过介电层132至例如贯通孔112和/或管芯连接器126的开口中。
在图9中，介电层140沉积在金属化图案138和介电层132上。在一些实施例中，介电层140由聚合物形成，该聚合物可以是诸如PBO、聚酰亚胺、BCB等可以使用光刻掩模图案化的感光材料。在其他实施例中，介电层140由诸如氮化硅的氮化物；诸如氧化硅、PSG、BSG、BPSG的氧化物等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层140。
在图10中，之后，图案化介电层140。该图案化形成开口以暴露金属化图案138的部分。可以通过可接受的工艺进行图案化，诸如通过将介电层140(当介电层140是感光材料时)暴露于光或通过使用例如各向异性蚀刻的蚀刻。如果介电层140是感光材料，则在曝光之后，可以显影介电层140。
在图11中，在介电层140上形成具有通孔的金属化图案146。以形成金属化图案146为例，在介电层140上方和穿过介电层140的开口中形成晶种层(未示出)。在一些实施例中，晶种层是金属层，该层可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和钛层上方的铜层。例如，可以使用PVD等形成晶种层。之后，在晶种层上形成光刻胶并且图案化光刻胶。该光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案146。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中以及晶种层的暴露的部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括金属，如铜、钛、钨、铝等。之后，去除光刻胶以及其上未形成导电材料的晶种层的部分。可以通过可接受的灰化或剥离工艺去除光刻胶，诸如使用氧等离子体等。一旦去除光刻胶，诸如通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)去除晶种层的暴露的部分。晶种层的剩余部分和导电材料形成金属化图案146和通孔。该通孔形成在穿过介电层140至例如金属化图案138的部分的开口中。
在图12中，介电层148沉积在金属化图案146和介电层140上。在一些实施例中，介电层148由聚合物形成，该聚合物可以是诸如PBO、聚酰亚胺、BCB等可以使用光刻掩模图案化的感光材料。在其他实施例中，介电层148由诸如氮化硅的氮化物；诸如氧化硅、PSG、BSG、BPSG的氧化物等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层148。
在图13中，之后，图案化介电层148。该图案化形成开口以暴露金属化图案146的部分。可以通过可接受的工艺进行图案化，诸如通过将介电层148(当介电层148是感光材料时)暴露于光或通过使用例如各向异性蚀刻的蚀刻。如果介电层148是感光材料，则在曝光之后，可以显影介电层148。
在图14中，在介电层148上形成具有通孔的金属化图案154。以形成金属化图案154为例，在介电层148上方和穿过介电层148的开口中形成晶种层(未示出)。在一些实施例中，晶种层是金属层，该层可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和钛层上方的铜层。例如，可以使用PVD等形成晶种层。之后，在晶种层上形成光刻胶并且图案化光刻胶。该光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案154。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中以及晶种层的暴露的部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括金属，如铜、钛、钨、铝等。之后，去除光刻胶以及其上未形成导电材料的晶种层的部分。可以通过可接受的灰化或剥离工艺去除光刻胶，诸如使用氧等离子体等。一旦去除光刻胶，诸如通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)去除晶种层的暴露的部分。晶种层的剩余部分和导电材料形成金属化图案154和通孔。该通孔形成在穿过介电层148至例如金属化图案146的部分的开口中。
在图15中，介电层156沉积在金属化图案154和介电层148上。在一些实施例中，介电层156由聚合物形成，该聚合物可以是诸如PBO、聚酰亚胺、BCB等可以使用光刻掩模图案化的感光材料。在其他实施例中，介电层156由诸如氮化硅的氮化物；诸如氧化硅、PSG、BSG、BPSG的氧化物等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层156。
图16、图17和图18示出了根据一些实施例的RDL路由的简化平面图。图16示出了图15的第一封装结构的一个的简化平面图。图16示出了包封在密封剂130中的两个集成电路管芯114A和114B。在实施例中，两个集成电路管芯114A和114B之间的距离D2可以为约50μm至约300μm。在另一实施例中，两个集成电路管芯114A和114B之间的距离D2可以是不同的值。第一集成电路管芯114A和密封剂130之间共有第一边界702A，并且第二集成电路管芯114B和密封剂130之间共有第二边界702B。
如图16示出的，导线704和708在集成电路管芯114A和114B与密封剂130之间的边界702A和702B上方延伸。导线704和708可以将集成电路管芯114A上方的导电通孔706A和710A电连接至和机械连接至集成电路管芯114B中和/或上方的导电通孔706B和710B。如上所述，由于集成电路管芯114A和114B的材料与密封剂130之间的CTE失配，因此器件封装件的曲率变化可能发生在边界702A和702B处，这对边界702A和702B的位置处的导线704和708施加应力。已经观察到，可以通过使接近边界702A和702B的密封剂130上方以及集成电路管芯114A和114B上方的导线704和708更宽来减轻对导线704和708的这种应力。
在上面的金属化图案154/146/138(RDL图案)的导线704和708中示出了导线的两种配置。导线704更短，其中，焊盘/通孔更接近边界702A和702B，并且导线708更长，其中，焊盘/通孔更远离边界702A和702B。这允许邻近的导线704和708的焊盘/通孔更紧凑地封装在一起。导电通孔706A、706B、710A和710B(例如，管芯连接器126、贯通孔112和/或金属化图案154/146/138的通孔)也示出为虚线以供参考。未示出介电层132、140、148和156。仅仅为了简单起见，由图16示出的平面图的各个部件示出为单层。在各个实施例中，根据图15的截面图，图16中的部件可以设置在不同的层中。此外，导线704和708可以设置在封装件内的相同的金属化图案中或不同的金属化图案中。例如，导线704可以设置在导线708的相同的层内、之上或之下。
导线704和708的每个分别包括至少一个更宽的部分704B和708B，该部分分别设置在密封剂130上方以及边界702A和702B的第一距离D1内的集成电路管芯114A和114B上方。导线704和708的每个均可以包括较窄部分704A和708A，窄于较宽部分，位于第一距离D1之外的集成电路管芯114A和114B上方。在一些实施例中，较宽部分704B和708B具有大于或等于约5μm的宽度W2。在一些实施例中，较窄部分704A和708A具有小于或等于2μm的宽度W1。在一些实施例中，第一距离D1大于或等于约10μm。在其它实施例中，宽度W1和W2以及第一距离可以是不同的值，其中，宽度W2大于宽度W1。以上描述的部分/段的宽度在垂直于该部分/段的纵轴的方向上测量。已经观察到，以此处描述的方法，通过根据集成电路管芯114A和/或114B以及密封剂130之间的CTE失配来配置导线，可以显著地减小在管芯/模塑料边界上方延伸的导线的应力。通过减小施加至导线的应力，可以减少RDL的金属化图案中的破裂和/或其它制造缺陷。此外，通过具有焊盘/通孔区域中的较窄部分704A和708A，具有较宽导线的路由损失是微不足道的。
除了导线的较宽部分包括钝角弯曲之外，图17示出了与图16类似的RDL路由的简化平面图。在图17中，除了较宽部分712B中的钝角弯曲之外，导线712以及通孔714A和714B与图16的导线704以及通孔706A和706B类似，并且不在此处重复描述。在图17中，除了较宽部分716B中的钝角弯曲之外，导线716以及通孔718A和718B与图16的导线708以及通孔710A和710B类似，并且不在此处重复描述。
导线712和716的较宽部分712B和716B中的钝角弯曲具有弯曲角度θ1。在一些实施例中，如较宽部分712B和716B的相应的段之间测量的，角度θ1可以大于90°并且小于180°。此外，导线以及导线段与边界702A和702B之间的角度仅是说明性的，导线段可以以横跨边界702A和702B的角度设置。
除了导线的较宽部分包括锐角弯曲之外，图18示出了与图16类似的RDL路由的简化平面图。在图18中，除了较宽部分720B中的锐角弯曲之外，导线720以及通孔722A和722B与图16的导线704以及通孔706A和706B类似，并且不在此处重复描述。在图18中，除了较宽部分724B中的锐角弯曲之外，导线724以及通孔726A和726B与图16的导线708以及通孔710A和710B类似，并且在此处不重复描述。
导线720和724的较宽部分720B和724B中的锐角弯曲具有弯曲角度θ2。在一些实施例中，如较宽部分720B和724B的相应的段之间测量的，角度θ2可以小于90°并且大于0°。此外，导线以及导线段与边界702A和702B之间的角度仅是说明性的，导线段可以以横跨边界702A和702B的角度设置。在一些实施例中，较宽部分的段之间的角度为直角，例如，约90°。
在图16、图17和图18中，导电通孔706B、710B、714B、718B、722B、和726B设置在集成电路管芯114B上方或之中。在其它实施例中，导电通孔706B、710B、714B、718B、722B和726B可以设置在密封剂130上方或之中，从而使得仅在集成电路管芯114A和密封剂130之间存在一个边界702。
在一些实施例中，上述RDL路由设计技术仅应用于位于集成电路管芯114和密封剂130上面的第一金属化图案(例如，金属化图案138)，而剩余的金属化图案没有参照图16和图17中所描述的配置路由。在一些其它实施例中，上述RDL路由设计技术应用于位于集成电路管芯114和密封剂130上面的所有金属化图案(例如，金属化图案138、146和154)。
图19至图24示出了根据一些实施例的用于进一步形成第一封装件并且用于将其它封装结构附接至第一封装件的工艺期间的中间步骤的截面图。
在图19中，之后，图案化介电层156。该图案化形成开口以暴露金属化图案154的部分。可以通过可接受的工艺进行图案化，诸如通过将介电层156(当介电层156是感光材料时)暴露于光或通过使用例如各向异性蚀刻的蚀刻。如果介电层156是感光材料，则在曝光之后，可以显影介电层156。
前侧再分布结构160示出为实例。可以在前侧再分布结构160中形成更多或更少的介电层和金属化图案。如果形成更少的介电层和金属化图案，则可以省略以上讨论的步骤和工艺。如果形成更多的介电层和金属化图案，则可以重复以上讨论的步骤和工艺。本领域中普通技术人员将容易理解，哪些步骤和工艺将省略或重复。
虽然参照前侧再分布结构160讨论此处描述的RDL路由设计，但是该RDL路由工艺的教导也可以应用于背侧再分布结构110。
在图20中，在前侧再分布结构160的外侧上形成焊盘162。焊盘162用于连接至导电连接器166(见图21)并且可以称为凸块下金属(UBM)162。在示出的实施例中，穿过开口(穿过介电层156)至金属化图案154形成焊盘162。以形成焊盘162为例，在介电层156上方形成晶种层(未示出)。在一些实施例中，晶种层是金属层，该层可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和钛层上方的铜层。例如，可以使用PVD等形成晶种层。之后，在晶种层上形成光刻胶并且图案化光刻胶。该光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于焊盘162。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中以及晶种层的暴露的部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括金属，如铜、钛、钨、铝等。之后，去除光刻胶以及其上未形成导电材料的晶种层的部分。可以通过可接受的灰化或剥离工艺去除光刻胶，诸如使用氧等离子体等。一旦去除光刻胶，诸如通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)去除晶种层的暴露的部分。晶种层的剩余部分和导电材料形成焊盘162。在实施例中，其中，不同地形成焊盘162，可以利用更多的光刻胶和图案化步骤。
在图21中，在UBM 162上形成导电连接器166。导电连接器166可以是BGA连接器、焊料球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯浸金技术(ENEPIG)形成的凸块等。导电连接器166可以包括导电材料，诸如焊料、铜、铝、金、镍、银、钯，锡等或它们的组合。在一些实施例中，最初通过诸如蒸发、电镀、印刷、焊料转移、球放置等常用的方法形成焊料层来形成导电连接器166。一旦已经在结构上形成焊料层，可以实施回流以将材料成形为期望的凸块形状。在另一实施例中，导电连接器166是由溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如铜柱)。该金属柱可以是无焊料的并且具有基本垂直的侧壁。在一些实施例中，在金属柱连接器166的顶部上形成金属盖层(未示出)。金属盖层可以包括镍、锡、锡-铅、金、银、钯、铟、镍-钯-金、镍-金等或它们的组合并且可以通过镀工艺形成。
在图22中，实施载体衬底分离以将载体衬底100从背侧再分布结构(例如，介电层104)分离(脱粘)。根据一些实施例，分离包括在释放层102上投射诸如激光或UV光的光，使得释放层102在光的热量下分解，并且可以去除载体衬底100。之后，翻转该结构并且放置在带190上。
如图22中进一步示出的，穿过介电层104形成开口以暴露金属化图案106的部分。例如，可以使用激光钻孔、蚀刻等形成开口。
例如，通过沿着邻近的区域600和602之间的划线区域锯切来实施切割工艺。锯切分割了第一封装区域600与第二封装区域602。
图23示出了产生的分割的封装件200，该封装件可以是第一封装区域600或第二封装区域602的一个。封装件200也可以称为集成扇出(InFO)封装件200。
图24示出了封装结构500，封装结构500包括封装件200(可以称为第一封装件200)、第二封装件300和衬底400。第二封装件300包括衬底302和连接至衬底302的一个或多个堆叠的管芯308(308A和308B)。衬底302可以由半导体材料制成，诸如硅、锗、金刚石等。在一些实施例中，也可以使用化合物材料，诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化镓铟、这些的组合等。此外，衬底302可以是绝缘体上硅(SOI)衬底。通常，SOI衬底包括半导体材料层，诸如外延硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)或它们的组合。在一个可选实施例中，衬底302基于绝缘芯，诸如玻璃纤维增强树脂芯。一种示例性芯材料是玻璃纤维树脂，诸如FR4。用于芯材料的替代物包括双马来酰亚胺-三嗪(BT)树脂，或者可选地，其它印刷电路板(PCB)材料或膜。诸如味之素积聚膜(ABF)或其它层压件的积聚膜可以用于衬底302。
衬底302可以包括有源和无源器件(未在图24中示出)。本领域中普通技术人员将意识到，诸如晶体管，电容器，电阻器，这些的组合等的各种器件均可以用于产生半导体封装件300的设计的结构和功能要求。可以使用任何合适的方法形成该器件。
衬底302也可以包括金属化层(未示出)和贯通孔306。金属化层可以形成在有源和无源器件上方并且设计为连接各个器件以形成功能电路。金属化层可以由电介质(例如，低k介电材料)和导电材料(例如，铜)的交替层形成并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成，其中，通孔互连导电材料层。在一些实施例中，衬底302基本无有源和无源器件。
衬底302可以具有位于衬底302的第一侧上以连接至堆叠的管芯308的接合焊盘303，以及位于衬底303的第二侧上以连接至导电连接器314的接合焊盘304，衬底302的第二侧与第一侧相对。在一些实施例中，通过在衬底302的第一侧和第二侧上的介电层(未示出)内形成凹槽(未示出)来形成接合焊盘303和304。该凹槽可以形成为允许接合焊盘303和304嵌入在介电层内。在其它实施例中，省略了凹槽，因为结合焊盘303和304可以形成在介电层上。在一些实施例中，接合焊盘303和304包括由铜、钛、镍、金、钯等或它们的组合制成的薄晶种层(未示出)。接合焊盘303和304的导电材料可以沉积在薄晶种层上方。可以通过电化学镀工艺、化学镀工艺、CVD、ALD、PVD等或它们的组合形成导电材料。在实施例中，接合焊盘303和304的导电材料是铜、钨、铝、银、金等或它们的组合。
在实施例中，接合焊盘303和304是UBM，该UBM包括三层导电材料，诸如钛层、铜层和镍层。然而，本领域中普通技术人员将意识到，存在适合于形成UBM 303和304的材料和层的许多合适的布置，诸如铬/铬-铜合金/铜/金的布置、钛/钛钨/铜的布置或铜/镍/金的布置。可以用于UBM303和304的任何合适的材料或材料层旨在完全地包括在本发明的范围内。在一些实施例中，贯通孔306穿过衬底302延伸并且将至少一个接合焊盘303连接至至少一个接合焊盘304。
在示出的实施例中，堆叠的管芯308通过引线接合310连接至衬底302，但是可以使用其它连接，诸如导电凸块。在实施例中，堆叠的管芯308是堆叠的存储器管芯。例如，堆叠的存储器管芯308可以包括低功率(LP)双数据速率(DDR)存储器模块，诸如LPDDR1、LPDDR2、LPDDR3、LPDDR4等存储器模块。
在一些实施例中，堆叠的管芯308和引线接合310可以由模塑材料312包封。例如，模塑材料312可以使用压缩模制模塑在堆叠的管芯308和引线接合310上。在一些实施例中，模塑材料312是模塑料、聚合物、环氧树脂、氧化硅填充材料等或它们的组合。可以实施固化步骤以固化模塑材料312，其中，该固化可以是热固化、UV固化等或它们的组合。
在一些实施例中，堆叠的管芯308和引线接合310掩埋在模塑材料312中，并且在模塑材料312固化之后，实施诸如研磨的平坦化步骤以去除模塑材料312的过量部分并且为第二封装件300提供基本平坦的表面。
在形成第二封装件300之后，通过导电连接器314、接合焊盘304和金属化图案106将第二封装件300接合至第一封装件200。在一些实施例中，可以通过引线接合310、接合焊盘303和304、贯通孔306、导电连接器314和贯通孔112将堆叠的存储器管芯308连接至集成电路管芯114。
导电连接器314可以与以上描述的导电连接器166类似并且不在此处重复该描述，但是导电连接器314和166不需要相同。在一些实施例中，在接合导电连接器314之前，导电连接器314涂布有助焊剂(未示出)，例如免洗助焊剂。导电连接器314可以浸入助焊剂中，或助焊剂可以喷射至导电连接器314。在另一实施例中，助焊剂可以施加至金属化图案106的表面。
在一些实施例中，导电连接器314可以具有在它们被回流之前在其上形成的环氧助焊剂(未示出)，在第二封装件300附接至第一封装件200之后剩余环氧助焊剂的至少一些环氧部分。这些剩余的环氧部分可以用作底部填充物以减少应力并且保护由回流导电连接器314产生的接头。在一些实施例中，底部填充物(未示出)可以形成在第二封装件300和第一封装件200之间并且围绕导电连接器314。底部填充物可以在第二封装件300附接之后，通过毛细管流动工艺形成，或者可以在第二封装件300附接之前，通过合适的沉积方法形成。
第二封装件300和第一封装件200之间的接合可以是焊料接合或直接金属至金属(诸如铜至铜或锡至锡)接合。在实施例中，第二封装件300通过回流工艺接合至第一封装件200。在这种回流工艺期间，导电连接器314与接合焊盘304和金属化图案106接触以将第二封装件300物理和电连接至第一封装件200。在接合工艺之后，IMC(未示出)可以在金属化图案106和导电连接器314的界面处形成并且也可以在导电连接器314和接合焊盘304之间的界面处形成(未示出)。
半导体封装件500包括安装至衬底400的封装件200和300。衬底400可以称为封装衬底400。封装件200使用导电连接器166安装至封装衬底400。
封装衬底400可以由半导体材料制成，诸如硅、锗、金刚石等。可选地，也可以使用化合物材料，诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化镓铟、这些的组合等。此外，封装衬底400可以是SOI衬底。通常，SOI衬底包括半导体材料层，诸如外延硅、锗、硅锗、SOI、SGOI或它们的组合。在一个可选实施例中，封装衬底400基于绝缘芯，诸如玻璃纤维增强树脂芯。一种示例性芯材料是玻璃纤维树脂，诸如FR4。用于芯材料的替代物包括双马来酰亚胺-三嗪BT树脂，或者可选地，其它PCB材料或膜。诸如ABF或其它层压件的积聚膜可以用于封装衬底400。
封装衬底400可以包括有源和无源器件(未在图24中示出)。本领域中普通技术人员将意识到，诸如晶体管，电容器，电阻器，这些的组合等的各种器件均可以用于产生半导体封装件500的设计的结构和功能要求。可以使用任何合适的方法形成该器件。
封装衬底400也可以包括金属化层和通孔(未示出)以及位于金属化层和通孔上方的接合焊盘402。金属化层可以形成在有源和无源器件上方并且设计为连接各个器件以形成功能电路。金属化层可以由电介质(例如，低k介电材料)和导电材料(例如，铜)的交替层形成并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成，其中，通孔互连导电材料层。在一些实施例中，封装衬底400基本无有源和无源器件。
在一些实施例中，可以回流导电连接器166以将封装件200附接至接合焊盘402。导电连接器166将衬底400(包括衬底400中的金属化层)电和/或物理连接至第一封装件200。
导电连接器166可以具有在它们被回流之前在其上形成的环氧助焊剂(未示出)，在封装件200附接至衬底400之后剩余环氧助焊剂的至少一些环氧部分。这些剩余的环氧部分可以用作底部填充物以减少应力并且保护由回流导电连接器166产生的接头。在一些实施例中，底部填充物(未示出)可以形成在第一封装件200和衬底400之间并且围绕导电连接器166。底部填充物可以在封装件200附接之后，通过毛细管流动工艺形成，或者可以在封装件200附接之前，通过合适的沉积方法形成。
本发明中的器件和方法的实施例具有许多优势。具体地，再分布层(RDL)路由设计使得半导体-密封剂边界(例如，硅/模塑料(Si/MC)边界)处具有更可靠的鲁棒性。例如，将晶圆形式的封装件从室温加热至220℃，由于CTE失配使得曲率急剧变化，引起半导体密封剂边界处的RDL上的高弯曲应力。从扇入传递至扇出区域的应力可能引起管芯拐角和管芯侧的RDL破裂。因此，在一些实施例中，RDL路由设计(见图16、17和18)可以用于可靠的鲁棒性。
一个实施例是结构，该结构包括第一集成电路管芯、第一集成电路管芯周围的密封剂、将第一导电通孔电连接至第二导电通孔的导线，该导线包括位于第一集成电路管芯上方并且具有第一宽度的第一段，以及位于第一集成电路管芯上方具有大于第一宽度的第二宽度的第二段，第二段在第一集成电路管芯和密封剂之间的第一边界上方延伸。
在上述结构中，其中，所述导线还包括第三段，所述第三段具有小于所述第二宽度的第三宽度，所述第二段设置在所述第一段和所述第三段之间。
在上述结构中，其中，所述第二段包括第一弯曲，所述第一弯曲具有第一角度。
在上述结构中，其中，所述第二段包括第一弯曲，所述第一弯曲具有第一角度，所述第一角度大于90°。
在上述结构中，其中，所述第二段包括第一弯曲，所述第一弯曲具有第一角度，所述第一角度小于90°。
在上述结构中，其中，所述第二段包括第一弯曲，所述第一弯曲具有第一角度，所述第一角度为90°。
在上述结构中，其中，所述第二导电通孔延伸至所述密封剂内或设置在所述密封剂上方。
在上述结构中，还包括邻近所述第一集成电路管芯的第二集成电路管芯，所述密封剂设置在所述第一集成电路管芯和所述第二集成电路管芯之间，所述第二导电通孔设置在所述第二集成电路管芯上方。
另一实施例是方法，该方法包括将第一集成电路管芯包封在密封剂中，在第一集成电路管芯和密封剂上方形成再分布层(RDL)，其中，RDL包括位于第一集成电路管芯上方的第一导电通孔以及将第一导电通孔电连接至第二导电通孔的导线，该导线包括位于第一集成电路管芯上方并且具有第一宽度的第一段，以及在第一集成电路管芯和密封剂之间的边界上方延伸的第二段，第二段具有大于第一宽度的第二宽度。
在上述方法中，其中，所述第二导电通孔延伸穿过所述密封剂。
在上述方法中，其中，所述第二导电通孔设置在所述密封剂上方。
在上述方法中，其中，所述第二导电通孔设置在第二集成电路管芯上方。
在上述方法中，其中，所述第二段包括第一弯曲，所述第一弯曲具有第一角度。
在上述方法中，其中，所述第二段包括第一弯曲，所述第一弯曲具有第一角度，所述第一角度大于90°。
在上述方法中，其中，所述第二段包括第一弯曲，所述第一弯曲具有第一角度，所述第一角度小于90°。
在上述方法中，其中，所述第二段包括第一弯曲，所述第一弯曲具有第一角度，所述第一角度为90°。
进一步的实施例是方法，该方法包括形成第一封装件，包括在载体衬底上方形成电连接器，将第一管芯和第二管芯附接至载体衬底，电连接器从第一管芯的背侧延伸至第一管芯的有源侧，有源侧与背侧相对，电连接器邻近第一管芯和第二管芯，用模塑料包封第一管芯、第二管芯和电连接器，并且在第一管芯和第二管芯的有源侧以及模塑料上面形成再分布结构，形成再分布结构包括在第一管芯的有源侧上方形成第一导电通孔，在第二管芯的有源侧上方形成第二导电通孔，并且形成将第一导电通孔电连接至第二导电通孔的导线，该导线包括第一段、第二段和第三段，第一段位于第一管芯上方并且具有第一宽度，第二段在第一管芯和模塑料之间的第一边界上方延伸并且在第二管芯和模塑料之间的第二边界上方延伸，第二段具有大于第一宽度的第二宽度，第三段位于第二管芯上方并且具有小于第二宽度的第三宽度。
在上述方法中，其中，所述第二段包括具有第一角度的至少一个弯曲。
在上述方法中，其中，形成所述第一封装件还包括：在所述再分布结构上方形成电连接至所述再分布结构的第一组导电连接器；以及去除所述载体衬底。
在上述方法中，还包括：使用第二组导电连接器将第二封装件接合至所述第一封装件，所述第二封装件接近所述第一管芯和所述第二管芯的背侧。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种封装件，包括：
第一集成电路管芯；
密封剂，位于所述第一集成电路管芯周围；
导线，将第一导电通孔电连接至第二导电通孔，所述导线包括：
第一段，位于所述第一集成电路管芯上方并且具有第一宽度；以及
第二段，位于所述第一集成电路管芯上方并且具有大于所述第一宽度的第二宽度，所述第二段在所述第一集成电路管芯和所述密封剂之间的第一边界上方延伸。
2.根据权利要求1所述的封装件，其中，所述导线还包括第三段，所述第三段具有小于所述第二宽度的第三宽度，所述第二段设置在所述第一段和所述第三段之间。
3.根据权利要求1所述的封装件，其中，所述第二段包括第一弯曲，所述第一弯曲具有第一角度。
4.根据权利要求3所述的封装件，其中，所述第一角度大于90°。
5.根据权利要求3所述的封装件，其中，所述第一角度小于90°。
6.根据权利要求3所述的封装件，其中，所述第一角度为90°。
7.根据权利要求1所述的封装件，其中，所述第二导电通孔延伸至所述密封剂内或设置在所述密封剂上方。
8.根据权利要求1所述的封装件，还包括邻近所述第一集成电路管芯的第二集成电路管芯，所述密封剂设置在所述第一集成电路管芯和所述第二集成电路管芯之间，所述第二导电通孔设置在所述第二集成电路管芯上方。
9.一种形成封装件的方法，包括：
将第一集成电路管芯包封在密封剂中；
在所述第一集成电路管芯和所述密封剂上方形成再分布层(RDL)，其中，所述再分布层包括：
第一导电通孔，位于所述第一集成电路管芯上方；以及
导线，将所述第一导电通孔电连接至第二导电通孔，所述导线包括：
第一段，位于所述第一集成电路管芯上方并且具有第一宽度；和
第二段，在所述第一集成电路管芯和所述密封剂之间的边界上方延伸，所述第二段具有大于所述第一宽度的第二宽度。
10.一种形成封装件的方法，包括：
形成第一封装件，包括：
在载体衬底上方形成电连接器；
将第一管芯和第二管芯附接至所述载体衬底，所述电连接器从所述第一管芯的背侧延伸至所述第一管芯的有源侧，所述有源侧与所述背侧相对，所述电连接器邻近所述第一管芯和所述第二管芯；
用模塑料包封所述第一管芯、所述第二管芯和所述电连接器；以及
在所述第一管芯和所述第二管芯的有源侧以及所述模塑料上面形成再分布结构，形成所述再分布结构包括：
在所述第一管芯的所述有源侧上方形成第一导电通孔；
在所述第二管芯的所述有源侧上方形成第二导电通孔；和
形成将所述第一导电通孔电连接至所述第二导电通孔的导线，所述导线包括第一段、第二段和第三段，所述第一段位于所述第一管芯上方并且具有第一宽度，所述第二段在所述第一管芯和所述模塑料之间的第一边界上方延伸并且在所述第二管芯和所述模塑料之间的第二边界上方延伸，所述第二段具有大于所述第一宽度的第二宽度，所述第三段位于所述第二管芯上方并且具有小于所述第二宽度的第三宽度。
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