TWI667762B - 半導體封裝中的重佈線層及其形成方法 - Google Patents

半導體封裝中的重佈線層及其形成方法 Download PDF

Info

Publication number
TWI667762B
TWI667762B TW106113987A TW106113987A TWI667762B TW I667762 B TWI667762 B TW I667762B TW 106113987 A TW106113987 A TW 106113987A TW 106113987 A TW106113987 A TW 106113987A TW I667762 B TWI667762 B TW I667762B
Authority
TW
Taiwan
Prior art keywords
die
integrated circuit
section
package
conductive
Prior art date
Application number
TW106113987A
Other languages
English (en)
Other versions
TW201830635A (zh
Inventor
黃立賢
蘇安治
吳集錫
余振華
葉德強
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201830635A publication Critical patent/TW201830635A/zh
Application granted granted Critical
Publication of TWI667762B publication Critical patent/TWI667762B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H01L2224/11822—Applying permanent coating, e.g. in-situ coating by dipping, e.g. in a solder bath
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2405—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/8101—Cleaning the bump connector, e.g. oxide removal step, desmearing
    • H01L2224/81011—Chemical cleaning, e.g. etching, flux
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/81024—Applying flux to the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82106—Forming a build-up interconnect by subtractive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

一種示例封裝包括：第一積體電路晶粒；包封體，圍繞所述第一積體電路晶粒；導線，將第一導電介層窗電性連接至第二導電介層窗，所述導線包括第一區段以及第二區段，所述第一區段位於所述第一積體電路晶粒之上且具有第一寬度，所述第二區段位於所述第一積體電路晶粒之上且具有較所述第一寬度大的第二寬度，所述第二區段在所述第一積體電路晶粒與所述包封體之間的第一邊界之上延伸。

Description

半導體封裝中的重佈線層及其形成方法
本發明實施例是有關於一種半導體封裝中的重佈線層及其形成方法。
由於各種電子組件（例如電晶體、二極體、電阻器、電容器等）積體密度持續提高，半導體行業經歷了快速發展。在很大程度上，積體密度提高肇因於最小特徵尺寸（minimum feature size）的重複減小，使得更多組件能夠被整合於特定區域中。隨著縮小電子裝置需求之增長，更加需要更小且更具創造性的半導體晶粒封裝技術。此種封裝系統的實例之一即為堆疊式封裝（Package-on-Package，PoP）技術。在堆疊式封裝裝置中，頂部半導體封裝被堆疊於底部半導體封裝的頂部上，以提供高水準的積體及組件密度。堆疊式封裝技術一般而言能夠生產得到功能性增強且在印刷電路板（PCB）佔用覆蓋區域小的半導體裝置。
本發明實施例提供為一種封裝結構。所述結構包括：第一積體電路晶粒；包封體，圍繞所述第一積體電路晶粒；導線，將第一導電介層窗電性連接至第二導電介層窗，所述導線包括第一區段以及第二區段，所述第一區段位於所述第一積體電路晶粒之上且具有第一寬度，所述第二區段位於所述第一積體電路晶粒之上且具有較所述第一寬度大的第二寬度，所述第二區段在所述第一積體電路晶粒與所述包封體之間的第一邊界之上延伸。
本發明實施例提供為一種形成重佈線層的方法。所述方法包括：將第一積體電路晶粒包封於包封體中；在所述第一積體電路晶粒及所述包封體之上形成重佈線層（RDL），其中所述重佈線層包括第一導電介層窗以及導線，所述第一導電介層窗位於所述第一積體電路晶粒之上，所述導線將所述第一導電介層窗電性連接至第二導電介層窗，所述導線包括第一區段以及第二區段，所述第一區段位於所述第一積體電路晶粒之上且具有第一寬度，所述第二區段在所述第一積體電路晶粒與所述包封體之間的邊界之上延伸，所述第二區段具有較所述第一寬度大的第二寬度。
本發明實施例提供為一種形成封裝之方法。所述方法包括形成第一封裝，所述形成所述第一封裝包括：在載體基底之上形成電性連接件；將第一晶粒及第二晶粒貼合至所述載體基底，所述電性連接件自所述第一晶粒的後側延伸至所述第一晶粒的主動側，所述主動側與所述後側彼此相對，所述電性連接件相鄰於所述第一晶粒及所述第二晶粒；以模製化合物包封所述第一晶粒及所述電性連接件；以及形成重佈線結構，所述重佈線結構上覆於所述第一晶粒的所述主動側及所述第二晶粒的主動側以及所述模製化合物上。所述形成所述重佈線結構包括：在所述第一晶粒的所述主動側之上形成第一導電介層窗；在所述第二晶粒的所述主動側之上形成第二導電介層窗；以及形成將所述第一導電介層窗電性連接至所述第二導電介層窗的導線，所述導線包括第一區段、第二區段、及第三區段，所述第一區段位於所述第一晶粒之上並具有第一寬度，所述第二區段在所述第一晶粒與所述模製化合物之間的第一邊界之上延伸且在所述第二晶粒與所述模製化合物之間的第二邊界之上延伸，所述第二區段具有較所述第一寬度大的第二寬度，所述第三區段位於所述第二晶粒之上且具有較所述第二寬度小的第三寬度。
以下揭露內容提供用於實現本發明的不同特徵的諸多不同的實施例或實例。以下闡述組件及排列的具體實例以簡化本揭露內容。當然，該些僅為實例且不旨在進行限制。舉例而言，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本揭露內容可能在各種實例中重複參考編號及/或字母。此種重複是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「之下（beneath）」、「下面（below）」、「下部的（lower）」、「上方（above）」、「上部的（upper）」等空間相對性用語來闡述圖中所示的一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外亦囊括裝置在使用或操作中的不同定向。所述裝置可具有其他定向（旋轉90度或處於其他定向）且本文中所用的空間相對性描述語可同樣相應地進行解釋。
本文所論述的實施例可在特定上下文中進行論述，即在包括能夠使半導體-包封體邊界（例如矽/模製化合物（silicon/molding compound，Si/MC）邊界）處的可靠性穩健度提高之重佈線層佈線設計（redistribution layer (RDL) routing design）的封裝結構之上下文中進行論述。所述封裝結構可包括扇出型封裝或扇入型封裝且可包括一或多個重佈線層。舉例而言，將晶圓形式之封裝自室溫加熱至220攝氏度（℃）會因熱膨脹係數（coefficient of thermal expansion，CTE）不匹配所造成的曲度變化而在半導體-包封體邊界處的重佈線層上造成高的彎曲應力(bending stresses)。所述半導體可為晶粒/晶片。傳遞跨越此一邊界的應力可使重佈線層破裂。因此，在某些實施例中，重佈線層佈線設計可根據此熱膨脹係數不匹配來進行配置且可用於提高可靠性穩健度及減少製造缺陷。在某些實施例中，橫跨半導體-包封體邊界且與半導體-包封體邊界相距預定距離內的重佈線層可被製作成寬於正常的重佈線層，以使其較不易於破裂。此外，重佈線層可在所述邊界外及距所述邊界為預定距離之外具有正常寬度，使得重佈線層較寬的跡線沒有佈線障礙(routing penalty)。
此外，本發明的教示內容適用於任何包括橫跨於具有不同熱膨脹係數的不同材料之上的一或多個導電層的封裝結構。其他實施例慮及其他應用，例如藉由閱讀本揭露內容而將對此項技術中具有通常知識者顯而易見的不同封裝類型或不同配置。應注意，本文所論述的實施例可能未必說明結構中可存在的每個組件或特徵。舉例而言，例如當對一個組件的論述可足以傳達實施例的各個態樣時，可自圖中省略多個所述組件。此外，本文所論述的方法實施例可被論述成以特定次序執行；然而，其他方法實施例可以任何邏輯次序執行。
圖1至圖15說明根據某些實施例的在形成第一封裝結構的製程期間的各中間步驟的剖視圖。圖1說明載體基底100及形成在載體基底100上的剝離層102。將分別說明用於形成第一封裝及第二封裝的第一封裝區600及第二封裝區602。
載體基底100可為玻璃載體基底、陶瓷載體基底等。載體基底100可為晶圓，進而使得可同時在載體基底100上形成多個封裝。剝離層102可由聚合物系材料形成，所述聚合物系材料可與載體基底100一起自將在後續步驟中形成的上覆結構被移除。在某些實施例中，剝離層102為當受熱時會失去其黏合性質的環氧樹脂系熱釋放材料，例如光熱轉換（light-to-heat-conversion，LTHC）釋放塗層。在其他實施例中，剝離層102可為當暴露至紫外光（UV）時會失去其黏合性質的紫外光膠。剝離層102可為液體形態被分配並固化，可為層壓至載體基底100上的層壓膜（laminate film）或可為類似材料。剝離層102的頂表面可被整平且可具有高共面程度（degree of coplanarity）。
參見圖2，形成介電層104及金屬化圖案106。如圖2所示，在剝離層102上形成介電層104。介電層104的底表面可接觸剝離層102的頂表面。在某些實施例中，介電層104是由例如聚苯並噁唑（polybenzoxazole，PBO）、聚醯亞胺、苯並環丁烯（benzocyclobutene，BCB）等聚合物形成。在其他實施例中，介電層104是由以下材料形成：氮化物，例如氮化矽；氧化物，例如氧化矽、磷矽酸鹽玻璃（phosphosilicate glass，PSG）、硼矽酸鹽玻璃（borosilicate glass，BSG）、摻雜硼的磷矽酸鹽玻璃（boron-doped phosphosilicate glass，BPSG）等；或者類似材料。介電層104可藉由任何可接受的沈積製程來形成，例如旋轉塗佈（spin coating）、化學氣相沈積（chemical vapor deposition，CVD）、層壓、類似製程或其組合等。
在介電層104上形成金屬化圖案106。作為形成金屬化圖案106的實例，在介電層104之上形成晶種層（圖中未示出）。在某些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在某些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沈積（physical vapor deposition，PVD）等來形成晶種層。接著在晶種層上形成光阻並將所述光阻圖案化。可藉由旋轉塗佈等來形成光阻且可將所述光阻暴露於光線以進行圖案化。光阻的圖案對應於金屬化圖案106。所述圖案化會形成貫穿光阻的開口以暴露出晶種層。在光阻的開口中及在晶種層的暴露出的部分上形成導電材料。可藉由鍍覆（例如電鍍或無電電鍍）等來形成所述導電材料。所述導電材料可包括金屬，如銅、鈦、鎢、鋁等。接著，移除光阻以及其上未形成有導電材料的晶種層部分。可藉由例如使用氧電漿等可接受的灰化製程（ashing process）或剝除製程（stripping process）來移除光阻。一旦光阻被移除，則例如使用可接受的蝕刻製程（例如藉由濕式蝕刻或乾式蝕刻）來移除晶種層的暴露出的部分。晶種層的剩餘部分與導電材料形成金屬化圖案106。
圖3中，在金屬化圖案106及介電層104上形成介電層108。在某些實施例中，介電層108是由聚合物形成，所述聚合物可為可使用光微影罩幕進行圖案化的感光性材料（例如聚苯並噁唑、聚醯亞胺、苯並環丁烯等）。在其他實施例中，介電層108是由以下材料形成：氮化物，例如氮化矽；氧化物，例如氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃；或者類似材料。可藉由旋轉塗佈、層壓、化學氣相沈積等或其組合來形成介電層108。接著將介電層108圖案化以形成開口來暴露出金屬化圖案106的部分。所述圖案化可透過可接受的製程來進行，例如在介電層為感光性材料時將介電層108暴露至光線或者藉由使用例如非等向性蝕刻（anisotropic etch）進行蝕刻而圖案化。
可將介電層104及108以及金屬化圖案106稱作後側重佈線結構110。如圖所示，後側重佈線結構110包括所述兩個介電層104及108以及一個金屬化圖案106。在其他實施例中，後側重佈線結構110可包括任何數目的介電層、金屬化圖案及介層窗。可藉由重複進行形成金屬化圖案106及介電層108的製程而在後側重佈線結構110中形成一或多個額外金屬化圖案及介電層。可在形成金屬化圖案期間藉由在下方介電層的開口中形成金屬化圖案的晶種層及導電材料來形成介層窗。因此介層窗可與各種金屬化圖案進行互連及電性耦合。
此外，在圖3中，形成貫穿式介層窗（through via）112。作為形成貫穿式介層窗112的實例，在後側重佈線結構110（例如，如圖所示的介電層108以及金屬化圖案106暴露出來的部分）之上形成晶種層。在某些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在某些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沈積等來形成晶種層。在晶種層上形成光阻並將所述光阻圖案化。可藉由旋轉塗佈等來形成光阻且可將所述光阻暴露至光線以進行圖案化。光阻的圖案對應於貫穿式介層窗。所述圖案化會形成貫穿光阻的開口以暴露出晶種層。在光阻的開口中及在晶種層的暴露出的部分上形成導電材料。可藉由鍍覆（例如電鍍或無電電鍍）等來形成導電材料。所述導電材料可包括金屬，如銅、鈦、鎢、鋁等。移除光阻以及晶種層的上面未形成有導電材料的部分。可藉由例如使用氧電漿等可接受的灰化製程或剝除製程來移除光阻。一旦光阻被移除，則例如使用可接受的蝕刻製程（例如藉由濕式蝕刻或乾式蝕刻）來移除晶種層暴露的部分。晶種層的剩餘部分與導電材料形成貫穿式介層窗112。
在圖4中，藉由黏合劑116而將積體電路晶粒114黏附至介電層108。如圖4所示，在第一封裝區600及第二封裝區602中的每一者中黏附兩個積體電路晶粒114，且在其他實施例中，可在每一區中黏附更多或更少的積體電路晶粒114。舉例而言，在實施例中，可在每一區中黏附僅一個積體電路晶粒114。積體電路晶粒114可為邏輯晶粒（例如中央處理單元、微控制器等）、記憶體晶粒（例如動態隨機存取記憶體（dynamic random access memory，DRAM）晶粒、靜態隨機存取記憶體（static random access memory，SRAM）晶粒等）、電力管理晶粒（例如電力管理積體電路（power management integrated circuit，PMIC）晶粒）、射頻（radio frequency，RF）晶粒、感測器晶粒、微機電系統（micro-electro-mechanical-system，MEMS）晶粒、訊號處理晶粒（例如數位訊號處理（digital signal processing，DSP）晶粒）、前端晶粒（例如類比前端（analog front-end，AFE）晶粒）等或其組合。此外，在某些實施例中，積體電路晶粒114可為不同尺寸（例如，不同高度及/或表面積），且在其他實施例中，積體電路晶粒114可為相同尺寸（例如，相同高度及/或表面積）。
在將積體電路晶粒114黏附至介電層108之前，可根據適用於在積體電路晶粒114中形成積體電路的製造製程來加工積體電路晶粒114。舉例而言，積體電路晶粒114各自包括半導體基底118，例如經摻雜或未經摻雜的矽、或絕緣層上半導體（semiconductor-on-insulator，SOI）基底的主動層。半導體基底可包含例如以下等其他半導體材料：鍺；化合物半導體，包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或者其組合。亦可使用例如多層式基底或梯度基底（gradient substrate）等其他基底。可在半導體基底118中及/或半導體基底118上形成例如電晶體、二極體、電容器、電阻器等裝置且可透過由例如位於半導體基底118上的一或多個介電層中的金屬化圖案形成的互連結構120而使各所述裝置互連以形成積體電路。
積體電路晶粒114更包括與外部連接的墊122（例如鋁墊）。墊122位於可被稱作積體電路晶粒114的相應主動側的位置上。積體電路晶粒114上及墊122的部分上具有保護膜124。具有貫穿保護膜124而到達墊122的開口。在貫穿保護膜124的開口中具有例如導電柱（例如包含例如銅等金屬）等晶粒連接件126，且晶粒連接件126機械地且電性地耦合至相應墊122。可藉由例如電鍍等來形成晶粒連接件126。晶粒連接件126電性耦合積體電路晶粒114的相應積體電路。
在積體電路晶粒114的主動側上、例如在保護膜124及晶粒連接件126上形成介電材料128。介電材料128橫向地包封晶粒連接件126，且介電材料128橫向地鄰接相應積體電路晶粒114。介電材料128可為例如聚苯並噁唑、聚醯亞胺、苯並環丁烯等聚合物、例如氮化矽等氮化物、例如氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃等氧化物、類似材料或者其組合，且可例如藉由旋轉塗佈、層壓、化學氣相沈積等來形成。
黏合劑116位於積體電路晶粒114的後側上且將積體電路晶粒114黏附至後側重佈線結構110（例如示意圖中的介電層108）。黏合劑116可為任何適合的黏合劑、環氧樹脂、晶粒貼合膜（die attach film，DAF）等。可將黏合劑116施加至積體電路晶粒114的後側，例如施加至相應半導體晶圓的後側或可施加於載體基底100的表面之上。可例如藉由鋸切或切割而將積體電路晶粒114單體化，並使用例如拾取及放置工具（pick-and-place tool）藉由黏合劑116而將積體電路晶粒114黏附至介電層108。
在圖5中，在各個組件上形成包封體130。包封體130可為模製化合物、環氧樹脂等，且可藉由壓縮模製（compression molding）、轉移模製（transfer molding）等來施加。在固化之後，包封體130可經歷研磨製程（grinding process）以暴露出貫穿式介層窗112及晶粒連接件126。貫穿式介層窗112的頂表面、晶粒連接件126的頂表面及包封體130的頂表面在研磨製程之後是共面的。在某些實施例中，例如若已暴露出貫穿式介層窗112及晶粒連接件126，則可省略研磨。
在圖6至圖15及圖19中，形成前側重佈線結構160。如將在圖19中說明，前側重佈線結構160包括介電層132、140、148及156、以及金屬化圖案138、146及154。
在圖6中，在包封體130、貫穿式介層窗112及晶粒連接件126上沈積介電層132。在某些實施例中，介電層132是由聚合物形成，所述聚合物可為可使用光微影罩幕而圖案化的感光性材料（例如聚苯並噁唑、聚醯亞胺、苯並環丁烯等）。在其他實施例中，介電層132是由以下材料形成：氮化物，例如氮化矽；氧化物，例如氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃；或者類似材料。可藉由旋轉塗佈、層壓、化學氣相沈積等或其組合來形成介電層132。
在圖7中，接著將介電層132圖案化。所述圖案化會形成開口以暴露出貫穿式介層窗112的部分及晶粒連接件126的部分。所述圖案化可透過可接受的製程來進行，例如藉由在介電層132為感光性材料時將介電層132暴露至光線或者透過使用例如非等向性蝕刻以蝕刻進行所述圖案化。若介電層132為感光性材料，則可在所述曝光之後將介電層132顯影。
在圖8中，在介電層132上形成具有介層窗的金屬化圖案138。作為形成金屬化圖案138的實例，在介電層132之上及貫穿介電層132的開口中形成晶種層（圖中未示出）。在某些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在某些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沈積等來形成晶種層。接著在晶種層上形成光阻並將所述光阻圖案化。可藉由旋轉塗佈等來形成光阻且可將所述光阻暴露至光以進行圖案化。光阻的圖案對應於金屬化圖案138。所述圖案化會形成貫穿光阻的開口以暴露出晶種層。在光阻的開口中及在晶種層的暴露出的部分上形成導電材料。可藉由鍍覆（例如電鍍或無電電鍍）等來形成導電材料。所述導電材料可包括金屬，如銅、鈦、鎢、鋁等。接著，移除光阻以及晶種層的上面未形成有導電材料的部分。可藉由例如使用氧電漿等可接受的灰化製程或剝除製程來移除光阻。一旦光阻被移除，則例如使用可接受的蝕刻製程（例如藉由濕式蝕刻或乾式蝕刻）來移除晶種層的暴露出的部分。晶種層的剩餘部分與導電材料形成金屬化圖案138及介層窗。在貫穿介電層132而到達例如貫穿式介層窗112及/或晶粒連接件126的開口中形成所述介層窗。
在圖9中，在金屬化圖案138及介電層132上沈積介電層140。在某些實施例中，介電層140是由聚合物形成，所述聚合物可為可使用光微影罩幕進行圖案化的感光性材料（例如聚苯並噁唑、聚醯亞胺、苯並環丁烯等）。在其他實施例中，介電層140是由以下材料形成：氮化物，例如氮化矽；氧化物，例如氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃；或者類似材料。可藉由旋轉塗佈、層壓、化學氣相沈積等或其組合來形成介電層140。
在圖10中，接著將介電層140圖案化。所述圖案化會形成開口以暴露出金屬化圖案138的部分。所述圖案化可藉由可接受的製程，例如在所述介電層為感光性材料時將介電層140暴露至光線或者藉由使用例如非等向性蝕刻進行蝕刻而圖案化。若介電層140為感光性材料，則可在所述曝光之後將介電層140顯影。
在圖11中，在介電層140上形成具有介層窗的金屬化圖案146。作為形成金屬化圖案146的實例，在介電層140之上及在貫穿介電層140的開口中形成晶種層（圖中未示出）。在某些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在某些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沈積等來形成晶種層。接著在晶種層上形成光阻並將所述光阻圖案化。可藉由旋轉塗佈等來形成光阻且可將所述光阻暴露至光線以進行圖案化。光阻的圖案對應於金屬化圖案146。所述圖案化會形成貫穿光阻的開口以暴露出晶種層。在光阻的開口中以及在晶種層的暴露出的部分上形成導電材料。可藉由鍍覆（例如電鍍或無電電鍍）等來形成所述導電材料。所述導電材料可包括金屬，如銅、鈦、鎢、鋁等。接著，移除光阻以及晶種層上未形成有導電材料的部分。可藉由例如使用氧電漿等可接受的灰化製程或剝除製程來移除光阻。一旦光阻被移除，則例如使用可接受的蝕刻製程（例如藉由濕式蝕刻或乾式蝕刻）來移除晶種層的暴露出的部分。晶種層的剩餘部分與導電材料形成金屬化圖案146及介層窗。在貫穿介電層140而到達例如金屬化圖案138的部分的開口中形成所述介層窗。
在圖12中，在金屬化圖案146及介電層140上沈積介電層148。在某些實施例中，介電層148是由聚合物形成，所述聚合物可為可使用光微影罩幕進行圖案化的感光性材料（例如聚苯並噁唑、聚醯亞胺、苯並環丁烯等）。在其他實施例中，介電層148是由以下材料形成：氮化物，例如氮化矽；氧化物，例如氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃；或者類似材料。可藉由旋轉塗佈、層壓、化學氣相沈積等或其組合來形成介電層148。
在圖13中，接著將介電層148圖案化。所述圖案化會形成開口以暴露出金屬化圖案146的部分。所述圖案化可藉由可接受的製程來進行，例如在所述介電層為感光性材料時將介電層148暴露至光線或者藉由使用例如非等向性蝕刻進行蝕刻而圖案化。若介電層148為感光性材料，則可在所述曝光之後將介電層148顯影。
在圖14中，在介電層148上形成具有介層窗的金屬化圖案154。作為形成金屬化圖案154的實例，在介電層148之上及在貫穿介電層148的開口中形成晶種層（圖中未示出）。在某些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在某些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沈積等來形成晶種層。接著在晶種層上形成光阻並將所述光阻圖案化。可藉由旋轉塗佈等來形成光阻且可將所述光阻暴露至光以進行圖案化。光阻的圖案對應於金屬化圖案154。所述圖案化會形成貫穿光阻的開口以暴露出晶種層。在光阻的開口中及在晶種層的暴露出的部分上形成導電材料。可藉由鍍覆（例如電鍍或無電電鍍）等來形成所述導電材料。所述導電材料可包括金屬，如銅、鈦、鎢、鋁等。接著，移除光阻以及晶種層的上面未形成有導電材料的部分。可藉由例如使用氧電漿等可接受的灰化製程或剝除製程來移除光阻。一旦光阻被移除，則例如使用可接受的蝕刻製程（例如藉由濕式蝕刻或乾式蝕刻）來移除晶種層的暴露出的部分。晶種層的剩餘部分與導電材料形成金屬化圖案154及介層窗。在貫穿介電層148而到達例如金屬化圖案146部分的開口中形成所述介層窗。
在圖15中，在金屬化圖案154及介電層148上沈積介電層156。在某些實施例中，介電層156是由聚合物形成，所述聚合物可為可使用光微影罩幕進行圖案化的感光性材料（例如聚苯並噁唑、聚醯亞胺、苯並環丁烯等）。在其他實施例中，介電層156是由以下材料形成：氮化物，例如氮化矽；氧化物，例如氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃；或者類似材料。可藉由旋轉塗佈、層壓、化學氣相沈積等或其組合來形成介電層156。
圖16、圖17及圖18說明根據某些實施例的重佈線層佈線的簡化平面圖。圖16說明圖15所示第一封裝結構中的一者的簡化平面圖。圖16說明包封於包封體130中的兩個積體電路晶粒114A及114B。在實施例中，所述兩個積體電路晶粒114A及114B之間的距離D2可為約50微米（μm）至約300微米。在另一實施例中，所述兩個積體電路晶粒114A及114B之間的距離D2可為不同值。第一積體電路晶粒114A與包封體130之間共享第一邊界702A，且第二積體電路晶粒114B與包封體130之間共享第二邊界702B。
如由圖16所示，導線704及708在積體電路晶粒114A及114B與包封體130之間的邊界702A及702B之上延伸。導線704及708可將位於積體電路晶粒114A之上的導電介層窗706A及710A電性地且機械地連接至位於積體電路晶粒114B中及/或積體電路晶粒114B之上的導電介層窗706B及710B。如以上所論述，由於積體電路晶粒114A及114B的材料與包封體130的材料之間存在熱膨脹係數不匹配，因此裝置封裝可能在邊界702A及702B處出現曲度，此會對位於邊界702A及702B的位置處的導線704及708施加應力。已觀察到，可藉由將導線704及708在包封體130之上及在位於邊界702A及702B附近的積體電路晶粒114A及114B之上製作得更寬而使對導線704及708施加的此應力得到減弱。
在上覆的金屬化圖案154/146/138（重佈線層圖案）的導線704及708顯示出導線的兩種配置方式。導線704較短且其墊/介層窗比較靠近邊界702A及702B，而導線708較長且其墊/介層窗比較遠離邊界702A及702B。這使得相鄰導線704及708的墊/介層窗能夠更緊密地封裝於一起。導電介層窗706A、706B、710A及710B（例如，晶粒連接件126、貫穿式介層窗112及/或金屬化圖案154/146/138的介層窗）亦以虛線圖形繪示以供參考。圖中未示出介電層132、140、148及156。圖16所說明的平面圖的各種特徵是出於簡潔而以單層進行說明。在各種實施例中，根據圖15所示剖視圖，圖16中的特徵可安置於不同層中。此外，導線704及708可安置於封裝內的同一金屬化圖案中或不同金屬化圖案中。舉例而言，導線704可安置於導線708同一層內、其上方或下方。
導線704及708中的每一者分別包括至少一個較寬部分704B及708B，所述至少一個較寬部分704B及708B各自安置於包封體130之上以及在距邊界702A及702B第一距離D1內安置於積體電路晶粒114A及114B之上。導線704及708中的每一者可包括較窄部分704A及708A，所述較窄部分704A及708A比所述較寬部分窄，其位於處於第一距離D1外的積體電路晶粒114A及114B之上。在某些實施例中，較寬部分704B及708B具有大於或等於約5微米的寬度W2。在某些實施例中，較窄部分704A及708A具有小於或等於約2微米的寬度W1。在某些實施例中，第一距離D1大於或等於約10微米。在其他實施例中，寬度W1及W2以及所述第一距離可為不同的值，而寬度W2大於寬度W1。上述部分/區段的寬度是在垂直於所述部分/區段的縱向軸線的方向上量測。已觀察到以本文所述方式根據積體電路晶粒114A及/或114B與包封體130之間的熱膨脹係數不匹配來配置導線，則針對在晶粒/模製化合物邊界之上延伸的導線之應力可顯著減小。藉由減小施加至導線的應力，可減少重佈線層的金屬化圖案中的裂開及/或其他製造缺陷。此外，藉由在墊/介層窗區中提供較窄部分704A及708A，具有較寬的導線所導致之佈線障礙將不顯著。
圖17說明重佈線層佈線的簡化平面圖，除了導線的較寬部分包括鈍角彎曲部以外，均與圖16所示重佈線層佈線相似。在圖17中，除較寬部分712B中的鈍角彎曲部以外，導線712以及介層窗714A及714B均與圖16所示導線704以及介層窗706A及706B相似，故本文中不再對其予以贅述。在圖17中，除較寬部分716B中的鈍角彎曲部以外，導線716以及介層窗718A及718B均與圖16所示導線708以及介層窗710A及710B相似，故本文中不再對其予以贅述。
導線712及716之較寬部分712B及716B中的鈍角彎曲部為具有角度θ1的彎曲部。在某些實施例中，如在較寬部分712B及/或716B的相應區段之間所量測，角度θ1可大於90°且小於180°。此外，導線以及導線區段與邊界702A及702B之間的角度純粹為說明性的，且導線區段可被安置成呈一定角度跨越邊界702A及702B。
圖18說明重佈線層佈線的簡化平面圖，除了導線的較寬部分包括銳角彎曲部以外，均與圖16所示重佈線層佈線相似。在圖18中，除較寬部分720B中的銳角彎曲部以外，導線720以及介層窗722A及722B均與圖16所示導線704以及介層窗706A及706B相似，故本文中不再對其予以贅述。在圖18中，除較寬部分724B中的銳角彎曲部以外，導線724以及介層窗726A及726B均與圖16所示導線708以及介層窗710A及710B相似，故本文中不再對其予以贅述。
導線720及724的較寬部分720B及724B中的銳角彎曲部為具有角度θ2的彎曲部。在某些實施例中，如在較寬部分720B及/或724B的相應區段之間所量測，角度θ2可小於90°且大於0°。此外，導線以及導線區段與邊界702A及702B之間的角度純粹為說明性的，且導線區段可被安置成呈一定角度跨越邊界702A及702B。在某些實施例中，較寬部分的區段之間的角度為直角，例如為約90°。
在圖16、圖17及圖18中，導電介層窗706B、710B、714B、718B、722B及726B安置於積體電路晶粒114B之上或積體電路晶粒114B中。在其他實施例中，導電介層窗706B、710B、714B、718B、722B及726B可安置於包封體130之上或包封體130中，進而使得在積體電路晶粒114A與包封體130之間僅具有一個邊界702。
在某些實施例中，上述重佈線層佈線設計技術僅適用於上覆於積體電路晶粒114及包封體130上的第一金屬化圖案（例如，金屬化圖案138），其餘金屬化圖案則不根據圖16及圖17中所述配置進行佈線。在某些其他實施例中，上述重佈線層佈線設計技術適用於所有上覆於積體電路晶粒114及包封體130上的金屬化圖案（例如，金屬化圖案138、146及154）。
圖19至圖24說明根據某些實施例在進一步形成第一封裝及將其他封裝結構貼合至所述第一封裝的製程期間各中間步驟的剖視圖。
在圖19中，接著將介電層156圖案化。所述圖案化會形成開口以暴露出金屬化圖案154的部分。所述圖案化可藉由可接受的製程來進行，例如在介電層為感光性材料時將介電層156暴露至光線或者藉由使用例如非等向性蝕刻進行蝕刻而圖案化。若介電層156為感光性材料，則可在所述曝光之後將介電層156顯影。
所顯示前側重佈線結構160僅作為示例。可在前側重佈線結構160中形成更多或更少的介電層及金屬化圖案。若欲形成更少的介電層及金屬化圖案，則可省略以上所論述的步驟及製程。若欲形成更多的介電層及金屬化圖案，則可重複以上所論述的步驟及製程。此項技術中具有通常知識者將易於理解哪些步驟及製程將被省略或重複進行。
儘管本文所述重佈線層佈線設計是針對前側重佈線結構160來論述，然而重佈線層佈線製程的教示內容亦可適用於後側重佈線結構110。
在圖20中，在前側重佈線結構160的外側上形成墊162。墊162用於耦合至導電連接件166（參見圖21）且可被稱作凸塊下金屬（under bump metallurgy，UBM）162。在所示實施例中，經由貫穿介電層156而到達金屬化圖案154的開口來形成墊162。作為形成墊162的實例，在介電層156之上形成晶種層（圖中未示出）。在某些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在某些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沈積等來形成晶種層。接著在晶種層上形成光阻並將所述光阻圖案化。可藉由旋轉塗佈等來形成光阻且可將所述光阻暴露至光線以進行圖案化。光阻的圖案對應於墊162。所述圖案化會形成貫穿光阻的開口以暴露出晶種層。在光阻的開口中及在晶種層的暴露出的部分上形成導電材料。可藉由鍍覆（例如電鍍或無電電鍍）等來形成導電材料。所述導電材料可包括金屬，如銅、鈦、鎢、鋁等。接著，移除光阻以及晶種層的上面未形成有導電材料的部分。可藉由例如使用氧電漿等可接受的灰化製程或剝除製程來移除光阻。一旦光阻被移除，則例如使用可接受的蝕刻製程（例如藉由濕式蝕刻或乾式蝕刻）來移除晶種層的暴露出的部分。晶種層的剩餘部分與導電材料形成墊162。在其中以不同方式形成墊162的實施例中，可利用更多的光阻及圖案化步驟。
在圖21中，在凸塊下金屬162上形成導電連接件166。導電連接件166可為球柵陣列封裝（ball grid array，BGA）連接件、焊球、金屬柱、受控塌陷晶片連接（controlled collapse chip connection，C4）凸塊、微凸塊、化學鍍鎳鈀浸金技術（electroless nickel-electroless palladium-immersion gold technique，ENEPIG）形成的凸塊等。導電連接件166可包含導電材料，例如焊料、銅、鋁、金、鎳、銀、鈀、錫等或其組合。在某些實施例中，藉由以下方式來形成導電連接件166：首先利用例如蒸鍍、電鍍、印刷、焊料轉移（solder transfer）、植球（ball placement）等常用方法形成焊料層。一旦已在所述結構上形成焊料層，則可執行迴焊（reflow）以將所述材料造型成所期望凸塊形狀。在另一實施例中，導電連接件166為藉由濺鍍、印刷、電鍍、無電電鍍、化學氣相沈積等而形成的金屬柱（例如銅柱）。所述金屬柱可無焊料且具有實質上垂直的側壁。在某些實施例中，在金屬柱連接件166的頂部上形成金屬頂蓋層（圖中未示出）。金屬頂蓋層可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金等或其組合且可藉由電鍍製程來形成。
在圖22中，執行載體基底剝離（carrier substrate de-bonding）以將載體基底100自後側重佈線結構（例如，介電層104）分離（剝離）。根據某些實施例，所述剝離包括在剝離層102上投射例如雷射光或紫外光等光，以使得剝離層102在所述光線的熱量作用下分解，且可移除載體基底100。接著將所述結構翻轉並放置於膠帶190上。
如圖22中進一步說明，經由介電層104形成開口以暴露出金屬化圖案106的部分。可例如使用雷射鑽孔（laser drilling）、蝕刻等來形成開口。
藉由沿切割道區（例如，在相鄰的區600與602之間）鋸切來執行單體化製程（singulation process）。所述鋸切將第一封裝區600自第二封裝區602單體化。
圖23說明可來自第一封裝區600或第二封裝區602中的一者的所得經單體化的封裝200。封裝200亦可被稱作積體扇出型（integrated fan-out，InFO）封裝200。
圖24說明包括封裝200（可被稱作第一封裝200）、第二封裝300及基底400的封裝結構500。第二封裝300包括基底302及耦合至基底302的一或多個經堆疊晶粒308（308A及308B）。基底302可由例如矽、鍺、金剛石等半導體材料製成。在某些實施例中，亦可使用例如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化砷化鎵（gallium arsenic phosphide）、磷化鎵銦、其組合等化合物材料。另外，基底302可為絕緣層上矽（silicon-on-insulator，SOI）基底。一般而言，絕緣層上矽基底包括例如磊晶矽、鍺、矽鍺、絕緣層上矽、絕緣層上矽鍺（silicon germanium on insulator，SGOI）或其組合等半導體材料的層。在一個替代性實施例中，基底302是基於例如經玻璃纖維強化的樹脂芯體等絕緣芯體。一種示例性芯體材料為玻璃纖維樹脂（例如FR4）。所述芯體材料的替代材料包括雙馬來醯亞胺三嗪（bismaleimide-triazine，BT）樹脂，或者作為另一選擇，為其他印刷電路板（printed circuit board，PCB）材料或膜。可對基底302使用例如味之素增層膜（Ajinomoto build-up film，ABF）等增層膜或其他層壓膜。
基底302可包括主動裝置及被動裝置（圖24中未示出）。如此技術中具有通常知識者將理解，可使用例如電晶體、電容器、電阻器、其組合等各種各樣的裝置來產生半導體封裝300的設計的結構性要求及功能性要求。可使用任何適合的方法來形成所述裝置。
基底302亦可包括金屬化層（圖中未示出）及貫穿式介層窗306。金屬化層可形成在主動裝置及被動裝置之上並被設計成連接各種裝置以形成功能性電路系統。金屬化層可由交錯的介電質（例如低介電常數(low-k)介電材料）層及導電材料（例如銅）層形成且可藉由任何適合的製程（例如沈積、鑲嵌、雙鑲嵌等）來形成，其中由介層窗對各層導電材料進行互連。在某些實施例中，基底302實質上無主動裝置及被動裝置。
基底302可具有位於基底302的第一側上的結合墊303以耦合至堆疊晶粒308，並具有位於基底302的第二側上的結合墊304以耦合至導電連接件314，基底302的第二側與第一側相對。在某些實施例中，藉由在基底302的第一側及第二側上的介電層（圖中未示出）中形成凹陷（圖中未示出）來形成結合墊303及304。所述凹陷可被形成為使得結合墊303及304能夠嵌置於介電層中。在其他實施例中，由於可在介電層上形成結合墊303及304，因此省略所述凹陷。在某些實施例中，結合墊303及304包括由銅、鈦、鎳、金、鈀等或其組合製成的薄晶種層（圖中未示出）。可在所述薄晶種層之上沈積結合墊303及304的導電材料。可藉由電化學電鍍製程（electro-chemical plating process）、無電電鍍製程、化學氣相沈積、原子層沈積（atomic layer deposition，ALD）、物理氣相沈積等或其組合來形成所述導電材料。在實施例中，結合墊303及304的導電材料為銅、鎢、鋁、銀、金等或其組合。
在實施例中，結合墊303及304為包含三個導電材料層（例如鈦層、銅層及鎳層）的凸塊下金屬。然而，此項技術中具有通常知識者將認識到，有諸多適合的材料及層的排列（例如為鉻/鉻-銅合金/銅/金的排列、為鈦/鈦鎢/銅的排列、或為銅/鎳/金的排列）適合於形成凸塊下金屬303及304。可用於凸塊下金屬303及304的任何適合的材料或材料層全部旨在包含於本申請案的範圍內。在某些實施例中，貫穿式介層窗306延伸貫穿基底302且將至少一個結合墊303耦合至至少一個結合墊304。
在所示實施例中，儘管可使用其他連接體（例如導電凸塊），然而藉由導線接合件310將經堆疊晶粒308耦合至基底302。在實施例中，經堆疊晶粒308為經堆疊記憶體晶粒。舉例而言，經堆疊記憶體晶粒308可包括低功率（low-power）雙倍資料速率（double data rate，DDR）記憶體模組，例如LPDDR1、LPDDR2、LPDDR3、LPDD4或類似的記憶體模組。
在某些實施例中，可藉由模製材料312來包封經堆疊晶粒308及導線結合件310。可例如使用壓縮模製將模製材料312模製於經堆疊晶粒308及導線結合件310上。在某些實施例中，模製材料312為模製化合物、聚合物、環氧樹脂、氧化矽填充材料等或其組合。可執行固化步驟以固化模製材料312，其中所述固化可為熱固化、紫外固化等或其組合。
在某些實施例中，將經堆疊晶粒308及導線結合件310埋置於模製材料312中，且在模製材料312固化之後，執行平坦化步驟（例如研磨）以移除模製材料312的多餘部分並為第二封裝300提供實質上平坦的表面。
在形成第二封裝300之後，經由導電連接件314、結合墊304及金屬化圖案106而將封裝300結合至第一封裝200。在某些實施例中，可經由導線結合件310、結合墊303及304、貫穿式介層窗306、導電連接件314及貫穿式介層窗112而將經堆疊記憶體晶粒308耦合至積體電路晶粒114。
儘管導電連接件314及116無需為相同的，然而導電連接件314可相似於上述導電連接件166且本文中不再對其予以贅述。在某些實施例中，在結合導電連接件314之前，以例如免清洗焊劑（no-clean flux）等焊劑（圖中未示出）塗佈導電連接件314。可將導電連接件314浸入焊劑中或可將所述焊劑噴射至導電連接件314上。在另一實施例中，可將焊劑施加至金屬化圖案106的表面。
在某些實施例中，在導電連接件314被迴焊之前導電連接件314上可形成有環氧樹脂焊劑（圖中未示出），所述環氧樹脂焊劑的環氧樹脂部分中的至少某些環氧樹脂部分將在第二封裝300貼合至第一封裝200之後存留。此一存留的環氧樹脂部分可充當底部填充物以減小應力並保護因迴焊導電連接件314而形成的接頭。在某些實施例中，可在第二封裝300與第一封裝200之間且環繞導電連接件314形成底部填充物（圖中未示出）。可在貼合第二封裝300之後藉由毛細流動製程（capillary flow process）來形成底部填充物或者可在貼合第二封裝300之前藉由適合的沈積方法來形成所述底部填充物。
第二封裝300與第一封裝200之間的結合可為焊料結合或直接的金屬對金屬（例如銅對銅或錫對錫）結合。在實施例中，藉由迴焊製程將第二封裝300結合至第一封裝200。在此迴焊製程期間，導電連接件314接觸結合墊304及金屬化圖案106以將第二封裝300實體地且電性地耦合至第一封裝200。在結合製程之後，可在金屬化圖案106與導電連接件314的介面處且亦在導電連接件314與結合墊304（圖中未示出）之間的介面處形成介金屬化合物（intermetallic compound，IMC）（圖中未示出）。
半導體封裝500包括安裝至基底400的封裝200及300。基底400可被稱為封裝基底400。使用導電連接件166將封裝200安裝至封裝基底400。
封裝基底400可由例如矽、鍺、金剛石等半導體材料製成。作為另一選擇，亦可使用例如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化砷化鎵、磷化鎵銦、其組合等化合物材料。另外，封裝基底400可為絕緣層上矽基底。一般而言，絕緣層上矽基底包括例如磊晶矽、鍺、矽鍺、絕緣層上矽、絕緣層上矽鍺或其組合等半導體材料的層。在一個替代性實施例中，封裝基底400是基於例如被玻璃纖維強化的樹脂芯體等絕緣芯體。一種示例性芯體材料為玻璃纖維樹脂（例如FR4）。所述芯體材料的替代材料包括雙馬來醯亞胺三嗪BT樹脂，或者作為另一選擇，為其他印刷電路板材料或膜。可對封裝基底400使用例如味之素增層膜等增層膜或其他層壓膜。
封裝基底400可包括主動裝置及被動裝置（圖24中未示出）。如此項技術中具有通常知識者將認識到，可使用例如電晶體、電容器、電阻器、其組合等各種各樣的裝置來產生半導體封裝500的設計的結構性要求及功能性要求。可使用任何適合的方法來形成所述裝置。
封裝基底400亦可包括金屬化層及介層窗（圖中未示出）以及位於所述金屬化層及介層窗之上的結合墊402。金屬化層可在主動裝置及被動裝置之上形成並被設計成連接各種裝置以形成功能性電路系統。金屬化層可由交錯的介電質（例如低介電常數介電材料）層及導電材料（例如銅）層形成且可藉由任何適合的製程（例如沈積、鑲嵌、雙鑲嵌等）來形成，其中由介層窗對各層導電材料進行互連。在某些實施例中，封裝基底400實質上無主動裝置及被動裝置。
在某些實施例中，可將導電連接件166迴焊以將封裝200貼合至結合墊402。導電連接件166將基底400（包括基底400中的金屬化層）電性地及/或實體地耦合至第一封裝200。
在對導電連接件166進行迴焊之前導電連接件166上可形成有環氧樹脂焊劑（圖中未示出），環氧樹脂焊劑的環氧樹脂部分中的至少某些環氧樹脂部分將在封裝300貼合至基底400之後存留。此一存留的環氧樹脂部分可充當底部填充物以減小應力並保護因迴焊導電連接件166而形成的接頭。在某些實施例中，可在第一封裝200與基底400之間且環繞導電連接件166形成底部填充物（圖中未示出）。可在貼合封裝200之後藉由毛細流動製程來形成底部填充物或者可在貼合封裝200之前藉由適合的沈積方法來形成所述底部填充物。
本發明中的裝置及方法的實施例具有諸多優點。具體而言，重佈線層（RDL）佈線設計能夠使半導體-包封體邊界（例如，矽/模製化合物（Si/MC）邊界）處的可靠性穩健度提高。舉例而言，將晶圓形式之封裝自室溫加熱至220℃會因熱膨脹係數不匹配所造成的曲度的急劇變化而在半導體-包封體邊界處的重佈線層上造成高彎曲應力。自扇入型區域至扇出型區域傳遞的應力可致使重佈線層在晶粒隅角及晶粒側邊處裂開。因此，在某些實施例中，可使用所述重佈線層佈線設計（參見圖16、圖17及圖18）來達成可靠性穩健度。
一個實施例提供一種封裝結構。所述結構包括：第一積體電路晶粒；包封體，圍繞所述第一積體電路晶粒；導線，將第一導電介層窗電性連接至第二導電介層窗，所述導線包括第一區段以及第二區段，所述第一區段位於所述第一積體電路晶粒之上且具有第一寬度，所述第二區段位於所述第一積體電路晶粒之上且具有較所述第一寬度大的第二寬度，所述第二區段在所述第一積體電路晶粒與所述包封體之間的第一邊界之上延伸。
在某些實施例中，其中所述第二區段包括第一彎曲部，所述第一彎曲部具有第一角度。所述第一角度大於約90°、小於約90°或大約為90°。
另一實施例提供一種形成重佈線層的方法。所述方法包括：將第一積體電路晶粒包封於包封體中；在所述第一積體電路晶粒及所述包封體之上形成重佈線層，其中所述重佈線層包括第一導電介層窗以及導線，所述第一導電介層窗位於所述第一積體電路晶粒之上，所述導線將所述第一導電介層窗電性連接至第二導電介層窗，所述導線包括第一區段以及第二區段，所述第一區段位於所述第一積體電路晶粒之上且具有第一寬度，所述第二區段在所述第一積體電路晶粒與所述包封體之間的邊界之上延伸，所述第二區段具有較所述第一寬度大的第二寬度。
又一實施例提供一種形成封裝之方法。所述方法包括形成第一封裝，所述形成所述第一封裝包括：在載體基底之上形成電性連接件；將第一晶粒及第二晶粒貼合至所述載體基底，所述電性連接件自所述第一晶粒的後側延伸至所述第一晶粒的主動側，所述主動側與所述後側彼此相對，所述電性連接件相鄰於所述第一晶粒及所述第二晶粒；以模製化合物包封所述第一晶粒及所述電性連接件；以及形成重佈線結構，所述重佈線結構上覆於所述第一晶粒的所述主動側及所述第二晶粒的主動側以及所述模製化合物上。所述形成所述重佈線結構包括：在所述第一晶粒的所述主動側之上形成第一導電介層窗；在所述第二晶粒的所述主動側之上形成第二導電介層窗；以及形成將所述第一導電介層窗電性連接至所述第二導電介層窗的導線，所述導線包括第一區段、第二區段及第三區段，所述第一區段位於所述第一晶粒之上並具有第一寬度，所述第二區段在所述第一晶粒與所述模製化合物之間的第一邊界之上延伸且在所述第二晶粒與所述模製化合物之間的第二邊界之上延伸，所述第二區段具有較所述第一寬度大的第二寬度，所述第三區段位於所述第二晶粒之上且具有較所述第二寬度小的第三寬度。
在某些實施例中，所述第二區段包括至少一個具有第一角度的彎曲部。在某些實施例中，形成所述第一封裝更包括：形成位於所述重佈線結構之上並電性耦合至所述重佈線結構的第一組導電連接件；以及移除所述載體基底。
以上概述了若干實施例的特徵，以使熟習此項技術者可更佳地理解本發明的各個態樣。熟習此項技術者應知，其可容易地使用本發明作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到，該些等效構造並不背離本發明的精神及範圍，而且他們可在不背離本發明的精神及範圍的條件下對其作出各種改變、代替及變更。
100‧‧‧載體基底
102‧‧‧剝離層
104、108、132、140、148、156‧‧‧介電層
106、138、146、154‧‧‧金屬化圖案
110‧‧‧後側重佈線結構
112‧‧‧貫穿式介層窗
114‧‧‧積體電路晶粒
114A‧‧‧第一積體電路晶粒
114B‧‧‧第二積體電路晶粒
116‧‧‧黏合劑
118‧‧‧半導體基底
120‧‧‧互連結構
122‧‧‧墊
124‧‧‧保護膜
126‧‧‧晶粒連接件
128‧‧‧介電材料
130‧‧‧包封體
160‧‧‧前側重佈線結構
162‧‧‧墊
166‧‧‧導電連接件
190‧‧‧膠帶
200‧‧‧第一封裝
300‧‧‧第二封裝
302‧‧‧基底
303、304‧‧‧結合墊
306‧‧‧貫穿式介層窗
308A、308B‧‧‧經堆疊晶粒
310‧‧‧導線接合件
312‧‧‧模製材料
314‧‧‧導電連接件
400‧‧‧基底
402‧‧‧結合墊
500‧‧‧半導體封裝
600‧‧‧第一封裝區
602‧‧‧第二封裝區
702A‧‧‧第一邊界
702B‧‧‧第二邊界
704、708、712、716、720、724‧‧‧導線
704A、708A‧‧‧較窄部分
704B、708B、712B、716B、720B、724B‧‧‧較寬部分
706A、706B、710A、710B、714A、714B、718B、722B、726B‧‧‧導電介層窗
718A、722A、726A‧‧‧介層窗
D1‧‧‧第一距離
D2‧‧‧距離
W1、W2‧‧‧寬度
θ1、θ2‧‧‧角度
結合附圖閱讀以下詳細說明，會最佳地理解本發明的各個態樣。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。 圖1至圖15描繪根據某些實施例在形成第一封裝結構製程期間的各中間步驟的剖視圖。 圖16至圖18描繪根據某些實施例導電層佈線的平面圖。 圖19至圖24描繪根據某些實施例在進一步形成第一封裝及將其他封裝結構貼合至所述第一封裝的製程期間的各中間步驟的剖視圖。

Claims (10)

  1. 一種封裝結構，包括： 第一積體電路晶粒； 包封體，圍繞所述第一積體電路晶粒； 導線，將第一導電介層窗電性連接至第二導電介層窗，所述導線包括： 第一區段，位於所述第一積體電路晶粒之上且具有第一寬度；以及 第二區段，位於所述第一積體電路晶粒之上且具有較所述第一寬度大的第二寬度，所述第二區段在所述第一積體電路晶粒與所述包封體之間的第一邊界之上延伸。
  2. 如申請專利範圍第1項所述的封裝結構，其中所述導線更包括第三區段，所述第三區段具有較所述第二寬度小的第三寬度，所述第二區段安置於所述第一區段與所述第三區段之間。
  3. 如申請專利範圍第1項所述的封裝結構，其中所述第二區段包括第一彎曲部。
  4. 如申請專利範圍第1項所述的封裝結構，其中所述第二導電介層窗延伸至所述包封體內或安置於所述包封體之上。
  5. 如申請專利範圍第1項所述的封裝結構，更包括與所述第一積體電路晶粒相鄰的第二積體電路晶粒，所述包封體安置於所述第一積體電路晶粒與所述第二積體電路晶粒之間，所述第二導電介層窗安置於所述第二積體電路晶粒之上。
  6. 一種形成重佈線層的方法，包括： 將第一積體電路晶粒包封於包封體中； 在所述第一積體電路晶粒及所述包封體之上形成重佈線層，其中所述重佈線層包括： 第一導電介層窗，位於所述第一積體電路晶粒之上；以及 導線，將所述第一導電介層窗電性連接至第二導電介層窗，所述導線包括： 第一區段，位於所述第一積體電路晶粒之上且具有第一寬度；以及 第二區段，在所述第一積體電路晶粒與所述包封體之間的邊界之上延伸，所述第二區段具有較所述第一寬度大的第二寬度。
  7. 如申請專利範圍第6項所述形成重佈線層的方法，其中所述第二導電介層窗延伸貫穿所述包封體、安置於所述包封體之上或者安置於第二積體電路晶粒之上。
  8. 如申請專利範圍第6項所述形成重佈線層的方法，其中所述第二區段包括第一彎曲部。
  9. 一種形成封裝之方法，包括： 形成第一封裝，包括： 在載體基底之上形成電性連接件； 將第一晶粒及第二晶粒貼合至所述載體基底，所述電性連接件自所述第一晶粒的後側延伸至所述第一晶粒的主動側，所述主動側相對於所述後側，所述電性連接件相鄰於所述第一晶粒及所述第二晶粒； 以模製化合物包封所述第一晶粒、所述第二晶粒及所述電性連接件；以及 形成重佈線結構，所述重佈線結構上覆於所述第一晶粒的所述主動側及所述第二晶粒的主動側以及所述模製化合物上，所述形成所述重佈線結構包括： 在所述第一晶粒的所述主動側之上形成第一導電介層窗； 在所述第二晶粒的所述主動側之上形成第二導電介層窗；以及 形成將所述第一導電介層窗電性連接至所述第二導電介層窗的導線，所述導線包括第一區段、第二區段及第三區段，所述第一區段位於所述第一晶粒之上並具有第一寬度，所述第二區段在所述第一晶粒與所述模製化合物之間的第一邊界之上延伸且在所述第二晶粒與所述模製化合物之間的第二邊界之上延伸，所述第二區段具有較所述第一寬度大的第二寬度，所述第三區段位於所述第二晶粒之上且具有較所述第二寬度小的第三寬度。
  10. 如申請專利範圍第9項所述形成封裝之方法，更包括： 使用第二組導電連接件將第二封裝結合至所述第一封裝，所述第二封裝鄰近所述第一晶粒的所述後側及所述第二晶粒的後側。
TW106113987A 2016-10-31 2017-04-26 半導體封裝中的重佈線層及其形成方法 TWI667762B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201662415210P 2016-10-31 2016-10-31
US62/415,210 2016-10-31
US15/396,208 US10304801B2 (en) 2016-10-31 2016-12-30 Redistribution layers in semiconductor packages and methods of forming same
US15/396,208 2016-12-30

Publications (2)

Publication Number Publication Date
TW201830635A TW201830635A (zh) 2018-08-16
TWI667762B true TWI667762B (zh) 2019-08-01

Family

ID=62020578

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106113987A TWI667762B (zh) 2016-10-31 2017-04-26 半導體封裝中的重佈線層及其形成方法

Country Status (4)

Country Link
US (1) US10304801B2 (zh)
KR (1) KR101993973B1 (zh)
CN (1) CN108010854B (zh)
TW (1) TWI667762B (zh)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
US9741620B2 (en) 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
US10879212B2 (en) 2017-05-11 2020-12-29 Invensas Bonding Technologies, Inc. Processed stacked dies
US10217720B2 (en) 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US20180374798A1 (en) 2017-06-24 2018-12-27 Amkor Technology, Inc. Semiconductor device having emi shielding structure and related methods
US10304697B2 (en) * 2017-10-05 2019-05-28 Amkor Technology, Inc. Electronic device with top side pin array and manufacturing method thereof
US11276676B2 (en) 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
US11158606B2 (en) 2018-07-06 2021-10-26 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
US11462419B2 (en) * 2018-07-06 2022-10-04 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US11158600B2 (en) * 2018-09-28 2021-10-26 Taiwan Semiconductor Manufacturing Co., Ltd. Lithography process for semiconductor packaging and structures resulting therefrom
US10665520B2 (en) * 2018-10-29 2020-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11183487B2 (en) * 2018-12-26 2021-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
KR20210104742A (ko) 2019-01-14 2021-08-25 인벤사스 본딩 테크놀로지스 인코포레이티드 접합 구조체
US10777518B1 (en) * 2019-05-16 2020-09-15 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of manufacturing the same
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11264359B2 (en) 2020-04-27 2022-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Chip bonded to a redistribution structure with curved conductive lines
KR20210152721A (ko) * 2020-06-09 2021-12-16 삼성전자주식회사 반도체 패키지
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
TWI734545B (zh) * 2020-07-03 2021-07-21 財團法人工業技術研究院 半導體封裝結構
US11670601B2 (en) 2020-07-17 2023-06-06 Taiwan Semiconductor Manufacturing Co., Ltd. Stacking via structures for stress reduction
KR20220014364A (ko) * 2020-07-23 2022-02-07 삼성전자주식회사 반도체 패키지
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
JP2022083468A (ja) * 2020-11-25 2022-06-06 ソニーグループ株式会社 半導体装置
CN112670194B (zh) * 2020-12-26 2023-05-23 上海韦尔半导体股份有限公司 一种芯片封装工艺及芯片封装结构

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201225210A (en) * 2010-12-06 2012-06-16 Stats Chippac Ltd Semiconductor device and method of forming high routing density interconnect sites on substrate
TW201227901A (en) * 2010-12-15 2012-07-01 Stats Chippac Ltd Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
TW201234680A (en) * 2010-11-02 2012-08-16 Dainippon Printing Co Ltd Led-element mounting lead frame, resin-attached lead frame, method of manufacturing semiconductor device, and semiconductor-element mounting lead frame

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
WO2013057867A1 (ja) * 2011-10-21 2013-04-25 パナソニック株式会社 半導体装置
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9318429B2 (en) 2014-03-31 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated structure in wafer level package
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US10177115B2 (en) 2014-09-05 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming
US10115647B2 (en) 2015-03-16 2018-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. Non-vertical through-via in package
TWI584425B (zh) * 2016-06-27 2017-05-21 力成科技股份有限公司 扇出型晶圓級封裝結構

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201234680A (en) * 2010-11-02 2012-08-16 Dainippon Printing Co Ltd Led-element mounting lead frame, resin-attached lead frame, method of manufacturing semiconductor device, and semiconductor-element mounting lead frame
TW201225210A (en) * 2010-12-06 2012-06-16 Stats Chippac Ltd Semiconductor device and method of forming high routing density interconnect sites on substrate
TW201227901A (en) * 2010-12-15 2012-07-01 Stats Chippac Ltd Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask

Also Published As

Publication number Publication date
KR20180048249A (ko) 2018-05-10
TW201830635A (zh) 2018-08-16
CN108010854B (zh) 2020-09-01
US20180122774A1 (en) 2018-05-03
CN108010854A (zh) 2018-05-08
KR101993973B1 (ko) 2019-06-27
US10304801B2 (en) 2019-05-28

Similar Documents

Publication Publication Date Title
TWI667762B (zh) 半導體封裝中的重佈線層及其形成方法
US11652063B2 (en) Semiconductor package and method of forming the same
US11508695B2 (en) Redistribution layers in semiconductor packages and methods of forming same
TWI690030B (zh) 半導體封裝及其形成方法
TWI713129B (zh) 半導體元件及其形成方法
KR102127796B1 (ko) 반도체 패키지 및 방법
TWI669785B (zh) 半導體封裝體及其形成方法
KR102060742B1 (ko) 패키지 구조물 및 그 형성 방법
KR102060624B1 (ko) 더미 커넥터를 구비한 반도체 패키지와 이를 형성하는 방법
TWI642157B (zh) 半導體封裝件及其形成方法
TWI685927B (zh) 封裝結構及其形成方法
TWI610412B (zh) 封裝結構及其形成方法
KR102108236B1 (ko) 반도체 패키지들 내의 금속화 패턴들 및 그 형성 방법들
US8889484B2 (en) Apparatus and method for a component package
US11158619B2 (en) Redistribution layers in semiconductor packages and methods of forming same
TWI724653B (zh) 半導體裝置及其形成方法
JP2022023830A (ja) 半導体パッケージにおける放熱及びその形成方法
TW202347678A (zh) 積體電路裝置