TWI734545B - 半導體封裝結構 - Google Patents
半導體封裝結構 Download PDFInfo
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Abstract
一種半導體封裝結構,其包括重佈線層結構、晶片、電子元件以及應力補償層。所述重佈線層結構具有相對的第一表面與第二表面。所述晶片設置於所述重佈線層結構的所述第一表面上,且與述重佈線層結構電性連接。所述電子元件設置於所述重佈線層結構中,與所述晶片電性連接,且包括設置於其中的介電層。所述應力補償層設置於所述重佈線層結構中或上。所述介電層在垂直於所述第二表面的第一方向上提供50 Mpa至200 Mpa之間的第一應力,所述應力補償層在與所述第一方向相反的第二方向上提供50 Mpa至200 Mpa之間的第二應力,且所述第一應力與所述第二應力之間的差不超過60 Mpa。
Description
本申請是有關於一種半導體封裝結構。
近年來,隨著電子產品的需求朝向高功能化、訊號傳輸高速化及電路元件高密度化,半導體相關產業也日漸發展。在半導體產業的半導體封裝製程中,一般會將晶片設置於重佈線層(redistribution layer,RDL)結構上,然後於重佈線層結構上形成包封體(encapsulant)來包封晶片,以形成半導體封裝結構。
此外,為了縮小半導體封裝結構的尺寸,可將某些主動元件或被動元件設置於重佈線層結構中。然而,對於具有高介電常數之介電層的主動元件或被動元件來說,介電層往往會產生張應力或壓應力,因而導致半導體封裝結構產生翹曲或捲曲的問題。
本申請提供一種半導體封裝結構,其具有設置於重佈線層結構中的應力補償層。
本申請的半導體封裝結構包括重佈線層結構、晶片、電子元件以及應力補償層。所述重佈線層結構具有相對的第一表面與第二表面。所述晶片設置於所述重佈線層結構的所述第一表面上,且與所述重佈線層結構電性連接。所述電子元件設置於所述重佈線層結構中,與所述晶片電性連接,且包括設置於其中的介電層。所述應力補償層設置於所述重佈線層結構中。所述介電層在垂直於所述第二表面的第一方向上提供50Mpa至200Mpa之間的第一應力,所述應力補償層在與所述第一方向相反的第二方向上提供50Mpa至200Mpa之間的第二應力,且所述第一應力與所述第二應力之間的差不超過60Mpa。
本申請的半導體封裝結構包括重佈線層結構、晶片、電子元件以及應力補償層。所述重佈線層結構具有相對的第一表面與第二表面。所述晶片設置於所述重佈線層結構的所述第一表面上,且與所述重佈線層結構電性連接。所述電子元件設置於所述重佈線層結構中,與所述晶片電性連接,且包括設置於其中的介電層。所述應力補償層設置於所述重佈線層結構上。所述介電層在垂直於所述第二表面的第一方向上提供50Mpa至200Mpa之間的第一應力,所述應力補償層在與所述第一方向相反的第二方向上提供50Mpa至200Mpa之間的第二應力,且所述第一應力與所述第二應力之間的差不超過60Mpa。
為讓本申請能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
10、20、30、40、50、60、70、80、90、92、94:半導體封裝結構
100:重佈線層結構
100a:線路層
100b:接觸窗
100c:絕緣層
101a:第一表面
101b:第二表面
102:晶片
103:包封體
104、204:電子元件
104a:上電極
104b:下電極
104c、204b:介電層
105、108a、108b、205:導通孔
106、106a、106b、106c、106d:應力補償層
110a、110b:接墊
112:承載基板
204a:電極層
圖1為依照本申請第一實施例的半導體封裝結構所繪示的剖面示意圖。
圖2為依照本申請第二實施例的半導體封裝結構所繪示的剖面示意圖。
圖3為依照本申請第三實施例的半導體封裝結構所繪示的剖面示意圖。
圖4為依照本申請第四實施例的半導體封裝結構所繪示的剖面示意圖。
圖5為依照本申請第五實施例的半導體封裝結構所繪示的剖面示意圖。
圖6為依照本申請第六實施例的半導體封裝結構所繪示的剖面示意圖。
圖7為依照本申請第七實施例的半導體封裝結構所繪示的剖面示意圖。
圖8為依照本申請第八實施例的半導體封裝結構所繪示的剖面示意圖。
圖9為依照本申請第九實施例的半導體封裝結構所繪示的剖面示意圖。
圖10為依照本申請第十實施例的半導體封裝結構所繪示的剖
面示意圖。
圖11為依照本申請第十一實施例的半導體封裝結構所繪示的剖面示意圖。
圖12為依照本申請其他實施例的半導體封裝結構所繪示的剖面示意圖。
圖13為依照本申請其他實施例的半導體封裝結構所繪示的剖面示意圖。
下文列舉實施例並配合附圖來進行詳細地說明,但所提供的實施例並非用以限制本申請所涵蓋的範圍。此外,附圖僅以說明為目的,並未依照原尺寸進行繪示。為了方便理解,在下述說明中,相同的元件將以相同的元件符號來說明。
此外,文中所提到「上」、「下」等的方向性用語,僅是用以參考附圖的方向,並非用以限制本申請。
圖1為依照本申請第一實施例的半導體封裝結構所繪示的剖面示意圖。請參照圖1,本實施例的半導體封裝結構10主要包括重佈線層結構100、晶片102、電子元件104以及應力補償層106。重佈線層結構100具有相對的第一表面101a與第二表面101b。重佈線層結構100包括線路層100a、連接每一層線路層100a的接觸窗100b以及絕緣層100c。線路層100a與接觸窗100b設置於絕緣層100c中,且每一層線路層100a通過絕緣層而彼此分離開。
在本實施例中,為了使附圖清晰,僅繪示出2層線路層100a,但本申請不限於此。在其他實施例中,重佈線層結構可視實際需求而包括更多層的線路層。此外,本申請也不對重佈線層結構的佈局以及各構件的材料作限定。
晶片102設置於重佈線層結構100的第一表面101a上,且與重佈線層結構100電性連接。詳細地說,晶片102通過設置於絕緣層100c中的導通孔108a以及設置於重佈線層結構100的第一表面101a上且與導通孔108a連接的接墊110a而與重佈線層結構100電性連接。晶片102可通過設置於其主動表面上的接墊(未繪示)而與接墊110a連接。然而,晶片102可以任何其他熟知的方式來與重佈線層結構100電性連接,本申請不對此做限定。晶片102可為各種熟知的晶片,例如記憶晶片、控制晶片等等,本申請不對此作限定。此外,包封體103設置於重佈線層結構100的第一表面101a上並包封晶片102,以避免晶片102受到損壞。
電子元件104設置於重佈線層結構100中,且與晶片102電性連接。詳細地說,晶片102通過設置於絕緣層100c中的導通孔108b以及設置於重佈線層結構100的第一表面101a上且與導通孔108b連接的接墊110b而與電子元件104電性連接。晶片102可通過設置於其主動表面上的接墊(未繪示)而與接墊110b連接。然而,晶片102可以任何其他熟知的方式來與電子元件104電性連接,本申請不對此作限定。
在本實施例中,電子元件104為包括具高介電常數(例
如介電常數大於3.9)的介電層的元件。介電層的材料例如為氧化鋅、氧化鈦、氧化鉭、氧化鋁或其組合。也就是說,只要其中具有高介電常數的介電層的電容器、電阻器、電感器、濾波器、天線、電晶體或其組合皆可作為本實施例的電子元件104。因此,在以下內容中,將示例性地採用電容器來作為電子元件104,但本申請不限於此。此外,一般來說,當電子元件104中具有高介電常數的介電層時,取決於介電層的材料,在垂直於重佈線層結構100的第二表面101b的第一方向上會提供第一應力,後續將對此作進一步說明。
在本實施例中,以電容器為例,電子元件104包括上電極104a、下電極104b以及位於上電極104a與下電極104b之間的介電層104c。上電極104a與下電極104b經由導通孔105而電性連接。介電層104c具高介電常數(例如介電常數大於3.9)且作為電容器的電容介電層。上電極104a與下電極104b的詳細結構與材料為領域技術人員所熟知,於此不另行說明。在本實施例中,為了便於說明,以平板式電容器為例來說明電子元件104,但本申請不限於此。在其他實施例中,電子元件104也可以是其他類型的電容器,只要以高介電常數的介電層作為電容介電層即可。
應力補償層106設置於重佈線層結構100中。詳細地說,在本實施例中,應力補償層106設置於上電極104a與介電層104c之間。應力補償層106的材料例如為氧化矽、氮化矽、氧化鋁或其組合。應力補償層106用以降低或抵銷介電層104c提供的第一
應力。因此,取決於介電層104c提供的第一應力,應力補償層106在與第一方向相反的第二方向上提供第二應力。舉例來說,當介電層104c在垂直於重佈線層結構100的第二表面101b的第一方向上提供張應力時,應力補償層106則在第二方向上提供壓應力。反之,當介電層104c在垂直於重佈線層結構100的第二表面101b的第一方向上提供壓應力時,應力補償層106則在第二方向上提供張應力。在本實施例中,介電層104c提供的第一應力介於50Mpa至200Mpa之間,應力補償層106提供的第二應力介於50Mpa至200Mpa之間,且第一應力與第二應力之間的差不超過60Mpa。如此一來,介電層104c產生的第一應力可被降低或抵銷,因此可避免半導封裝結構10產生翹曲或捲曲的問題。如表1所示,當針對一個薄膜(例如玻璃)進行翹曲測試時,若在相對的方向上的應力差不超過60Mpa,則所述薄膜的翹曲現象不明顯且屬於可接受程度。所述翹曲測試包括針對矩形薄膜在相對的方向上分別施加應力,且測量矩形薄膜的四個側邊處(位置A、位置B、位置C與位置D)的翹曲值。
特別一提的是,在應力補償層106和電子元件104中的介電層的材料皆為氧化鋁的情況下,可藉由調整膜層厚度變化、膜沉積速率、膜沉積溫度、沉積製程中的氣體流量比或退火溫度來調整應力補償層106和電子元件104中的介電層各自的應力。
在第一實施例中,應力補償層106設置於重佈線層結構100中,且位於電子元件104中,以達到降低或抵銷介電層104c提供的應力的目的,但本申請不限於此。在其他實施例中,應力補償層106設置於重佈線層結構100中的其他位置。
此外,在本申請中,應力補償層106可為單層或多層,且在多層的情況下相鄰兩層的材料可彼此不同。在第一實施例中,應力補償層106為單層。在另一實施例中,應力補償層106可為由應力補償層106a與應力補償層106b所構成的雙層結構,如圖12所示。在其他實施例中,應力補償層106可為三層結構或具有更多層的多層結構。在應力補償層106為多層結構的實施例中,介電層104c提供的第一應力介於50Mpa至200Mpa之間,各應
力補償層提供的合力為第二應力,第二應力介於50Mpa至200Mpa之間,且第一應力與第二應力之間的差不超過60Mpa。
圖2為依照本申請第二實施例的半導體封裝結構所繪示的剖面示意圖。在本實施例中,與第一實施例相同的元件將以相同的元件符號表示,且不再對其進行說明。
請參照圖2,在本實施例中,與第一實施例的差異在於:在半導體封裝結構20中,應力補償層106設置於重佈線層結構100中,且位於電子元件104與重佈線層結構100的線路層100a上方。詳細地說,在本實施例中,應力補償層106覆蓋電子元件104的上電極104a與最上層的線路層100a。此外,導通孔108a穿過線路層100a上方的應力補償層106而與最上層的線路層100a連接,以將線路層100a與接墊110a電性連接,且導通孔108b穿過電子元件104上方的應力補償層106而與上電極104a電性連接,以將電子元件104與接墊110b電性連接。
此外,在本實施例中,應力補償層106與上電極104a以及最上層的線路層100a接觸,但本申請不限於此。在其他實施例中,應力補償層106也可以與上電極104a以及最上層的線路層100a間隔一段距離。
在本實施例中,由於重佈線層結構100中設置有應力補償層106,因此電子元件104中的介電層104c產生的應力可被應力補償層106降低或抵銷,因而可有效地避免半導封裝結構20產生翹曲或捲曲。
圖3為依照本申請第三實施例的半導體封裝結構所繪示的剖面示意圖。在本實施例中,與第一實施例相同的元件將以相同的元件符號表示,且不再對其進行說明。
請參照圖3,在本實施例中,與第二實施例的差異在於:在半導體封裝結構30中,應力補償層106設置於重佈線層結構100中,且僅位於電子元件104上方。詳細地說,在本實施例中,應力補償層106覆蓋電子元件104的上電極104a,且應力補償層106和電子元件104中的介電層104c實質上具有相同的尺寸或具有相同的投影面積,亦即應力補償層106是對應於介電層104c而設置。此外,導通孔108b穿過電子元件104上方的應力補償層106而與上電極104a電性連接,以將電子元件104與接墊110b電性連接。
此外,在本實施例中,應力補償層106與上電極104a接觸,但本申請不限於此。在其他實施例中,應力補償層106也可以與上電極104a間隔一段距離。
在本實施例中,由於重佈線層結構100中設置有應力補償層106,因此電子元件104中的介電層104c產生的應力可被應力補償層106降低或抵銷,因而可有效地避免半導封裝結構30產生翹曲或捲曲。
圖4為依照本申請第四實施例的半導體封裝結構所繪示的剖面示意圖。在本實施例中,與第一實施例相同的元件將以相同的元件符號表示,且不再對其進行說明。
請參照圖4,在本實施例中,與第一實施例的差異在於:
在半導體封裝結構40中,應力補償層106設置於重佈線層結構100中,且位於電子元件104與重佈線層結構100的線路層100a的周圍。詳細地說,在本實施例中,應力補償層106位於電子元件104的下電極104b周圍以及重佈線層結構100的最下層的線路層100a的周圍,但本申請不限於此。在其他實施例中,應力補償層106也可位於電子元件104的上電極104a周圍以及重佈線層結構100的最上層的線路層100a的周圍,或者應力補償層106也可位於電子元件104與線路層100a的周圍的其他位置。
在本實施例中,由於重佈線層結構100中設置有應力補償層106,因此電子元件104中的介電層104c產生的應力可被應力補償層106降低或抵銷,因而可有效地避免半導封裝結構40產生翹曲或捲曲。
圖5為依照本申請第五實施例的半導體封裝結構所繪示的剖面示意圖。在本實施例中,與第一實施例相同的元件將以相同的元件符號表示,且不再對其進行說明。
請參照圖5,在本實施例中,與第一實施例的差異在於:在半導體封裝結構50中,應力補償層106設置於重佈線層結構100中,且位於電子元件104與重佈線層結構100的線路層100a下方。詳細地說,在本實施例中,應力補償層106覆蓋電子元件104的下電極104b與最下層的線路層100a。
此外,在本實施例中,應力補償層106與下電極104b以及最下層的線路層100a接觸,但本申請不限於此。在其他實施例
中,應力補償層106也可以與下電極104b以及最下層的線路層100a間隔一段距離。
在本實施例中,由於重佈線層結構100中設置有應力補償層106,因此電子元件104中的介電層104c產生的應力可被應力補償層106降低或抵銷,因而可有效地避免半導封裝結構50產生翹曲或捲曲。
圖6為依照本申請第六實施例的半導體封裝結構所繪示的剖面示意圖。在本實施例中,與第一實施例相同的元件將以相同的元件符號表示,且不再對其進行說明。
請參照圖6,在本實施例中,與第五實施例的差異在於:在半導體封裝結構60中,應力補償層106設置於重佈線層結構100中,且僅位於電子元件104下方。詳細地說,在本實施例中,應力補償層106直接設置為電子元件104的下電極104b接觸,且應力補償層106和電子元件104中的介電層104c實質上具有相同的尺寸或具有相同的投影面積,亦即應力補償層106是對應於介電層104c而設置。
此外,在本實施例中,應力補償層106與下電極104b接觸,但本申請不限於此。在其他實施例中,應力補償層106也可以與下電極104b間隔一段距離。
在本實施例中,由於重佈線層結構100中設置有應力補償層106,因此電子元件104中的介電層104c產生的應力可被應力補償層106降低或抵銷,因而可有效地避免半導封裝結構60產
生翹曲或捲曲。
在上述的各實施例中,應力補償層106皆設置於重佈線層結構100中,以降低或抵銷電子元件104中的介電層104c產生的應力,但本申請不限於此。在其他實施例中,應力補償層106也可設置於重佈線層結構100的外部,且仍可具有降低或抵銷電子元件104中的介電層104c產生的應力的效果,以下將對此作進一步說明。
圖7為依照本申請第七實施例的半導體封裝結構所繪示的剖面示意圖。在本實施例中,與第一實施例相同的元件將以相同的元件符號表示,且不再對其進行說明。
請參照圖7,在本實施例中,與第一實施例的差異在於:在半導體封裝結構70中,應力補償層106設置於重佈線層結構100上,且位於重佈線層結構100的第一表面101a上。詳細地說,在本實施例中,應力補償層106設置於重佈線層結構100的絕緣層100c與包封體103之間,且位於接墊110a與接墊110b的周圍。
在本實施例中,由於重佈線層結構100的表面上設置有應力補償層106,因此電子元件104中的介電層104c產生的應力可被應力補償層106降低或抵銷,因而可有效地避免半導封裝結構70產生翹曲或捲曲。
圖8為依照本申請第八實施例的半導體封裝結構所繪示的剖面示意圖。在本實施例中,與第一實施例相同的元件將以相同的元件符號表示,且不再對其進行說明。
請參照圖8,在本實施例中,與第七實施例的差異在於:在半導體封裝結構80中,應力補償層106設置於重佈線層結構100上,且位於重佈線層結構100的第二表面101b上。
在本實施例中,由於重佈線層結構100的表面上設置有應力補償層106,因此電子元件104中的介電層104c產生的應力可被應力補償層106降低或抵銷,因而可有效地避免半導封裝結構80產生翹曲或捲曲。
此外,在另一實施例中,可如同第七實施例與第八實施例所述,於重佈線層結構100的第一表面101a上以及第二表面101b上同時設置應力補償層。如圖13所示,重佈線層結構100的第一表面101a上設置有應力補償層106c,重佈線層結構100的第二表面101b上設置有應力補償層106d,且應力補償層106c與應力補償層106d的材料可彼此相同或不同。在應力補償層106為多層結構的實施例中,介電層104c提供的第一應力介於50Mpa至200Mpa之間,各應力補償層提供的合力為第二應力,第二應力介於50Mpa至200Mpa之間,且第一應力與第二應力之間的差不超過60Mpa。
在上述的各實施例中,電子元件104與重佈線層結構100的線路層100a設置於實質上相同的水平高度上,但本申請不限於此。在其他實施例中,電子元件104與重佈線層結構100的線路層100a可設置於不同的水平高度上,以下將對此作進一步說明。
圖9為依照本申請第九實施例的半導體封裝結構所繪示
的剖面示意圖。在本實施例中,與第一實施例相同的元件將以相同的元件符號表示,且不再對其進行說明。
請參照圖9,在本實施例中,與第八實施例的差異在於:在半導體封裝結構90中,電子元件104設置於重佈線層結構100的線路層100a的下方。此外,電子元件104的上電極104a通過最下層的接觸窗100b而與最下層的線路層100a電性連接。
在本實施例中,由於重佈線層結構100的第二表面101b上設置有應力補償層106,因此電子元件104中的介電層104c產生的應力可被應力補償層106降低或抵銷,因而可有效地避免半導封裝結構90產生翹曲或捲曲。
圖10為依照本申請第十實施例的半導體封裝結構所繪示的剖面示意圖。在本實施例中,與第一實施例相同的元件將以相同的元件符號表示,且不再對其進行說明。
請參照圖10,在本實施例中,與第八實施例的差異在於:在半導體封裝結構92中,電子元件204設置於重佈線層結構100中,且與晶片102電性連接。電子元件204包括多個電極層204a以及夾設於這些電極層204a之間的介電層204b。電極層204a如同上電極104a與下電極104b,且介電層204b如同介電層104c,於此不再進行說明。此外,相鄰的電極層204a之間經由導通孔205而電性連接。也就是說,在本實施例中,電子元件204為由多個電極層204a所堆疊形成的電容器。此外,在本實施例中,電子元件204包括3層電極層204a與2層介電層204b,但本申請不限於
此。在其他實施例中,電子元件可包括更多層電極層與更多層介電層。舉例來說,在一些實施例中,電子元件204可包括4層電極層204a與3層介電層204b,甚至可包括21層電極層204a與20層介電層204b。
在本實施例中,由於重佈線層結構100的第二表面101b上設置有應力補償層106,因此電子元件204中的介電層204b產生的應力可被應力補償層106降低或抵銷,因而可有效地避免半導封裝結構92產生翹曲或捲曲。
在上述的各實施例中,半導封裝結構並未包括承載基板,但本申請不限於此。在其他實施例中,半導封裝結構也可包括承載基板,以下將對此作進一步說明。
圖11為依照本申請第十一實施例的半導體封裝結構所繪示的剖面示意圖。在本實施例中,與第一實施例相同的元件將以相同的元件符號表示,且不再對其進行說明。
請參照圖11,在本實施例中,與第一實施例的差異在於:半導體封裝結構94包括承載基板112,且承載基板112設置於重佈線層結構100的第二表面101b上。承載基板112可為介電基板,例如為聚醯亞胺(polyimide,PI)基板,其用以承載重佈線層結構100、晶片102、包封體103等構件。
此外,在上述各實施例中,也可視實際需求而在重佈線層結構100的第二表面101b上設置承載基板112。另外,在第二表面101b上設置有應力補償層106的實施例中,應力補償層106
則位於重佈線層結構100的第二表面101b與承載基板112之間。
雖然本申請已以實施例揭露如上,然其並非用以限定本申請,任何所屬技術領域中具有通常知識者,在不脫離本申請的精神和範圍內,當可作些許的更動與潤飾,故本申請的保護範圍當視後附的申請專利範圍所界定者為準。
10:半導體封裝結構
100:重佈線層結構
100a:線路層
100b:接觸窗
100c:絕緣層
101a:第一表面
101b:第二表面
102:晶片
103:包封體
104:電子元件
104a:上電極
104b:下電極
104c:介電層
105、108a、108b:導通孔
106:應力補償層
110a、110b:接墊
Claims (20)
- 一種半導體封裝結構,包括: 重佈線層結構,具有相對的第一表面與第二表面; 晶片,設置於所述重佈線層結構的所述第一表面上,且與所述重佈線層結構電性連接; 電子元件,設置於所述重佈線層結構中,與所述晶片電性連接,且包括設置於其中的介電層;以及 應力補償層,設置於所述重佈線層結構中, 其中所述介電層在垂直於所述第二表面的第一方向上提供50 Mpa至200 Mpa之間的第一應力,所述應力補償層在與所述第一方向相反的第二方向上提供50 Mpa至200 Mpa之間的第二應力,且所述第一應力與所述第二應力之間的差不超過60 Mpa。
- 如請求項1所述的半導體封裝結構,其中所述第一應力為張應力與壓應力中的一者,且所述第二應力為張應力與壓應力中的另一者。
- 如請求項1所述的半導體封裝結構,其中所述應力補償層的材料包括氧化矽、氮化矽、氧化鋁或其組合。
- 如請求項1所述的半導體封裝結構,其中所述介電層的材料包括氧化鋅、氧化鈦、氧化鉭、氧化鋁或其組合。
- 如請求項1所述的半導體封裝結構,其中所述電子元件包括電容器、電阻器、電感器、濾波器、天線、電晶體或其組合。
- 如請求項5所述的半導體封裝結構,其中所述電子元件為電容器,其中所述電容器包括上電極、下電極以及位於其間的所述介電層,且所述應力補償層設置於所述上電極與所述介電層之間。
- 如請求項1所述的半導體封裝結構,其中所述應力補償層設置於所述電子元件與所述重佈線層結構的線路層上方。
- 如請求項1所述的半導體封裝結構,其中所述應力補償層僅設置於所述電子元件上方。
- 如請求項1所述的半導體封裝結構,其中所述應力補償層設置於所述電子元件與所述重佈線層結構的線路層的周圍。
- 如請求項1所述的半導體封裝結構,其中所述應力補償層設置於所述電子元件與所述重佈線層結構的線路層下方。
- 如請求項1所述的半導體封裝結構,其中所述應力補償層僅設置於所述電子元件下方。
- 如請求項1所述的半導體封裝結構,更包括承載基板,設置於所述第二表面上。
- 一種半導體封裝結構,包括: 重佈線層結構,具有相對的第一表面與第二表面; 晶片,設置於所述重佈線層結構的所述第一表面上,且與所述重佈線層結構電性連接; 電子元件,設置於所述重佈線層結構中,與所述晶片電性連接,且包括設置於其中的介電層;以及 應力補償層,設置於所述重佈線層結構的外部, 其中所述介電層在垂直於所述第二表面的第一方向上提供50 Mpa至200 Mpa之間的第一應力,所述應力補償層在與所述第一方向相反的第二方向上提供50 Mpa至200 Mpa之間的第二應力,且所述第一應力與所述第二應力之間的差不超過60 Mpa。
- 如請求項13所述的半導體封裝結構,其中所述第一應力為張應力與壓應力中的一者,且所述第二應力為張應力與壓應力中的另一者。
- 如請求項13所述的半導體封裝結構,其中所述應力補償層的材料包括氧化矽、氮化矽、氧化鋁或其組合。
- 如請求項13所述的半導體封裝結構,其中所述介電層的材料包括氧化鋅、氧化鈦、氧化鉭、氧化鋁或其組合。
- 如請求項13所述的半導體封裝結構,其中所述電子元件包括電容器、電阻器、電感器、濾波器、天線、電晶體或其組合。
- 如請求項17所述的半導體封裝結構,其中所述電容器包括多個電極層以及位於相鄰的所述電極層之間的高介電常數層。
- 如請求項13所述的半導體封裝結構,其中所述應力補償層設置於所述第一表面上及/或所述第二表面上。
- 如請求項13所述的半導體封裝結構,更包括承載基板,設置於所述第二表面上。
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