TWI666749B - 封裝基板及封裝結構 - Google Patents
封裝基板及封裝結構 Download PDFInfo
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Abstract
一種封裝基板及封裝結構,該封裝基板係包括複數介電層及複數與各該介電層交互堆疊之線路層,其中,至少二該線路層具有厚度差。本發明能有效避免基板的翹曲現象。
Description
本發明係有關於一種封裝基板及封裝結構,尤指一種包括複數交互堆疊之介電層與線路層之封裝基板及封裝結構。
現行之覆晶技術因具有縮小晶片封裝面積及縮短訊號傳輸路徑等優點,目前已經廣泛應用於晶片封裝領域,例如:晶片尺寸構裝(Chip Scale Package,CSP)、晶片直接貼附封裝(Direct Chip Attached,DCA)以及多晶片模組封裝(Multi-Chip Module,MCM)等型態的封裝模組,其均可利用覆晶技術而達到封裝的目的。
第1圖所示者,係為習知的覆晶式封裝基板之剖視圖,如圖所示,該封裝基板1之內部具有複數線路層11,且各該線路層11的厚度均相同,例如19微米(μm)的厚度。
然而,於覆晶封裝製程的溫度循環(temperature cycle)測試中,因為晶片與封裝基板之熱膨脹係數的差異甚大或受熱不對稱等原因,所以封裝基板容易發生翹曲(warpage),導致許多問題,例如:晶片外圍的凸塊無法與封裝基板上對應的接點形成良好的接合,進而使得產品良率降低。
雖然增加所有該線路層的厚度可減緩封裝基板的翹曲現象,但卻會使得封裝基板的整體厚度增加,進而導致最終封裝結構的
整體厚度增加,不符合現今電子產品之輕薄短小的趨勢。
因此,如何避免上述習知技術中之種種問題,實為目前業界所急需解決的課題。
有鑒於上述習知技術之缺失,本發明提供一種封裝基板,係包括:複數介電層;以及複數與各該介電層交互堆疊之線路層,其中,至少二該線路層具有厚度差。
本發明復提供一種封裝結構,係包括:封裝基板,係包括複數介電層及複數與各該介電層交互堆疊之線路層,至少二該線路層具有厚度差;以及晶片,係接置於該封裝基板之上表面上。
於前述之封裝基板與封裝結構中,位於或接近該封裝基板之上表面的該線路層之厚度係大於位於或接近該封裝基板之下表面之該線路層之厚度,該上表面與下表面係分別為置晶側與非置晶側,最接近該上表面之線路層之厚度係大於其他所有該線路層之厚度,最接近該下表面之線路層之厚度係小於其他所有該線路層之厚度,除最接近該上表面之線路層與最接近下表面之線路層外,其餘的線路層係具有相同之厚度。
於另一實施例中,該等線路層之厚度係由該上表面逐漸往該下表面減少,接近該上表面之半數之線路層之厚度總和係大於接近該下表面之半數之線路層之厚度總和。
於本發明之封裝基板與封裝結構中,該等線路層中之最厚者與最薄者的厚度的比係為1.2:1至2:1,該等線路層中之最厚者與最薄者的厚度的比較佳係為1.5:1。
所述之封裝基板與封裝結構中,該等線路層中之最厚者與最
薄者的厚度的差係為3至15微米,該等線路層中之最厚者與最薄者的厚度的差較佳係為5至10微米。
又依上所述之封裝基板與封裝結構,該等線路層之數量係為單數或雙數。一該介電層係為核心板,且該等線路層係以該核心板為中心之方式對稱分佈於該核心板之相對兩表面上。
由上可知,本發明係調整封裝基板中之部分線路層的厚度,使部分線路層的厚度較厚,以增加封裝基板的整體剛性,減少基板翹曲的發生;此外,由於部分線路層的厚度較薄,故可使所有線路層的厚度總和不增加,進而能避免封裝基板及封裝結構的整體厚度增加。
1‧‧‧封裝基板
11、22‧‧‧線路層
2‧‧‧封裝基板
2a‧‧‧上表面
2b‧‧‧下表面
21‧‧‧介電層
21’‧‧‧核心板
31‧‧‧晶片
32‧‧‧封裝膠體
第1圖所示者係為習知的覆晶式封裝基板之剖視圖;第2圖所示者係本發明之封裝基板之剖視圖;以及第3圖所示者係本發明之封裝結構之剖視圖。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書
中所引用之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。
請參閱第2圖,係本發明之封裝基板之剖視圖。如圖所示,該封裝基板2係包括:複數介電層21;以及複數與各該介電層21交互堆疊之線路層22,其中,至少二該線路層22具有厚度差,其中,一該介電層21可為核心板21’,且該等線路層22係以該核心板21’為中心之方式對稱分佈於該核心板21’之相對兩表面上。
前述之封裝基板中,位於或接近該封裝基板2之上表面2a的該線路層22之厚度係大於位於或接近該封裝基板2之下表面2b之該線路層22之厚度,該上表面2a與下表面2b係分別為置晶側與非置晶側。
依前所述之封裝基板,最接近該上表面2a之線路層22之厚度係大於其他所有該線路層22之厚度,最接近該下表面2b之線路層22之厚度係小於其他所有該線路層22之厚度,除最接近該上表面2a之線路層22與最接近下表面2b之線路層22外,其餘的線路層22係具有相同之厚度。例如,該等線路層22之層數為6,該等線路層22之厚度由該上表面2a至該下表面2b分別是26微米、19微米、19微米、19微米、19微米與12微米。
於另一實施例中,該等線路層22之厚度係由該上表面2a逐漸往該下表面2b減少。例如,該等線路層22之層數為6,該等線路層22之厚度由該上表面2a至該下表面2b分別是26微米、23微米、19微米、19微米、15微米與12微米。
於另一實施例中,接近該上表面2a之半數之線路層22之厚度總和係大於接近該下表面2b之半數之線路層22之厚度總和。例如,該等線路層22之層數為6,該等線路層22之厚度由該上表面2a至該下表面2b分別是26微米、24微米、20微米、18微米、14微米與12微米。
再者,於一實施例中,如第2圖所示,該等線路層22之層數為6,該等線路層22之厚度由該上表面2a至該下表面2b分別是22微米、22微米、22微米、16微米、16微米與16微米。
又依前所述之封裝基板,該等線路層22中之最厚者與最薄者的厚度的比係為1.2:1至2:1,該等線路層22中之最厚者與最薄者的厚度的比係較佳為1.5:1。
又於所述之封裝基板中,該等線路層22中之最厚者與最薄者的厚度的差係為3至15微米,該等線路層22中之最厚者與最薄者的厚度的差係較佳為5至10微米。
於本發明之封裝基板中,該等線路層22之數量係為單數或雙數。
請參閱第3圖,係本發明之封裝結構之剖視圖。如圖所示,其主要係於本發明之封裝基板2之上表面2a上接置有晶片31,並形成有包覆該晶片31的封裝膠體32,至於其餘技術特徵大致如前所述,故不再為文贅述。
綜上所述,相較於習知技術,本發明係調整封裝基板中之部分線路層的厚度,使部分線路層的厚度較厚,以增加封裝基板的整體剛性,減少基板翹曲的發生(約減少5至25%),進而提高產品的良率;此外,由於並非增厚所有線路層的厚度,或者,由於
可使部分線路層的厚度減少,即部分線路層的厚度較薄,故可使所有線路層的厚度總和不增加,進而能避免封裝基板及封裝結構的整體厚度增加,而能符合現今電子產品之輕薄短小的趨勢。
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。
Claims (23)
- 一種封裝基板,係包括:複數介電層;以及複數與各該介電層交互堆疊之線路層,其中,位於該封裝基板之上表面之該線路層與下表面之該線路層之厚度不相同,位於該上表面與下表面之其中一者之該線路層的厚度大於其他線路層之厚度,位於該上表面與下表面之另一者之該線路層的厚度小於其他線路層之厚度。
- 如申請專利範圍第1項所述之封裝基板,其中,位於該封裝基板之上表面的該線路層之厚度係大於位於該封裝基板之下表面之該線路層之厚度。
- 如申請專利範圍第2項所述之封裝基板,其中,該上表面與下表面係分別為置晶側與非置晶側。
- 如申請專利範圍第2項所述之封裝基板,其中,位於該上表面之線路層之厚度係大於其他所有該線路層之厚度,位於該下表面之線路層之厚度係小於其他所有該線路層之厚度,除位於該上表面之線路層與位於該下表面之線路層外,其餘的線路層係具有相同之厚度。
- 如申請專利範圍第2項所述之封裝基板,其中,該等線路層之厚度係由該上表面逐漸往該下表面減少。
- 如申請專利範圍第2項所述之封裝基板,其中,接近該上表面之半數之線路層之厚度總和係大於接近該下表面之半數之線路層之厚度總和。
- 如申請專利範圍第2項所述之封裝基板,其中,該等線路層中之最厚者與最薄者的厚度的比係為1.2:1至2:1。
- 如申請專利範圍第7項所述之封裝基板,其中,該等線路層中之最厚者與最薄者的厚度的比係為1.5:1。
- 如申請專利範圍第2項所述之封裝基板,其中,該等線路層中之最厚者與最薄者的厚度的差係為3至15微米。
- 如申請專利範圍第9項所述之封裝基板,其中,該等線路層中之最厚者與最薄者的厚度的差係為5至10微米。
- 如申請專利範圍第2項所述之封裝基板,其中,該等線路層之數量係為單數或雙數。
- 如申請專利範圍第2項所述之封裝基板,其中,該複數介電層之其中一者係為核心板,且該等線路層之層數係以該核心板為中心之方式對稱分佈於該核心板之相對兩表面上。
- 一種封裝結構,係包括:封裝基板,係包括複數介電層及複數與各該介電層交互堆疊之線路層,其中,位於該封裝基板之上表面之該線路層與下表面之該線路層之厚度不相同,位於該上表面與下表面之其中一者之該線路層的厚度大於其他線路層之厚度,位於該上表面與下表面之另一者之該線路層的厚度小於其他線路層之厚度;以及晶片,係接置於該封裝基板之上表面上。
- 如申請專利範圍第13項所述之封裝結構,其中,位於該封裝基板之上表面的該線路層之厚度係大於位於該封裝基板之下表面之該線路層之厚度。
- 如申請專利範圍第14項所述之封裝結構,其中,位於該上表面之線路層之厚度係大於其他所有該線路層之厚度,位於該下表面之線路層之厚度係小於其他所有該線路層之厚度,除位於該上表面之線路層與位於該下表面之線路層外,其餘的線路層係具有相同之厚度。
- 如申請專利範圍第14項所述之封裝結構,其中,該等線路層之厚度係由該上表面逐漸往該下表面減少。
- 如申請專利範圍第14項所述之封裝結構,其中,接近該上表面之半數之線路層之厚度總和係大於接近該下表面之半數之線路層之厚度總和。
- 如申請專利範圍第14項所述之封裝結構,其中,該等線路層中之最厚者與最薄者的厚度的比係為1.2:1至2:1。
- 如申請專利範圍第18項所述之封裝結構,其中,該等線路層中之最厚者與最薄者的厚度的比係為1.5:1。
- 如申請專利範圍第14項所述之封裝結構,其中,該等線路層中之最厚者與最薄者的厚度的差係為3至15微米。
- 如申請專利範圍第20項所述之封裝結構,其中,該等線路層中之最厚者與最薄者的厚度的差係為5至10微米。
- 如申請專利範圍第14項所述之封裝結構,其中,該等線路層之數量係為單數或雙數。
- 如申請專利範圍第14項所述之封裝結構,其中,該複數介電層之其中一者係為核心板,且該等線路層之層數係以該核心板為中心之方式對稱分佈於該核心板之相對兩表面上。
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CN201410089672.4A CN104851870B (zh) | 2014-02-19 | 2014-03-12 | 封装基板及封装结构 |
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WO2003063238A1 (fr) * | 2002-01-25 | 2003-07-31 | Sony Corporation | Module haute frequence et son procede de fabrication |
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US6326557B1 (en) * | 2001-03-06 | 2001-12-04 | Mitac International Corp. | Multi-layer circuit board |
JP5026400B2 (ja) * | 2008-12-12 | 2012-09-12 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
JP5830400B2 (ja) * | 2012-02-02 | 2015-12-09 | ルネサスエレクトロニクス株式会社 | 半導体装置、および半導体装置の製造方法 |
US9768102B2 (en) * | 2012-03-21 | 2017-09-19 | STATS ChipPAC Pte. Ltd. | Integrated circuit packaging system with support structure and method of manufacture thereof |
US9230896B2 (en) * | 2012-06-05 | 2016-01-05 | Stats Chippac, Ltd. | Semiconductor device and method of reflow soldering for conductive column structure in flip chip package |
JP2014090080A (ja) * | 2012-10-30 | 2014-05-15 | Ibiden Co Ltd | プリント配線板、プリント配線板の製造方法及び電子部品 |
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WO1998020555A1 (en) * | 1996-11-08 | 1998-05-14 | W.L. Gore & Associates, Inc. | Method for minimizing warp in the production of electronic assemblies |
WO2003063238A1 (fr) * | 2002-01-25 | 2003-07-31 | Sony Corporation | Module haute frequence et son procede de fabrication |
TW200628040A (en) * | 2003-07-29 | 2006-08-01 | Matsushita Electric Ind Co Ltd | Multi-layer circuit board and the manufacturing method of the multi-layer circuit board |
TW200528004A (en) * | 2004-02-04 | 2005-08-16 | Ibiden Co Ltd | Multilayer printed wiring board |
WO2009037939A1 (ja) * | 2007-09-20 | 2009-03-26 | Ibiden Co., Ltd. | プリント配線板及びその製造方法 |
TWI365020B (en) * | 2008-03-27 | 2012-05-21 | Unimicron Technology Corp | Method of fabricating package substrate having semiconductor component embedded therein |
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US9900996B2 (en) | 2018-02-20 |
US20150237717A1 (en) | 2015-08-20 |
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