TWI365020B - Method of fabricating package substrate having semiconductor component embedded therein - Google Patents

Method of fabricating package substrate having semiconductor component embedded therein Download PDF

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TWI365020B
TWI365020B TW97110932A TW97110932A TWI365020B TW I365020 B TWI365020 B TW I365020B TW 97110932 A TW97110932 A TW 97110932A TW 97110932 A TW97110932 A TW 97110932A TW I365020 B TWI365020 B TW I365020B
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Taiwan
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layer
dielectric layer
dielectric
semiconductor wafer
metal
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TW97110932A
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Chinese (zh)
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TW200942105A (en
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Shih Ping Hsu
Kan Jung Chia
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Unimicron Technology Corp
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1365020 九、發明說明: 【發明所屬之技術領域】 本發明係有關於—種嵌埋有半導體元件之封裝 露半導體元件之非主動面以達散熱:果。 由於電子產品日趨輕薄短小’故對於用於承载邮 元件或電子元件之封裝基板亦需隨之縮減,而半導二 技術的演進已開發出不同的封裝型態,其中如球栅: i gr ld array,腸),係為—種先進的半導體封㈣ 術,其特點在於採用一基板來安置半導體晶片。 辦曰惟’傳統上該球柵陣列式之半導體封裝結構係將半導 胆晶片以覆晶接合(Flip Ghip)方式與基板電性連接 ㈣的目的1在更高頻使科或高速操 因導線連接路徑過長而產生電氣特性無法提昇,因而效能 有所限制’另外’因傳統料需要多次的連接介面 地增加生產製造成本。 宁 為能有效地提昇電性品質而符合下世代產品之應 用’業界紛紛研究㈣將半㈣W埋人縣基板中^ 接電性連接,而可肺電性料路徑,並減少訊號損失及 汛唬失真,以提昇在高速運作之能力。 請參閱第1A至1C圖,係為習知將半導體晶片嵌埋在 封裝基板中之製法剖視圖。 如第1A圖所示,首先’提供一第一基板⑽及第二 基板10b’其中該第—基板1Ga係具有至少—貫穿之開口 110593 1365020 . 100 〇 • 士弟1Β圖所示,將該第一基板i ο a結合於該第一 '板,上,且於該第一基板10a之開口 1〇〇中容置 -導體晶片1卜並以結合材料11〇將該半導體晶片u固定 於該開〇刚令,該半導體晶片…系具有一主動面Ua 及與該主動面lla相對之非主動面llb,且該主動面lla t具有複數電㈣1U,以供線路層電性連接至該半導體 晶片11。 •如帛1C圖所示,於該第一基板10a及半導體晶片u =動山面1U上形成有—增層結構12,以將該半導體晶 敢埋於第—及第:基板他,1()b中該增層結構Μ 二至少一介電層12〇、疊置於該介電層⑽上之線路 -I部數形成於該介電層120中之導電盲孔122, 之導電盲孔122電性連接該半導體晶片u之電極 η又於該增層結構12上具有複數電性接觸塾⑵, 且”玄电性接觸墊12 3電性連接兮始a ! 0, 社 电r連接5亥線路層121;另於該增層 、、”構12上形成有防焊層13, iqn ^ U防坏層13中具有複數 以對應露出該電性接觸墊12 3。 然:前述製法中’該半導體晶片u係設 板10a中,且該第二基板 ⑽的-端,故該半導體曰,〗广基板1〇3之開口 見私山. 牛蛉肢日日月11運作時所產生之熱量不 易放出,且隨著半導體晶片效 , 的熱量亦明顯增加,如益法有、曰 而伴&產生 Β μ ‘、,、法有效進行散熱,將嚴重影響半 導體晶片之性能及壽命。 曰干 ]10593 6 因此’如何提出一種半導體晶片纟埋式封裝結構,以 服白知半導體封裝結構製程中結構不易散熱等問題實 已成為目前業界亟待解決之課題。 、 【發明内容】 繁於以上所述習知技術之缺失,本發明之一目的在於 ^供種肷财半導體元件之封裝基板製法,係裸露半導 収元件之非主動面以達散熱效果。 為達上揭目的,本發明提供一種谈埋有半導體元件之 爲裳基板製法,係包括:提供—嵌埋有半導體晶片之介電 :’該半導體晶片具有—主動面及相對應之非主動面,且 二主動面具有複數電極墊’該介電層之二表面分別具有第 側:C二金屬層,且該介電層接觸於該第-金屬層 厂第-表面’接觸於該第二金屬層側為相對應之第二表 。玄第及第一金屬層經圖案化製程以於該介電層之 表面形成卜線路層,而於該介電層之第二表面形成 線路層;以及移除形成於該半導體晶片之非主動面 上之介電層以露出該半導體晶片之非主動面。 依上述之製法,該嵌埋有半導體晶片之介電層及於盆 具有之第-及第二金屬層之製法,係包括:提供一第 ;丨電層及第二介電層’其中該第二介電層中形成有一貫 曰之開口區;於該第二介電層之開口區中容設該半導體 ::’於該第一介電層之外側置設有-第-金屬層,並於 =二介電層及該半導體晶片之非主動面設有一第二全 葡層,以及壓合該第一金屬層、第—介電層、第二介電層 110593 7 1365020 及第二金屬層,使該第一介電 .層以固定該半導體晶片,其中^入層合成一介電 -屬層側成為第一表面 二、~ Λ ;丨宅層接觸於該第一金 ;二表面。 面’於該第二金屬層側成為相對應之第 之製法,該嵌埋有半導體晶片之介電芦及於 一金屬層及第一介電芦植志夕# 打匕括·鈇供由弟 屬層及第二介電層心之f 一背膠銅箔’及由第二金 鲁中形成有一貫穿之開口區; ;丨电層 容設該半導體晶片; 人^―”電層之開口區中 膠銅猪,使哕a该弟—背膠銅落及第二背 』泊使,亥弟一介電層及第二介電層 定該半導體晶片,其中,該介帝展垃雄 )丨电層以固 .:為第-表面,於該第二金屬層側成為相對應之第二表 或依上述之製法’該嵌埋有半導體晶片之介電層及於 ,、表面具有之第一及第二金屬層之製法,係包括:提供由 弟二金屬層及第二介電層組成之第二背勝銅箱、具有核心 介電層開口之核心介電層、及係由第一金屬層及第一介電 層組成之第一背膠銅馆;於該第二背膠銅绪之第二介電 層上接置該半導體晶片之非主動面,且該核心介電層開口 對應該半導體晶片;壓合該第—背膠銅箔、核心介電層、 及第二背_1 ’使該第一介電層、核心介電層及第二介 電層合成-介電層,並將該半導體晶片固定於該介電詹, 其中該介電層於該第一金屬層側係為第一表面,而於該第 110593 8 1365020 二金屬層側係為相對應之第二表面。 又依上述之製法’該嵌埋有半導體晶片之介電層及於 二面具有之第—及第二金屬層之製法,係包括:提供一 么载板’於S亥承載;卜兮λ古Ώ 成之第二背膠銅羯,且;:二層:第二介電層组 置於該承載板上,於,/第::= 二金屬層接 、μ弟一月骖銅泊中形成有一開口區, 以路出該承載板之部份表 匕 接置該半導體相口區中之承載板上 n aa之非主動面;再提供具有核心介電層 歼之核心介電層、以及由第一金 : =銅泊’其中’該核心介電層開口對應該半導體 Ϊ你第一背膠銅箱、核心介電層、及第二背职銅 =第:介電層、核心介電層及第二介電層合Π 曰以將δ亥半導體晶片 於嗲箪^ η a 力口疋於忒彡丨私層’其中該介電層 於。亥弟-金屬層側係為第 -曰 為相對庫之筮- # & 如於忒弟一金屬層側係 體曰以及移除該承餘,以露出該半導 篮日曰片之非主動面。 /干导 依刖述之製法,該第一介電層 — 性材料,並以雷射或電㈣除該半導=3=熱固 的介電層。 丁守般日日月之非主動面上 二介電層係為感 導體晶片之非主 ,依前述之製法’該第一介電層及第 叙材枓,並以曝光顯影之製程移除該半 動面上的介電層。 + 依以上之製法, 於該非主動面上’而 該半導體晶片復包括有—黏著層形成 該具有黏著層之半導體晶片製法,係 Π0593 9 1365020 包括:提供一承載平板;於該承 將一包含有複數半導體晶片之半成一黏著層; -·人a月之+蛤體晶圓(wafer)背面貼 • 、者層上;切割該半導體晶圓及該黏著層;以及 .移除該承載平板,以形成複 一’曰 致月面具有毒占考層之半導Ί#晶 月;該具有黏著層之半導 ,牛導虹日日片砍埋於該介電層中,並露 出口亥读占者層’之後以加埶戋 之黏著層。 ,”、戈UV先照射移除該半導體晶月 忒弟-及第二金屬層係為銅箔"亥第一及第 層之製法,係包括:於該介雷 μ 、’、 .^ . 電^之弟一表面及第一金屬層 开:成有位於該半導體晶片之電極塾上的介電層開孔’並 通孔;於該第-金屬層、第二金屬層 及電極墊之部份表面上形成—導電層;於料電\層3 =成-第三金屬層,並於該通孔内;; 通孔内部之空間,或該導雷 具而該導电 第-么恩麻* 係為實心導電通孔;於該 製程而形成有對應該半導體晶片層之電:::層經圖案化 日日5之電極塾的阻層筮一龆 口與對應該半導體晶片之非主& = L 曰弟開 除兮阻Μ ^ : 層第二開口;移 層’並移除該阻層第二開口中之第三金屬層、㈣及J 二金屬層;以及移除該第—阻層,以於該介電層^一 = 面形成該第一線路層,並於該介電層之第_開孔又 一導電盲孔以電性連接該半導體晶片之電極塾,且= ]〇 110593 電t第二表面形成該第二線路層, • ::ΐ有複數第-電性接觸塾,而該第::路::線路層並 .數第—電性接觸墊,且詨 、胃並形成有複 ’及第二線路層。 /电3^电性連接該第一線路層 形成有一第—J焊’:,層,1一表0面與該第-線路層表面 孔以對應露出竽第s二第防烊層並形成有複數第-開 於該介電父第:電性接㈣之部分表面;或復包括 增層結構,形成至少-第- :增層結構係包括有至少—第三介電該第 :層上之第三線路層、及複數設於第:介:】:該:三介 】盲孔’該第二導電盲孔並電性:二二2第:導 層,且該第一擗禺纟士祖 弟及弟三線路 數第s s、,°構上具有電性連接該第三線路層之複 焊層7該二 於該第一增層結構上形成有二防 表面㈣面。復包括於該介電層之第二 苐一線路層表面形 =成有第-開口,以露_導=非:::防 二:=3層並形成有複數第二開孔以對應露出該第 表之部分表面;或復包括於該介電層之第二 二師f 層上形成至少一第二增層結構,並於該第 構上形成第二防焊層’且該第二增層結構並形成 體曰=口對應該第二防焊層之第—開口,以露出該半導 曰之非主動面’該第二增層結構係包括有至少一第四 110593 11 1365020 介電層、疊置於該第四介電層上之 — 於第四介電;^巾t _ .胃 、’ s、及複數設 連接,該第三導電盲孔並電性 堤接。亥弟一及弟四線路層,且該第二钍 :複數第四電性接觸;:並於該= 笛- μ 層玄弟二防焊層中形成有複數 - #孔’㈣應露出該第四電性 該第二防焊層並形成有第一開 =面’且 非主動面。 乂路出料導體晶片之 =上述之製法’復包括於該第一介電層及第二介電 曰之間夾設有-核心板,其中該核心板並形成有一貫穿之 =心^ 口以供容置該半導體晶片,該核心板係為具有線 路之線路板或絕緣板,且該核心板復包括形成有一位於今 核心板開口周緣之阻膠框(Dam),而該具有阻膠框之核心 板:法:係包括·提供一核心板,該核心板具有相對應之 第三及第四表面,經圖案化製程以於該核心板之第三表面 上形成有第五線路層,而於該第四表面上則形成有第六線 路層以及一阻膠框;於該第四表面上形成第二阻層且該 第二阻層形成有開口區域以露出該第四表面之第六線路 層;薄化未為該第二阻層所覆蓋之第五線路層與第六線 路層,以成為第五薄化線路層與第六薄化線路層,使該阻 膠框之銅箔厚度高於該第五及第六薄化線路層;以及移 除該第二阻層,並於該阻膠框所圍構之空間中形成貫穿該 核心板之核心板開口。 本發明係將半導體晶片嵌埋於第一介電層及第二介 110593 12 1365020 電層中,且於該第一及第二介恭 -的 电層上为別形成有第一及第 該第一線路層電性連接該半導體晶片,並裸 〜古,二0片之非主動面,使該半導體晶片所產生之熱 里可有效逸散,俾達散熱效果。 【實施方式】 技二Γ二圖式說明本發明之具體實施例,以使所屬 與達二:識者可輕易地瞭解本發明之技術特徵 > [第一實施例] 封至2L圖’料本發明嵌埋有半導體元件之 封裝基板製法之剖面示意圖。 -介22二圖:不’首先’提供-第-介電層21,及第 :=中該第二介電層21,,中並形成有-貫穿 兮第八币,且该第二介電層21,,受熱後之流動性低於 4弟一介電層21,。 中六%古B圖所不’於5亥第二介電層21”之開口區210” 二…半導體晶片22,該半導體晶片以具有一主動 面22a及與其相對應之非主動面 複數電極塾221。 m動面22a具 -右2C A 2C,圖所示’於該第-介電層21,之外側置 :晶"「金屬層他’而於該第二介電層21,,及該半導 二曰a之外側置設有一第二金屬層23b,#中該第-金屬層23a,23b係為㈣;或可結合該第Μ% 圖所不之步驟,直接於該半導體晶片22之主動面他上 110593 13 1365020 由第一金屬層23a及第一介電層21,組成之 ^々(ReSln coated c〇pper f〇il),而於該 曰 • 99 ^ db + ^ 丨于眩b日片 , 卜主動面22b上壓合由第二金屬層23b及第二介電 :層21”組成之第二背膠銅箔’且該第二介電層2 : 、穿之開口區210”,又該開口區21〇,,係為該第二金 =3b所封閉,以供容置該半導體晶片22於該開:區 明,如第2C’圖所示;之後以第2C圖所示之結構作說 • ㊈第20圖所示’壓合該第-金屬層23a、第一介電 層21’、第二介電層21,,及第二金屬層23b,使該第一介^ 層21及第一介電層21,,合成一介電層,且該介電層a 係填充於該開口區210”與半導體晶片22之間的間隙中, 並溢流至該半導體晶片22之非主動面抓上以將該半 導體晶片22固定於該介電層21中,其中該介電層21於 該第一金屬層23a侧係為第—表面21a’而於該第二金屬 層23b側係為相對應之第二表面⑽;或壓合前述之第_ 琴及第二背膠銅羯,俾以構成相同之結構。 如第2E圖所不’薄化該第一及第二金屬㉟仏,现, 再以雷射開孔於該介電層21之第一表面仏及第一金屬 層23a上形成有位於該半導體晶片22之電極塾221上的 ’| %層開孔211a ’並以雷射開孔或機械鑽孔形成有至少 一貫穿該第一金Μ Μ 、人各 蜀禮介電層21以及第二金屬層23b 之通孔211b。 如第2F圖所不,接著,利用物理沈積之錢鍍 14 110593 1365020 (spuuering)或化學沈積之無電錄方式以於該第一金屬 層23a、第二金屬層23b、通孔2m、介電層開孔2以、 及電極塾221之部份表面上形成一導電層24,該導電層 24主要作為後述電鏟金屬材料所需之電流傳導路徑,发 可由金屬、合金或沉積數層金屬層所構成,如選自銅、錫、 錄、鉻、鈦及銅-鉻合金等所組群組之其中一者,或該導 電層24係為聚乙炔、聚笨胺或有機硫聚合物等導電高分 子材料。1365020 IX. Description of the Invention: [Technical Field] The present invention relates to an inactive surface of a packaged semiconductor device in which a semiconductor element is embedded for heat dissipation: As electronic products become thinner and lighter, the package substrates used to carry mail components or electronic components need to be reduced. The evolution of semi-conductor technology has developed different package types, such as ball grid: i gr ld Array, intestine, is an advanced semiconductor package (four), which is characterized by the use of a substrate to house a semiconductor wafer. Traditionally, the ball grid array type semiconductor package structure has the purpose of electrically connecting the semiconductor wafer to the substrate in a Flip Ghip mode (4). The connection path is too long and the electrical characteristics cannot be improved, so the performance is limited. 'In addition, the manufacturing cost is increased because the conventional material requires multiple connection interfaces. Ning is able to effectively improve the electrical quality and meet the application of the next generation of products. 'The industry has studied (4) to connect the semi-fourth (four) W buried in the substrate, and can connect the lung energy material path, and reduce signal loss and 汛唬Distortion to improve the ability to operate at high speeds. Referring to Figures 1A to 1C, there is shown a cross-sectional view of a conventional method in which a semiconductor wafer is embedded in a package substrate. As shown in FIG. 1A, first, a first substrate (10) and a second substrate 10b' are provided, wherein the first substrate 1Ga has at least a through opening 110593 1365020. 100 〇•士弟1Β图, the first A substrate i ο a is bonded to the first 'board, and the -conductor wafer 1 is received in the opening 1 of the first substrate 10a and the semiconductor wafer u is fixed to the opening by the bonding material 11 The semiconductor wafer has an active surface Ua and an inactive surface 11b opposite to the active surface 11a, and the active surface 11a has a plurality of electrical (four) 1U for electrically connecting the wiring layer to the semiconductor wafer 11. . As shown in FIG. 1C, a build-up structure 12 is formed on the first substrate 10a and the semiconductor wafer u=moving mountain surface 1U, so that the semiconductor crystal is buried in the first and the first substrate, 1 ( The layered structure b2 at least one dielectric layer 12〇, the number of line-I portions stacked on the dielectric layer (10) is formed in the conductive via hole 122 in the dielectric layer 120, and the conductive blind hole The electrode η electrically connected to the semiconductor wafer u further has a plurality of electrical contacts 塾 (2) on the build-up structure 12, and the electrical connection pads 12 3 are electrically connected to a! 0, the social power r connection 5 The wiring layer 121 is formed on the additional layer, and the solder resist layer 13 is formed on the structure 12, and the anti-friction layer 13 has a plurality of layers to correspondingly expose the electrical contact pads 123. However, in the above method, 'the semiconductor wafer u is provided in the board 10a, and the end of the second board (10), so the semiconductor 曰, the opening of the wide board 1〇3 is seen in the private mountain. The heat generated during operation is not easy to release, and the heat is also increased with the efficiency of the semiconductor wafer. If the method is used, the Β 曰 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 Performance and longevity.曰干]10593 6 Therefore, how to propose a semiconductor chip burying package structure to overcome the problem that the structure is not easy to dissipate heat during the process of the package structure of Baizhi semiconductor has become an urgent problem to be solved in the industry. SUMMARY OF THE INVENTION In view of the above-mentioned deficiencies of the prior art, one of the objects of the present invention is to provide a method for manufacturing a package substrate of a semiconductor device, which is an inactive surface of a bare semiconductor device to achieve a heat dissipation effect. In order to achieve the above object, the present invention provides a method for fabricating a semiconductor device, comprising: providing a dielectric embedded with a semiconductor wafer: 'the semiconductor wafer has an active surface and a corresponding inactive surface And the two active surfaces have a plurality of electrode pads. The two surfaces of the dielectric layer respectively have a first side: a C-metal layer, and the dielectric layer contacts the first surface of the first metal layer to contact the second metal The layer side is the corresponding second table. And the first metal layer is patterned to form a wiring layer on the surface of the dielectric layer, and a wiring layer is formed on the second surface of the dielectric layer; and removing the inactive surface formed on the semiconductor wafer The upper dielectric layer exposes the inactive surface of the semiconductor wafer. According to the above method, the dielectric layer in which the semiconductor wafer is embedded and the first and second metal layers in the basin are formed by: providing a first; a germanium layer and a second dielectric layer An open region is formed in the dielectric layer; the semiconductor is accommodated in the open region of the second dielectric layer: a 'metal layer is disposed on the outer side of the first dielectric layer, and Forming a second all-gross layer on the non-active layer and the inactive surface of the semiconductor wafer, and pressing the first metal layer, the first dielectric layer, the second dielectric layer 110593 7 1365020 and the second metal layer The first dielectric layer is used to fix the semiconductor wafer, wherein the surface of the dielectric layer is formed as a first surface, and the surface layer is in contact with the first gold surface; The surface of the second metal layer is corresponding to the first method, the semiconductor reed is embedded with a semiconductor wafer and a metal layer and the first dielectric reed Zhixi #匕 匕 鈇 鈇 由 由a smectic layer and a second dielectric layer f- a backing copper foil 'and an opening region formed by the second metal ruin; the 丨 electric layer accommodates the semiconductor wafer; the opening area of the electric layer In the plastic copper pig, the 该a the younger brother---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- The electric layer is a first surface, a second surface corresponding to the second metal layer side or a dielectric layer embedded with the semiconductor wafer and the surface having the first surface according to the above method And a method for manufacturing a second metal layer, comprising: providing a second back win copper box composed of a second metal layer and a second dielectric layer, a core dielectric layer having a core dielectric layer opening, and a first metal layer a first adhesive copper pavilion composed of a layer and a first dielectric layer; and the semiconductor crystal is attached to the second dielectric layer of the second adhesive copper The non-active surface, and the core dielectric layer opening corresponds to the semiconductor wafer; pressing the first-back adhesive copper foil, the core dielectric layer, and the second back_1' to make the first dielectric layer and the core dielectric The layer and the second dielectric layer are combined with a dielectric layer, and the semiconductor wafer is fixed to the dielectric, wherein the dielectric layer is a first surface on the side of the first metal layer, and the 110593 8 1365020 The second metal layer side is a corresponding second surface. According to the above method, the dielectric layer in which the semiconductor wafer is embedded and the first and second metal layers on both sides thereof are included: The carrier board is carried in S Hai; the second layer of copper is formed by the 兮 λ Ώ Ώ, and the second layer: the second dielectric layer is placed on the carrier board, at, /::== An open area is formed in the metal layer, and a portion of the surface of the carrier plate is connected to the inactive surface of the carrier layer n aa in the semiconductor phase port region; The core dielectric layer of the core dielectric layer, and the first gold: = copper berth 'where 'the core dielectric layer opening corresponds to half Ϊ Your first adhesive copper case, core dielectric layer, and second back-working copper =: dielectric layer, core dielectric layer and second dielectric layer 曰 曰 to δ 半导体 半导体 半导体 半导体^ η a 疋 疋 疋 忒彡丨 忒彡丨 ' 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥曰 and removing the allowance to expose the inactive surface of the semi-conductive basket. The dry conductor is based on the method described above, the first dielectric layer - the material, and the laser or electricity (four) Semiconductivity = 3 = thermoset dielectric layer. Ding Shou-like non-active surface of the dielectric layer is the non-primary of the sensed conductor chip, according to the above-mentioned method of 'the first dielectric layer and the first And removing the dielectric layer on the semi-moving surface by a process of exposure and development. + According to the above method, the semiconductor wafer includes an adhesive layer to form the semiconductor with an adhesive layer. The wafer manufacturing method, the system Π 0593 9 1365020 includes: providing a carrier plate; the substrate comprises a semi-adhesive layer comprising a plurality of semiconductor wafers; - a person's month + wafer wafer (wafer) on the back of the layer; on the layer; cutting the semiconductor wafer and the adhesive layer; and removing the carrier plate to form a complex one The semi-conducting 占# crystal moon; the semi-conducting layer with the adhesive layer, the Niudaohong Japanese film is buried in the dielectric layer, and the exposed layer is exposed to the occupant layer Floor. , "Go UV first irradiated to remove the semiconductor crystal moon brother - and the second metal layer is copper foil" "Hai first and first layer of the system, including: in the Jie Lei μ, ', . a surface of the electric brother and the first metal layer are opened: a dielectric layer opening and a through hole on the electrode electrode of the semiconductor wafer; and the first metal layer, the second metal layer and the electrode pad Forming a conductive layer on the surface; a material electricity layer / a layer 3 = a third metal layer, and in the through hole;; a space inside the through hole, or the conductive material and the conductive * is a solid conductive via; in this process, a layer corresponding to the electrode of the semiconductor wafer layer is formed: the layer is patterned by the electrode of the day 5, and the non-master & amp corresponding to the semiconductor wafer is formed. ; = L 开 开 开 Μ ^ : layer second opening; shift layer 'and remove the third metal layer, (four) and J two metal layer in the second opening of the resist layer; and remove the first resist layer The first circuit layer is formed on the dielectric layer, and another conductive via hole is formed in the first opening of the dielectric layer to electrically connect the semiconductor chip. Extremely, and = ] 〇 110593 The second surface of the electric t forms the second circuit layer, • :: 复 has a plurality of first-electrical contact 塾, and the::::: circuit layer and number-electricity Contact pad, and the sputum, stomach and formed with a complex 'and second circuit layer. / Electrical 3 ^ electrical connection of the first circuit layer formed with a -J welding ':, layer, 1 a table 0 surface and the first - The surface layer of the circuit layer is correspondingly exposed to the sth second smear layer and is formed with a plurality of surface-opening portions of the dielectric parent: electrical connection (4); or a build-up structure comprising at least - -: The build-up structure includes at least a third dielectric layer on the third layer of the first layer, and a plurality of layers disposed on the first layer:::: three: a blind hole, the second conductive blind hole is electrically connected : 二二二第:导层, and the first gentleman 祖祖弟弟弟三线数Ss,, ° has a reflow layer 7 electrically connected to the third circuit layer A second anti-surface (four) surface is formed on a build-up structure, and a surface of the second one of the dielectric layers is formed to have a first opening, such as a first opening, to expose _ conduction = non::: two:=3 Layers Forming at least one second build-up structure on the second second-layer f layer of the dielectric layer, and forming a second solder resist layer on the first structure And the second build-up structure forms a body 曰 = mouth corresponding to the first opening of the second solder mask to expose the inactive surface of the semi-conductive raft 'the second build-up structure includes at least one fourth 110593 11 1365020 dielectric layer, stacked on the fourth dielectric layer - the fourth dielectric; ^ towel t _. stomach, 's, and a plurality of connections, the third conductive blind hole and electric dyke Connected. Haidi one and the fourth four circuit layers, and the second one: the fourth fourth electrical contact; and in the = flute-μ layer Xuandi two solder mask layer formed a complex number - #孔' (four) should be exposed The fourth electrical property of the second solder mask is formed with a first open surface and an inactive surface. The method of the above-mentioned method is as follows: a core plate is interposed between the first dielectric layer and the second dielectric layer, wherein the core plate is formed with a through hole Providing the semiconductor wafer, the core board is a circuit board or an insulating board having a line, and the core board comprises a resistive frame (Dam) formed on the periphery of the opening of the core board, and the resistive frame is The core board: the method includes: providing a core board having corresponding third and fourth surfaces, and the patterning process is performed to form a fifth circuit layer on the third surface of the core board, and Forming a sixth circuit layer and a resistive plastic frame on the fourth surface; forming a second resist layer on the fourth surface; and forming a second resistive layer on the fourth surface to expose the sixth circuit layer of the fourth surface Thinning the fifth circuit layer and the sixth circuit layer not covered by the second resist layer to become the fifth thinned circuit layer and the sixth thinned circuit layer, so that the copper foil thickness of the resistive plastic frame is higher than The fifth and sixth thinned circuit layers; and removing the second resist layer, The barrier in the space surrounded by the plastic frame structure formed in the core board through the openings of the core board. In the present invention, the semiconductor wafer is embedded in the first dielectric layer and the second dielectric layer 110593 12 1365020, and the first and second layers are formed on the first and second dielectric layers. A circuit layer is electrically connected to the semiconductor wafer, and the non-active surface of the bare, ancient, and zero-pieces enables the heat generated by the semiconductor wafer to be effectively dissipated, and the heat dissipation effect is achieved. [Embodiment] The second embodiment of the present invention is described in order to make it possible to easily understand the technical features of the present invention. [First Embodiment] Sealed to 2L. A schematic cross-sectional view of a method of manufacturing a package substrate in which a semiconductor element is embedded. - 22 22: not 'first' provides - the first dielectric layer 21, and the second: the second dielectric layer 21, and is formed with - through the eighth coin, and the second dielectric Layer 21, the fluidity after heating is lower than that of the 4th dielectric layer 21. The semiconductor chip 22 has an active surface 22a and a non-active surface complex electrode corresponding thereto in the open area 210" of the second dielectric layer 21". 221. The moving surface 22a has a right 2C A 2C, and the figure is shown in the first dielectric layer 21, the outer side is: crystal " "metal layer" and the second dielectric layer 21, and the half A second metal layer 23b is disposed on the outer side of the second electrode, and the first metal layer 23a, 23b is (4); or may be combined with the step of the second electrode, directly on the semiconductor wafer 22 On the surface 110593 13 1365020 consists of a first metal layer 23a and a first dielectric layer 21, which is composed of a 々 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 a second adhesive copper foil 'composed of the second metal layer 23b and the second dielectric layer 21' and the second dielectric layer 2: the opening region 210" And the opening area 21〇 is closed by the second gold=3b for accommodating the semiconductor wafer 22 in the opening area, as shown in FIG. 2C′; and then shown in FIG. 2C Structure Description • The first metal layer 23a, the first dielectric layer 21', the second dielectric layer 21, and the second metal layer 23b are pressed to form the first dielectric layer as shown in FIG. 21 and the first dielectric layer 21, An electrical layer, and the dielectric layer a is filled in a gap between the opening region 210" and the semiconductor wafer 22, and overflows to the inactive surface of the semiconductor wafer 22 to fix the semiconductor wafer 22 to the semiconductor wafer 22 In the dielectric layer 21, the dielectric layer 21 is a first surface 21a' on the side of the first metal layer 23a and a corresponding second surface (10) on the second metal layer 23b side; or press the foregoing The _ piano and the second adhesive copper enamel, to form the same structure. As shown in FIG. 2E, the first and second metals 35 are not thinned. Now, a laser opening is formed on the first surface of the dielectric layer 21 and the first metal layer 23a. a '|% layer opening 211a' on the electrode 221 of the wafer 22 and formed by laser opening or mechanical drilling at least one through the first metal layer, the human dielectric layer 21, and the second metal The through hole 211b of the layer 23b. As shown in FIG. 2F, the physical deposition of 14 110593 1365020 or chemical deposition is performed on the first metal layer 23a, the second metal layer 23b, the via 2m, and the dielectric layer. A conductive layer 24 is formed on the surface of the opening 2 and the electrode 221, and the conductive layer 24 is mainly used as a current conducting path required for the metal material of the electric shovel to be described later, and may be made of a metal, an alloy or a plurality of metal layers. The composition is, for example, one selected from the group consisting of copper, tin, copper, titanium, copper and chromium alloys, or the conductive layer 24 is high in electrical conductivity such as polyacetylene, polystyrene or organic sulfur polymer. Molecular material.

如第2G及2G’圖所示’於該導電層24表面電鍍形成 有一第三金屬f 23c,並於該通孔2Ub中形成有導電通 孔26’如第2G圖所示’其中該第三金屬層23。之材料係 如船、錫、銀、銅、金、纽、錄、鋅、錄、錯、鎮、銦: 碲以及鎵等金屬之其中—者;惟,依實際操作之經驗,由 於銅為成熟之該材料且成本較低,因此,該第三金屬層 2—3c以由電鍍銅所構成者為較佳,但非以此為限;之後曰, 真充.^電或不導電之填充材料260(如銅或環氧樹脂 以填滿該導電通孔26内部;或於該通孔211b中電蘇 形成只心導電通孔26’,如第2(J,圖所示;之後以第跖: 所示之結構作說明。 m 如第2H圖所示,於該第三金屬層23c之表面利 刷、旋塗或貼合等方式形成第-阻層27,該第一阻層27 係為乾膜或液g光阻等触層,且該第-阻層27再^由 光顯衫等之圖案化製程而形成有複數阻層第一開口 270a及一阻層第二開σ 27此,其中該阻層第一開口 Π0593 】5 1365020 形成有第二開口 294,以露出該半導體晶片22之非主動 面22b,該第二增層結構29”係包括有至少 ,,、曼置於該第四介電層謂,,上之第四線路層;9;,層 ^複數設於第四介電層謂,,中之第三導電盲孔撕,,复 中部份之第三導雷言$ 9〇9, 〃 292並笔性連接該第二線路層 及第四、桌路層291,,’且該第二增層結構29” 數第四電性接觸勢复 接觸墊293,復於該第二增層結構29”上形成 有第一防烊層29b’且該苐二防輝層咖並 &gt; 口 291b,以對;s嗲坌_描a #碰n ,弟開 構29’之第二開口 294,並 丑&quot;¥體晶片22之非主動面22b,又該 挪中形成有複數個第二開孔咖以對應露出:第3 性接觸墊293”之部分表面。 扣^弟四包 [第二實施例] 埋有:ί:弟Γ至3D圖及第“至4J圖’係為本發明嵌 埋有2體4之封裝基板製法的第二實施例剖視圖。 了先’請參閱第3A至31)圖,係使半導體晶片 動面上形成有黏著層之製法。 =3A _示’首先’提供—承載平板3〇,並於該 承載千板30上形成有—黏著層3卜該黏著層μ係由一 加熱後易去除或利用UV光照後易去除之材料所组成。 如第3B圖所示,將該具有複數半導體晶片&amp; 體晶圓2的背面貼合於該黏著層31上。 如第3C圖所示,切割該半導俨曰 α脾道蝴日 牛钕粗日日囫2及黏著層31, 以將斜導體晶圓2分割成複數半導體晶片〜 110593As shown in the 2G and 2G' drawings, a third metal f 23c is formed on the surface of the conductive layer 24, and a conductive via 26' is formed in the through hole 2Ub as shown in FIG. 2G. Metal layer 23. The materials are such as ship, tin, silver, copper, gold, New Zealand, recorded, zinc, recorded, wrong, town, indium: metal such as germanium and gallium; however, due to practical experience, copper is mature The material is lower in cost. Therefore, the third metal layer 2 - 3c is preferably made of electroplated copper, but is not limited thereto; after that, the filling material is electrically or non-conductive. 260 (such as copper or epoxy to fill the inside of the conductive via 26; or in the through hole 211b, the saddle forms a center-only conductive via 26', as shown in the second (J, figure; after the third The structure shown is as follows: m. As shown in FIG. 2H, a first resist layer 27 is formed on the surface of the third metal layer 23c by brushing, spin coating or bonding, and the first resist layer 27 is a contact layer such as a dry film or a liquid photoresist, and the first resist layer 27 is formed by a patterning process such as an optical display to form a plurality of resistive layer first openings 270a and a resistive layer second opening σ 27 The first opening Π 0593 】 5 1365020 of the resist layer is formed with a second opening 294 to expose the inactive surface 22 b of the semiconductor wafer 22 , and the second build-up structure 29 ′′ Including, at least, the man placed on the fourth dielectric layer, the fourth circuit layer; 9; the layer is set in the fourth dielectric layer, and the third conductive blind hole is torn, The third lead of the complex part is $9〇9, 〃292 and the second line layer and the fourth and table layer 291 are connected penically, and the second layered structure 29 is the fourth. The electrical contact potential contact pad 293 is formed on the second build-up structure 29" to form a first anti-mite layer 29b' and the second anti-glaze layer is </b> Drawing a ##n, the second opening 294 of the brother's opening 29', and ugly&quot; the inactive surface 22b of the body wafer 22, and a plurality of second opening holes are formed in the movement to correspondingly expose: 3rd Part of the surface of the contact pad 293". The second package of the button is attached [Second embodiment] buried: ί: Dior to 3D and "4J" is a package substrate with 2 bodies embedded in the invention. A cross-sectional view of a second embodiment of the method. First, please refer to Figs. 3A to 31, which is a method for forming an adhesive layer on a moving surface of a semiconductor wafer. = 3A _ shows 'first' provides a carrying plate 3 〇 The bearer The adhesive layer 3 is formed of a material which is easily removed after heating or easily removed by UV illumination. As shown in FIG. 3B, the semiconductor wafer &amp; The back side of the wafer 2 is attached to the adhesive layer 31. As shown in Fig. 3C, the semi-conductive 俨曰 脾 道 蝴 蝴 日 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及2 split into multiple semiconductor wafers ~ 110593

\JL\J 如第3D圖所示,移除該 主動面具有黏著層31之半;體”板3〇’以形成複數非 接著,請參閱第4A至4/&quot;圖阳 體元件之封裝基板製法的第二/為本發明嵌埋有半導 -實施例…處在該半導二:例剖面示意圖,與該第 形成有-黏著層。 之非主動面上復包括 圖:示,首先’提供-第-介電層21,及第 :广,,中並形成有-貫穿之開 非主動容設該 一介恭爲01, 者層31之+導體晶片22,並於該第 -人::《外侧置設有-第-金屬層23a,而於該第 :二=21”及該半導體晶片22之黏 一金屬層23b。 π 矛 如第4B圖所示,獻人松 „ 0 该第一介電層21,與該第二介 丰電層21以固定該半導體晶片22,此處該 八-晶片22之非主動面2訃貼合有黏著層31,其係與 不八親和性,故溢勝僅形成於該半導體晶片22 曰_主動面22b的周緣,而不致於全面性地形成於半導體 『片22之非主動面咖,故有利於後續清除半導體晶片 C之非主動面22b之介電層。 衣法之第4C至圖的製程係與第一實施例中之第 E至2J圖相同,故不再贅述。 如第41圖所示,移除形成於該半導體晶片22之非主 動面22b上之部份介電層21以露出該半導體晶片22之非 19 110593 1365020 23b側係為相對應之第二表面2lb。 如第5D圖所示,之後製程如同 之第2E”K圖’以於該介電層21 :第二第一實施例 成有第-線路層28a,並電性連接 上形 於該介電層21 線路層28a,而 疋弟一表面21b卜郴士本 28b,且形成有—導帝 形成有第二線路層 28a及第二、, 連接该苐一線路層 矛跟路層28b’亚且露出該本遙 動面22b。 出。玄+蛉體晶片22之非主 [第四實施例] 請參閱第6A至6D圖,係為太恭B日七 A ^ '為本4明嵌埋有半導體元件 之封褒基板I法弟四貫施例的剖面示意圖。 如第6A圖所示,首弈,担碰 ^,c 9nn L 先k供一承載板200,於該承 二上設有由第二金屬層咖及第二介電層21,,組成 之弟一背膠銅領,該第二背膠㈣以其第二金屬層⑽ 接置於該承載板200上,且於該第二背膠銅落中形成有— 開口區210” ’以露出該承載板2〇〇之部份表面。 如第6B圖所示,於該開口區21〇,,中之承載板2〇〇上 接置-半導體晶月22’該半導體晶片22具有—主動面… 及與其相對應之非主動面22b,於該主動面22a具複數電 極墊221,且该半導體晶片22以其非主動面22b接置於 该承載板200上,再提供具有核心介電層開口 4〇〇之核心 介電層40、以及由第一金屬層2 3a與第一介電層21,組成 之第一背膠銅箔,其中,該核心介電層開口 4〇〇對應該半 導體晶片22。 21 】10593 1365020 圖所示’接著’壓合該第—背糊、核心 = 4。、及第二背糊,使該第一介電層21,、核心 • ;:!40及第二介電層21”合成-介電層21,以將該半 導:曰片22固定於該介電層21中,然後移除該承載板 出該半導體晶片22之非主動面咖;其中該介 二:於該第一金屬層23“則係為第-表面2la,而於 μ弟一金屬層23b侧係為相對應之第二表面 =第6D圖所示,t後製程如同與本發明第一實施例 E至2K圖,以於該介電層21之第一表面…上形 線路層28a,而於該介電層21之第二表面抓 升=成有第二線路層28b,且形成有一導電通孔26以電 =接該第-線路層28a及第二線路層咖,並且露出該 +導體晶片22之非主動面22b。 [第五實施例] °月參閱第7A至7C圖,係為本發明嵌埋有半導體元件 '亍裝基板製法弟五貫施例的剖面示意圖,與該第一實施 例之不同處在本實施例係具有一核心板。 如第7A圖所示,首先,提供第一介電層21,、核心 :反50以及第二介電層21”,其中,該核心板5〇係為具有 之線路板或絕緣板,且5玄核心板5 〇具有第三表面5 〇 a 及相對應之第四表面50b,該核心板50之第三表面50a 上形成有第五線路層51a,而於該第四表面5〇13上形成有 第/、線路層51 b,該核心板50並形成有一貫穿該第三表 面5〇a及第四表面50b之核心板開口 500,而於該第二介 ]10593 22 1365020 毛層21中亦形成有一貫穿之開口區21 〇,,,於該核心板 •開口 500及第二介電層21,,之開口區21〇”中置設半導體晶 -片22,且於該第一介電層21,之外側置設有一第一金屬層 23a’而於έ亥第二介電層21,,及該半導體晶片以之非主動 面22b設有第二金屬層23b。 如第7B圖所示’壓合該第—金屬層化、第一介電 層X,、核心板5〇、第二介電層21,,及第二金屬層2%, 使該第一介電層21,及第二介電層2ι,,合成一介電層Η , «並填充於該核心板5G之心板開口⑽與半導體晶片Μ 之間的間隙中,且該介電層21溢流至該半導體晶片22 之非主動面22b上,以將該半導體晶片22固定於該介電 - 中中°亥;|電層21於該第一金屬層23a側係為第 表面21a而於5玄第二金屬層2儿側係為相對應之二 表面21b。 ★如第7C圖所不,之後製程如同與本發明第一實施例 ❿之第找至2K圖,以於該介電層21之第一表面2ι&amp;上形 成有第、線路層28a,並電性連接該第五線路層5】a,而 Z ”電層21之第二表面训上形成有第二線路層 ’並電性連接該第六線路層51b,且形成有—導電通 X包眭連接s玄第一線路層28a及第二線路層28b, 並且露出該半導體晶片22之非主動面22b。 [第六實施例] 多閱第8A至8D圖及第9A至9D圖,係為本發明嵌 埋有半導體元件之封裝基板製法第六實施例的剖面示意 110593 23 1365020 第五實施例之不同處在於核心板具有一阻膠框,且該半導 體晶片之非主動面上形成有黏著層。 如第9A圖所示,提供一第一介電層2丨,、核心板5〇 .以及第二介電層21,,’其中該核心板5〇具有第三表面5〇a 及相對應之苐四表面50b,於該核心板50之第三表面5〇a 上形成有第五線路層51a,而於該第四表面50b上形成有 第六線路層51b及阻膠框51c,該核心板5〇並形成有一 貝穿孩第二表面50a及第四表面50b之核心板開口 5〇〇, 籲而於該第二介電層21”中亦形成有—貫穿之開口區 21〇”,於該核心板開口 500及第二介電層21,,之開口區 210”中置設半導體晶片22,其中,該開口區21〇”較佳應 大於該阻膠框51c的外緣,以避免後續壓合製程中,該第 二介電層21”溢流至該半導體晶片22之非主動面22b,該 半導體晶片22具有黏著層31,且於該第一介電層21,之 外側置設有一第一金屬層23a,而於該第二介電層21,,及 着该半導體晶片22之非主動面22b設有第二金屬層23b。 如第9B圖所示,壓合該第一金屬層23a、第一介電 層21’、核心板50、第二介電層21,,及第二金屬層2讣, 使該第一介電層21’及第二介電層21”合成一介電層21並 填充於該核心板50之核心板開口 500與半導體晶片22 之間的間隙中,以將該半導體晶片22固定於該介電層 21,且該核心板50之阻膠框51c接觸於該第二金屬^ 23b。 a 如第9C圖所示,後續之製程如與第二實施例中之第 110593 25 !365020 4C至4H圖之圖案化線路製程,以露出該半導體晶片μ .之非主動面22b上之黏著層31。 ^如第9D圖所示,藉由加熱或UV光照射之方式,移除 半導阮日日片22之非主動面22b上之黏著層31,以露出 6亥半導體晶片22之非主動面22b。 最後,如同第一實施例,復可於該介電層之表面及線 路層上形成防焊層與增層結構。 本發明係將半導體晶片嵌埋於第一介電層及第二介 φ :層中,且於該第一及第二介電層上分別形成有第一及第 一線路層,使該第一線路層電性連接該半導體晶片,故可 鈿短電性連接路徑,且為防止介電材料壓合後溢流至半導 ,晶片,非主動面上,並藉由該核心板之阻膠框以阻隔溢 T,並藉由裸露出該半導體晶片之非主動面,俾使半導體 晶片所產生之熱量可有效逸散,以達散熱效杲。 惟以上所述之具體實施例,僅係用以例釋本發明之特 點及功效,而非用以限定本發明之可實施範疇,在未脫離 本發明上揭之精神與技術範疇下,任何運用本發明所揭示 内容而完成之等效改變及修飾,均仍應為下述之申請專利 【圖式簡單說明】 型球柵陣型式封裝 第1A至1C圖係顯示習用底穴置晶 結構製法之剖面示意圖·, 第2A至2L圖係顯示本發明嵌埋有半導體元件之 基板製法之剖面示意圖; 、 】]〇593 26 1365020 第2C’圖係為第2A至2C圖合併之另一實施例之剖面 示意圖; ° 第2G’圖係為第2g圖之另一實施例; ’ 第2L圖係為第2L圖之另一實施結構; 第3A至3D圖係顯示本發明嵌埋有半導體元件之封裝 基板製A中具有黏著層之半導體晶片《製法剖二 圖; 思 第4A至4J圖係顯示本發明嵌埋有半導體元件之 φ基板製法之第二實施例剖面示意圖; ’、 第5A至5D圖係顯示本發明嵌埋有半導體元件 基板製法之第三實施例剖面示意圖; ,屐 第6A至6D圖係顯示本發明嵌埋有半 基板製法之第四實施例剖面示意圖; —几之封裝 第7Α至係顯示本發明嵌埋有半導體元 基板製法之第五實施例剖面示意圖; 、裝 第本發明嵌埋有半㈣ 基板製法中具有阻膠框之心板的製^封裝 及 卜思圖,以 第9A至9D係顯示本發明嵌埋有半導雕_ 板製法之第六實施例剖面示意圖。 奴70件之封裝基 【主要元件符號說明】 10a 第一基板 10b 第二基板 100 開口 110593 27 1365020 11 ' 22 半導體晶片 110 結合材料 • 111 、 221 電極塾 :11a 、 22a 主動面 lib 、 22b 非主動面 12 增層結構 120 、 21 介電層 121 線路層 φ 122 導電盲孔 123 電性接觸墊 13 防焊層 130 開孔 ' 2 半導體晶圓 ' 200 承载板 21 介電層 21, 第一介電層 * 21” 第二介電層 210 開口 210” 開口區 211a 介電層開孔 211b 通孔 21a 第一表面 21b 第二表面 23a 第一金屬層 1365020 23b 第二金屬層 23c 第三金屬層 .24 導電層 :26 導電通孔 26, 實心導電通孔 260 填充材料 27 第一阻層 270a 阻層第一開口 φ 270b 阻層第二開口 280a, 第一導電盲孔 281a 第一電性接觸墊 281b 第二電性接觸墊 28a 第一線路層 28b 第二線路層 29, 第一增層結構 29,, 第二增層結構 • 290, 第三介電層 290” 第四介電層 290a 第一開孔 291’ 第三線路層 291” 第四線路層 291b 第一開口 292’ 第二導電盲孔 292” 第三導電盲孔 1365020 292b 第二開孔 293’ 第三電性接觸墊 ;293” 第四電性接觸墊 :294 第二開口 29a 第一防焊層 29b 第二防焊層 30 承載平板 31 黏著層 φ 40 核心介電層 400 核心介電層開口 50 核心板 500 核心板開口 50a 第三表面 50b 第四表面 51a 第五線路層 51a’ 第五薄化線路層 • 51b 第六線路層 51b’ 第六薄化線路層 51c 阻膠框 60 第二阻層 600 開口區域 30 110593\JL\J As shown in Fig. 3D, remove the active surface with half of the adhesive layer 31; body "plate 3" to form a complex number, please refer to the 4A to 4/&quot; package of the male component The second method of the substrate manufacturing method is embedded with a semi-conductive method according to the invention - in the semi-conducting two: a schematic cross-sectional view, and the non-active surface formed by the first-in-a-side layer includes a picture: first, first The 'providing-first-dielectric layer 21, and the first: wide, medium and formed-through-opening non-actively accommodating the first conductor, the conductor layer 22 of the layer 31, and the first person: "The outer side is provided with a -metal layer 23a, and the second: 21" and the adhesion of a metal layer 23b of the semiconductor wafer 22. The π spear, as shown in FIG. 4B, presents the first dielectric layer 21, and the second dielectric layer 21 to fix the semiconductor wafer 22, where the inactive surface 2 of the octa-chip 22 The adhesive layer 31 is bonded to the adhesive layer 31, so that it is formed only on the periphery of the semiconductor wafer 22 主动 active surface 22b, and is not formed comprehensively on the semiconductor "inactive surface of the sheet 22". It is advantageous for the subsequent removal of the dielectric layer of the inactive surface 22b of the semiconductor wafer C. The process of the fourth embodiment of the coating method is the same as that of the first embodiment to the second embodiment, and therefore will not be described again. As shown in FIG. 41, a portion of the dielectric layer 21 formed on the inactive surface 22b of the semiconductor wafer 22 is removed to expose the non-19 110593 1365020 23b side of the semiconductor wafer 22 as a corresponding second surface 2lb. As shown in FIG. 5D, the subsequent process is like the 2E"K" for the dielectric layer 21: the second first embodiment has the first wiring layer 28a, and is electrically connected to the dielectric layer. 21 circuit layer 28a, and a younger face 21b, a gentleman's book 28b, and formed with a second circuit layer 28a Ti ,, a second wiring layer connected to the lance with the path layer 28b 'is exposed, and the present sub-surface movable away 22b. Out. Non-primary of the scorpion + scorpion wafer 22 [Fourth embodiment] Please refer to Figures 6A to 6D, which is a sacred B-day 7 A ^ 'Benefit 4, a semiconductor substrate embedded with a semiconductor device A schematic cross-sectional view of a solution. As shown in Figure 6A, the first game, the touch ^, c 9nn L first k for a carrier board 200, the second metal layer and the second dielectric layer 21, the brother a backing metal collar, the second backing (4) is attached to the carrying board 200 by the second metal layer (10), and an opening area 210"' is formed in the second adhesive copper drop to expose the carrying a portion of the surface of the plate 2A. As shown in FIG. 6B, in the open region 21A, the carrier plate 2 is connected to the semiconductor wafer 22, and the semiconductor wafer 22 has an active surface... The non-active surface 22b corresponding thereto has a plurality of electrode pads 221 on the active surface 22a, and the semiconductor wafer 22 is placed on the carrier board 200 with its inactive surface 22b, and is provided with a core dielectric layer opening. The core dielectric layer 40 and the first adhesive copper foil composed of the first metal layer 23a and the first dielectric layer 21, wherein the core dielectric layer opening 4 corresponds to the semiconductor wafer 22. 21] 10593 1365020 as shown in the figure 'Next' presses the first-back paste, core = 4, and the second back paste, so that the first dielectric layer 21, a core-;:!40 and a second dielectric layer 21" are synthesized-dielectric layer 21 to fix the semiconductor: 22 in the dielectric layer 21, and then the carrier wafer is removed from the semiconductor wafer 22 The non-active face coffee; wherein the second metal layer 23 is "the first surface 2a" and the second side of the metal layer 23b is the corresponding second surface = 6D The process after t is as shown in the first embodiment E to 2K of the present invention, so that the circuit layer 28a is formed on the first surface of the dielectric layer 21, and the second surface is lifted on the second surface of the dielectric layer 21. There is a second wiring layer 28b, and a conductive via 26 is formed to electrically connect the first wiring layer 28a and the second wiring layer, and expose the inactive surface 22b of the + conductor wafer 22. [Fifth Embodiment] Referring to FIGS. 7A to 7C, FIG. 7 is a schematic cross-sectional view showing a fifth embodiment of a semiconductor device embedded with a semiconductor device. The difference from the first embodiment is that a core plate is provided in this embodiment. As shown in FIG. 7A, first, a first dielectric layer 21, a core: a reverse 50, and a second dielectric layer 21" are provided, wherein the core board 5 is The circuit board or the insulating board has a fifth surface 5 〇a and a corresponding fourth surface 50b, and the fifth surface layer 51a is formed on the third surface 50a of the core board 50, and Forming a / / circuit layer 51 b on the fourth surface 5 〇 13 , the core plate 50 is formed with a core plate opening 500 penetrating the third surface 5 〇 a and the fourth surface 50 b , and the second a 10923 22 1365020 is also formed in the batt layer 21 with a through opening 21 〇, and a semiconductor crystal chip is disposed in the opening plate 21 〇" of the core plate opening 500 and the second dielectric layer 21 22, and on the outer side of the first dielectric layer 21, a first metal layer 23a' is disposed on the second dielectric layer 21, and the semiconductor wafer is provided with a second metal on the inactive surface 22b. Layer 23b. As shown in FIG. 7B, 'compressing the first metal layer, the first dielectric layer X, the core plate 5, the second dielectric layer 21, and the second metal layer 2%, so that the first dielectric The electric layer 21, and the second dielectric layer 2, are combined to form a dielectric layer Η, and are filled in a gap between the core opening (10) of the core plate 5G and the semiconductor wafer, and the dielectric layer 21 overflows. Flowing on the inactive surface 22b of the semiconductor wafer 22 to fix the semiconductor wafer 22 to the dielectric layer; the electrical layer 21 is on the side of the first metal layer 23a as the first surface 21a and 5 The side of the second metal layer 2 is the corresponding two surfaces 21b. ★, as shown in FIG. 7C, the subsequent process is as shown in the first embodiment of the present invention to the 2K diagram, so that the first surface 2i&amp; of the dielectric layer 21 is formed with the first, circuit layer 28a, and is electrically The fifth circuit layer 5 a is connected to the fifth circuit layer 5 a, and the second surface layer of the Z ” electrical layer 21 is formed with a second circuit layer ′ and electrically connected to the sixth circuit layer 51 b, and is formed with a conductive X package. The first circuit layer 28a and the second circuit layer 28b are connected to each other, and the inactive surface 22b of the semiconductor wafer 22 is exposed. [Sixth embodiment] Referring to Figures 8A to 8D and Figs. 9A to 9D, A cross-sectional view of a sixth embodiment of a method for fabricating a package substrate in which a semiconductor element is embedded is shown. 110593 23 1365020 The fifth embodiment differs in that the core plate has a resistive plastic frame, and an adhesive layer is formed on the inactive surface of the semiconductor wafer. As shown in FIG. 9A, a first dielectric layer 2丨, a core board 5〇, and a second dielectric layer 21 are provided, wherein 'the core board 5〇 has a third surface 5〇a and a corresponding one. a fourth surface 50b, a fifth wiring layer 51a is formed on the third surface 5〇a of the core board 50, and The fourth surface 50b is formed with a sixth circuit layer 51b and a resistive frame 51c, and the core plate 5 is formed with a core plate opening 5〇〇 of the second surface 50a and the fourth surface 50b. a semiconductor wafer 22 is disposed in the opening region 210" of the core plate opening 500 and the second dielectric layer 21, wherein the second dielectric layer 21" is formed with a through-opening region 21" The opening area 21〇” should preferably be larger than the outer edge of the resistive plastic frame 51c to prevent the second dielectric layer 21” from overflowing to the inactive surface 22b of the semiconductor wafer 22 in the subsequent pressing process. The wafer 22 has an adhesive layer 31, and a first metal layer 23a is disposed on the outer side of the first dielectric layer 21, and the second dielectric layer 21 and the inactive surface 22b of the semiconductor wafer 22 are disposed. A second metal layer 23b is provided. As shown in FIG. 9B, the first metal layer 23a, the first dielectric layer 21', the core board 50, the second dielectric layer 21, and the second metal layer 2 are laminated to make the first dielectric The layer 21' and the second dielectric layer 21" are combined with a dielectric layer 21 and filled in a gap between the core board opening 500 of the core board 50 and the semiconductor wafer 22 to fix the semiconductor wafer 22 to the dielectric. The layer 21 and the resistive plastic frame 51c of the core board 50 are in contact with the second metal 23b. As shown in Fig. 9C, the subsequent process is as shown in Fig. 20593 25!365020 4C to 4H in the second embodiment. The patterning process is performed to expose the adhesive layer 31 on the non-active surface 22b of the semiconductor wafer. ^ As shown in Fig. 9D, the semi-conducting Japanese film is removed by heating or UV light irradiation. The adhesive layer 31 on the non-active surface 22b of the surface 22b is exposed to expose the inactive surface 22b of the semiconductor wafer 22. Finally, as in the first embodiment, a solder resist layer is formed on the surface of the dielectric layer and the wiring layer. And a layered structure. The present invention embeds a semiconductor wafer in a first dielectric layer and a second dielectric layer, and in the first and the The first and first circuit layers are respectively formed on the dielectric layer, so that the first circuit layer is electrically connected to the semiconductor wafer, so that the electrical connection path can be shortened, and the dielectric material is prevented from overflowing to half after being pressed. Conducting, wafer, inactive surface, and blocking the overflow T by the plastic mask of the core board, and by exposing the inactive surface of the semiconductor wafer, the heat generated by the semiconductor wafer can be effectively dissipated, The specific embodiments described above are only used to exemplify the features and functions of the present invention, and are not intended to limit the scope of the present invention, without departing from the spirit and scope of the present invention. In the technical field, any equivalent changes and modifications made by using the disclosure of the present invention should still be the following patent application [Simple Description] Ball grid array type package 1A to 1C shows the bottom of the drawing FIG. 2A to 2L are schematic cross-sectional views showing a method of manufacturing a substrate in which a semiconductor element is embedded in the present invention; 】 〇 593 26 1365020 The 2C' figure is a combination of the 2A to 2C drawings. Another reality Schematic diagram of the embodiment; ° 2G' is another embodiment of the 2g diagram; '2L is another embodiment of the 2L diagram; 3A to 3D shows the semiconductor embedded with the invention A semiconductor wafer having an adhesive layer in the package substrate A of the device is shown in the second section; FIG. 4A to FIG. 4J are schematic cross-sectional views showing a second embodiment of the method for fabricating the φ substrate in which the semiconductor device is embedded in the present invention; ', 5A 5D is a schematic cross-sectional view showing a third embodiment of the method for fabricating a semiconductor device substrate embedding the present invention; and FIGS. 6A to 6D are cross-sectional views showing a fourth embodiment of the method for embedding a semi-substrate according to the present invention; FIG. 7 is a cross-sectional view showing a fifth embodiment of a method for fabricating a semiconductor element substrate in which the present invention is embedded; and a method for fabricating a core plate having a resistive plastic frame embedded in a semi-fourth substrate method. Fig. 9A to 9D are cross-sectional views showing a sixth embodiment of the semi-guided engraving method of the present invention. Slave 70 package base [main component symbol description] 10a first substrate 10b second substrate 100 opening 110593 27 1365020 11 ' 22 semiconductor wafer 110 bonding material • 111, 221 electrode 塾: 11a, 22a active surface lib, 22b non-active Face 12 build-up structure 120, 21 dielectric layer 121 circuit layer φ 122 conductive blind hole 123 electrical contact pad 13 solder mask 130 opening '2 semiconductor wafer' 200 carrier plate 21 dielectric layer 21, first dielectric Layer * 21" Second dielectric layer 210 opening 210" Open region 211a Dielectric layer opening 211b Through hole 21a First surface 21b Second surface 23a First metal layer 1365020 23b Second metal layer 23c Third metal layer. Conductive layer: 26 conductive via 26, solid conductive via 260 filling material 27 first resistive layer 270a resistive first opening φ 270b resistive second opening 280a, first conductive blind via 281a first electrical contact pad 281b Two electrical contact pads 28a first circuit layer 28b second circuit layer 29, first build-up structure 29, second build-up structure 290, third dielectric layer 290" fourth Electrical layer 290a first opening 291' third circuit layer 291" fourth circuit layer 291b first opening 292' second conductive blind hole 292" third conductive blind hole 1365020 292b second opening 293' third electrical contact Pad; 293" Fourth electrical contact pad: 294 Second opening 29a First solder mask 29b Second solder mask 30 Carrier plate 31 Adhesive layer φ 40 Core dielectric layer 400 Core dielectric opening 50 Core plate 500 Core Plate opening 50a third surface 50b fourth surface 51a fifth wiring layer 51a' fifth thinned wiring layer 51b sixth wiring layer 51b' sixth thinned wiring layer 51c plastic resistive frame 60 second resistive layer 600 open region 30 110593

Claims (1)

1365020 第97110932號專利申請案 100年11月22日修正替換頁 十、申請專利範圍: / h 一種嵌埋有半導體元件之封裝基板製法,係包括: 提供一第一介電層、第二介電層 '第一金屬層與 第二金屬層,該第二介電層中形成有一貫穿之開口 區,於該第二介電層之開口區中容設半導體晶片,該 半導體晶片具有一主動面及相對應之非主動面,且該 主動面具有複數電極墊,該主動面與非主動面係外露 於該開口區,該第一介電層係設置於該第二介電層外 • 露該半導體晶片主動面之側,該第一金屬層係設置於 該第一介電層遠離該半導體晶片之側,該第二金屬層 係設置於該第二介電層外露該半導體晶片非主動面 之側; 壓合該第一金屬層 '第一介電層、第二介電層及 第二金屬層,使該第一介電層及第二介電層合成一介 電層以固定與嵌埋該半導體晶片,該介電層之相對二 • 表面分別全面性地覆蓋有該第一金屬層及第二金屬 層,且該介電層接觸於該第一金屬層側為第一表面, 接觸於該第二金屬層側為相對應之第二表面; 對該第一及第二金屬層進行圖案化製程,以於該 二電層之第一表面形成第一線路層,並於該介電層之 第二表面形成第二線路層;以及 屉移除形成於該半導體晶片之非主動面上之介電 2層以露出該半導體晶片之非主動面。 .如申請專利範圍第1項之嵌埋有半導體元件之封裝基 110593(修正版) 31 1365020 第97110932號專利申請案 1〇〇年11月22日^替換苜 板製法’其中’於進行壓合前’該第一介電層與第— 金屬層係已預先結合成一第一背膠銅箔,該第二介電 層與第二金屬層係已預先結合成一第二背膠銅羯;或 者,於進行壓合前,該第一介電層與第一金屬層係各 自獨立而分離’該第二介電層與第二金屬層係各自獨 立而分離。 3. 如申請專利範圍第1項之嵌埋有半導體元件之封裝基 板製法,其中,該第一介電層及第二介電層係為熱固 性材料,且係以雷射或電漿移除該半導體晶片之非主 動面上的介電層。 如申請專利範圍第1項之嵌埋有半導體元件之封裝基 板製法,其中’該第一介電層及第二介電層係為感: 性材料,且係以曝光顯影之製程移除該半導體晶片之 非主動面上的介電層。 5. 如申請專利範圍第1項之❸里有半導體元件之封裝基 :製法,復包括於該介電層之第一表面與該第一線: 形成有一第一防焊層,該第一防焊層並形成有 複數第-開孔,以露出該部份之第—線路層,而 複數第一電性接觸墊。 … 6. =^專鄕圍第1項之餘有半導體S件之封裝基 上=二!:括於該介電層之第一表面及第-線路層 彤成第〃一第一增層結構’並於該第-增層結構上 防焊層,該第一增層結構係包括有至少-第 二,,電層、形成於該第三介電層上之第三線路層、及 110593(修正版) 32 丄邮020 第97110932號專利申請案 100年11月22日修正替換| 诘缸π上从你_ 干日修正替換i : 灵數形成於第三介電層中之第二導電 ...1盲孔並電性連接該第-及第三線路層,且最外層之 該第三線路層具有複數第三電性接觸墊並於該 • g層結構上形成有第-防焊層,該第-防焊層;= ^數第—開孔,以對應露出該第三電性接觸塾之部 分表面。 7. 如申請專利範圍第i項之嵌埋有半導體元件之封裝基 φ =製法,復包括於該介電層之第二表面與該第二線ς =二成有一第二防焊層’該第二防焊層形成有複 第開孔以露出該第二線路層之部份表面,以成為 第-電性接觸墊,且該第二防焊層並形成有第一開 口,以露出該半導體晶片之非主動面。 8. 專利範圍第1項之嵌埋有半導體元件之封裝基 衫法,復包括於該介電層之第二表面及第二線路層 形成至少一第二增層結構,並於該第二增声社 層,且該第二增層結構與第二防焊°層並 〜之第―開口與第-開口’以露出該半導體 曰日片之非主冑面,該第二增層肖構係包括有至少一第 四電層、形成於該第四介電層上之第四線路層、及 複數形成於第四介電層十之第三導電盲孔,該i三導 電盲孔並電性連接該第二及第四線路層,且最外狀 該第四線路層具有複數第四電性接觸墊,並於該第二 成有第二防焊層,該第二防焊層中形成 第二開孔,以對應露出該第四電性接觸墊之部 110593(修正版) 33 1365020 9. 第97110932號專利申請案 100年11月22日修正替換頁 分表面。 一種嵌埋有半導體元件之封裝基板製法,係包括: · 提供一第一介電層、第二介電層、第一金屬層與 - 第二金屬層’該第二介電層中形成有一貫穿之開口 區’於該第二介電層之開口區中容設半導體晶片,該 半導體晶片具有一主動面及相對應之非主動面,該非 主動面上預先形成有黏著層’且該主動面具有複數電 極塾’該主動面與黏著層係外露於該開口區,該第一 介電層係設置於該第二介電層外露該半導體晶片主籲 動面之侧’該第一金屬層係設置於該第一介電層遠離 該半導體晶片之側,該第二金屬層係設置於該第二介 電層外露該半導體晶片非主動面之側; 壓合該第一金屬層、第一介電層、第二介電層及 第二金屬層’使該第一介電層及第二介電層合成一介 電層以固定與嵌埋該半導體晶片’該半導體晶片之非 主動面係藉由該黏著層以接置該第二金屬層,該介電 層之相對二表面分別全面性地覆蓋有該第一金屬層 及第二金屬層,且該介電層接觸於該第一金屬層側為 第一表面,接觸於該第二金屬層側為相對應之第二表 面,該黏著層係與介電層不具親和性,故溢流之該介 電曰係开^成於該半導體晶片之非主動面的周緣,而不 致於全面性地形成於半導體晶片之非主動面.; 八對該第一及第二金屬層進行圖案化製程,以於該 電層之第一表面形成第一線路層,並於該介電層之 110593(修正版) 34 1365020 第97110932號專利申請案 100年11月22曰修正替換百 第二表面形成第二線路層;以及 移除形成於該半導體晶片之非主動面上之黏著 層以露出該半導體晶片之非主動面。 10.如申請專利範圍第9項之嵌埋有半導體元件之封裝基 板製法,其中,於進行壓合前,該第一介 盥^二 金屬層係已預先結合成一第一背膠銅箔,該第二介電 層與第二金屬層係已預先結合成一第二背膠銅箱;或 者,於進行壓合前,該第一介電層與第一金屬層係各 自獨立而分離,該第二介電層與第二金屬 立而分離。 例 11·如申請專利範圍第9項之嵌埋有半導體^件之封以 板製法,其中,係以加熱或uv光照射移除該半導ς 晶片之黏著層。 12.如申請專利範圍第9項之嵌埋有半導體元件之封裝美 板製法’復包括於該介電層之第一表面與該第一線ς 層=形成有一第一防焊層,該第一防焊層並形成有 開孔’以露出該部份之第—線路層,而成為 複數第一電性接觸墊。 13·如申請專利範圍第9項之嵌埋有半導體元件之封裝某 =二包括於該介電層之第一表面及第一線路; =至&gt;、一第一增層結構,並於該第一增層結構上 形成第-防焊層,該第-增層結構係.包括有至少一第 三介電層、形成於該第三介電層上之第三線路層、及 複數形成於第三介電層中之第二導電盲孔,該第二導 110593(修正版) 35 1365020 第97110932號專利申請案 _100年11月22曰修正替換百 命亡·ε丨斗雨tL + 午1丨月22日修正替換1 :目孔並電性連接該第-及第三線路 s亥第三線路層具有複數第三電性接觸墊,並於該第一 ==亡形成有第一防焊層’該第一防焊層中形成 、表 開孔,以對應露出該第三電性接觸塾之部 14·如申請專利範圍第9項之嵌埋有半導體元件之封裝基 =製法,復包括於該介電層之第二表面與該第二線ς 有一第二防焊層,該第二防焊層形成有複 弟開孔以露出該第二線路層之部份表面,以成為 弟-電性接觸墊,且該第二防焊層並形成有第一開 口,以露出該半導體晶片之非主動面。 15.=Γ利範圍第9項之鼓埋有半導體元件之封裝基 製:,復包括於該介電層之第二表面及第二線路層 =至少一第二增層結構,並於該第二增層結構上 =二防焊層,且該第二增層結構與第二防焊層並 =有對應之第二開口與第一開口,以露出該半導體 日日片之非主動面,該第二增層結構係包括有至少 2電層、形成於該第四介電層上之第四線路層、及 稷數形成於第四介電層中之第三導電盲孔,該第 2孔並電性連接該第二及第四線路層,且最外層之 路層具有複數第四電性接㈣,並於該第二 ^二構上形成有第二防焊層,該第二防焊層中形成 分I面第二開孔’以對應露出該第四電性接觸墊之部 110593(修正版) 36 1365020 ___ * 第97110932號專利申請案 ' 1〇〇年11月22日修正替換^ 16. —種嵌埋有半導體元件之封裝基板製法,係包括: .,· 提供一具有核心介電層開口之核心介電層,於該 . 核心介電層開口中容設半導體晶片,該半導體晶片具 有一主動面及相對應之非主動面,且該主動面具有複 數電極塾’該主動面與非主動面係外露於該核心介電 &quot; 層開口; 提供一第一介電層、第二介電層、第一金屬層與1365020 Patent Application No. 97110932 Revised November 22, 2010 Replacement Page 10, Patent Application Range: / h A method of manufacturing a package substrate embedded with a semiconductor component, comprising: providing a first dielectric layer, a second dielectric a first metal layer and a second metal layer, wherein the second dielectric layer is formed with an opening region, and a semiconductor wafer is disposed in the opening region of the second dielectric layer, the semiconductor wafer has an active surface and Corresponding non-active surface, the active surface has a plurality of electrode pads, the active surface and the inactive surface are exposed in the open area, and the first dielectric layer is disposed outside the second dielectric layer a side of the active surface of the wafer, the first metal layer is disposed on a side of the first dielectric layer away from the semiconductor wafer, and the second metal layer is disposed on a side of the second dielectric layer exposed to the inactive surface of the semiconductor wafer Pressing the first metal layer 'the first dielectric layer, the second dielectric layer and the second metal layer to form a dielectric layer to fix and embed the first dielectric layer and the second dielectric layer Semiconductor wafer, the dielectric layer The second surface is completely covered with the first metal layer and the second metal layer, and the dielectric layer is in contact with the first metal layer side as a first surface, and the second metal layer side is corresponding to the second metal layer side. a second surface; a patterning process for forming the first and second metal layers to form a first circuit layer on the first surface of the second electrical layer and a second circuit layer on the second surface of the dielectric layer And removing the dielectric 2 layer formed on the inactive surface of the semiconductor wafer to expose the inactive surface of the semiconductor wafer. The package base 110593 (revisioned version) in which the semiconductor element is embedded in the first application of the patent scope is in the form of a slab of the slab of the slab of the slab of the slab of the slab of the slab of the slab. The first dielectric layer and the first metal layer are pre-assembled into a first adhesive copper foil, and the second dielectric layer and the second metal layer are combined in advance to form a second adhesive copper; or Before the pressing, the first dielectric layer and the first metal layer are separated from each other independently. The second dielectric layer and the second metal layer are separated from each other independently. 3. The method of claim 1, wherein the first dielectric layer and the second dielectric layer are thermosetting materials and are removed by laser or plasma. A dielectric layer on the inactive surface of the semiconductor wafer. The method for manufacturing a package substrate embedded with a semiconductor device according to claim 1, wherein the first dielectric layer and the second dielectric layer are sensible materials, and the semiconductor is removed by an exposure and development process. A dielectric layer on the inactive surface of the wafer. 5. As claimed in the first paragraph of the patent application, there is a package base of a semiconductor component: a method of fabricating a first surface of the dielectric layer and the first line: forming a first solder resist layer, the first proof The solder layer is formed with a plurality of first-opening holes to expose the first circuit layer of the portion and the plurality of first electrical contact pads. ... 6. =^ 鄕 第 第 第 第 第 第 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体And a solder resist layer on the first build-up structure, the first build-up structure comprising at least a second, an electrical layer, a third circuit layer formed on the third dielectric layer, and 110593 ( Revised Edition) 32 丄 020 020 Patent No. 97110932 Patent Application November 22, 100 Correction Replacement | 诘 π from you _ dry day correction replace i: the number of the second conductive layer formed in the third dielectric layer. ..1 blind hole and electrically connected to the first and third circuit layers, and the third circuit layer of the outermost layer has a plurality of third electrical contact pads and a first solder mask layer is formed on the g layer structure The first solder mask layer is formed by the first solder mask layer to be exposed to the surface of the third electrical contact bump. 7. The package base φ of the semiconductor component embedded in the scope of claim i is a method of manufacturing the second surface of the dielectric layer and the second wire 二=2 to have a second solder resist layer. The second solder resist layer is formed with a plurality of openings to expose a portion of the surface of the second circuit layer to become a first electrical contact pad, and the second solder resist layer is formed with a first opening to expose the semiconductor The inactive surface of the wafer. 8. The package base method of claim 1, wherein the second surface of the dielectric layer and the second circuit layer form at least one second build-up structure, and the second increase is a second acoustic layer, and the second build-up structure and the second solder resist layer and the first opening and the first opening to expose the non-main surface of the semiconductor germanium, the second additive layer The method includes a fourth electrical layer, a fourth circuit layer formed on the fourth dielectric layer, and a third conductive via hole formed in the fourth dielectric layer ten. The i-three conductive via hole is electrically connected. Connecting the second and fourth circuit layers, and the outermost shape of the fourth circuit layer has a plurality of fourth electrical contact pads, and the second solder layer is formed in the second, and the second solder resist layer is formed Two openings are provided to correspondingly expose the portion of the fourth electrical contact pad 110593 (Revised Edition) 33 1365020 9. Patent No. 97110932 is amended on November 22, 100. A method for manufacturing a package substrate embedded with a semiconductor component, comprising: providing a first dielectric layer, a second dielectric layer, a first metal layer and a second metal layer, wherein the second dielectric layer is formed with a through hole The open area of the second dielectric layer accommodates a semiconductor wafer having an active surface and a corresponding inactive surface, the active surface being pre-formed with an adhesive layer and having an active surface a plurality of electrodes 塾' the active surface and the adhesive layer are exposed in the open area, the first dielectric layer is disposed on the side of the second dielectric layer exposed to the main surface of the semiconductor wafer. The first metal layer is disposed The second metal layer is disposed on a side of the second dielectric layer that exposes the inactive surface of the semiconductor wafer; and the first metal layer is laminated, the first dielectric layer is disposed on the side of the first dielectric layer away from the semiconductor wafer a layer, a second dielectric layer, and a second metal layer 'the first dielectric layer and the second dielectric layer are combined into a dielectric layer to fix and embed the semiconductor wafer. The inactive surface of the semiconductor wafer is used by The adhesive layer is connected to the second a metal layer, the opposite surfaces of the dielectric layer are respectively covered with the first metal layer and the second metal layer, and the dielectric layer is in contact with the first metal layer side as a first surface, contacting the first surface The side of the two metal layers is a corresponding second surface, and the adhesive layer has no affinity with the dielectric layer, so the dielectric raft which overflows is formed on the periphery of the inactive surface of the semiconductor wafer, without Formed comprehensively on the inactive surface of the semiconductor wafer; 8 patterning the first and second metal layers to form a first wiring layer on the first surface of the electrical layer, and in the dielectric layer 110593 (Revised) 34 1365020 Patent Application No. 97110932, November 22, pp., mod., the second surface layer is formed by replacing the second surface; and the adhesive layer formed on the inactive surface of the semiconductor wafer is removed to expose the The inactive surface of the semiconductor wafer. 10. The method of manufacturing a package substrate embedded with a semiconductor device according to claim 9, wherein the first dielectric layer is previously combined into a first adhesive copper foil before being pressed. The second dielectric layer and the second metal layer are pre-assembled into a second backing copper box; or, before the pressing, the first dielectric layer and the first metal layer are separated independently, the second The dielectric layer is separated from the second metal. [11] The method of claim 11, wherein the adhesive layer of the semiconductor wafer is removed by heating or uv light irradiation. 12. The method of manufacturing a packaged semiconductor device embedding a semiconductor device according to claim 9 of the invention, wherein the first surface of the dielectric layer and the first wire layer are formed with a first solder resist layer, the first A solder mask is formed with an opening 'to expose the first circuit layer of the portion to become a plurality of first electrical contact pads. 13. The package of embedded semiconductor component of claim 9 is included in the first surface of the dielectric layer and the first line; = to &gt;, a first build-up structure, and Forming a first solder mask layer on the first build-up structure, the first build-up layer structure including at least a third dielectric layer, a third circuit layer formed on the third dielectric layer, and a plurality of The second conductive blind hole in the third dielectric layer, the second guide 110593 (revision) 35 1365020 Patent Application No. 97110932 _100 November 22 曰 Correction replaces the death of a hundred deaths ε 丨 雨 rain tL + noon 1丨22日修正Replacement 1 : The eye hole is electrically connected to the third and third lines of the first and third lines, and the third circuit layer has a plurality of third electrical contact pads, and the first prevention is formed in the first == a soldering layer is formed in the first solder resist layer to open a portion corresponding to the portion of the third electrical contact 14 14. The package substrate embedded with the semiconductor component in claim 9 of the patent application scope The second surface of the dielectric layer and the second wire have a second solder mask, and the second solder resist layer is formed with a second opening. The exposed portion of the surface of the second wiring layer to be brother - conductive pads, and the second solder resist layer was formed with a first opening to expose the non-active surface of the semiconductor wafer. 15. The patent base of the ninth aspect of the invention is a package substrate of a semiconductor component: a second surface of the dielectric layer and a second circuit layer = at least one second build-up structure, and The second build-up structure has a second solder mask layer, and the second build-up structure and the second solder resist layer have a corresponding second opening and a first opening to expose the inactive surface of the semiconductor day slice. The second build-up structure includes at least two electrical layers, a fourth circuit layer formed on the fourth dielectric layer, and a third conductive via hole formed in the fourth dielectric layer, the second hole And electrically connecting the second and fourth circuit layers, and the outermost road layer has a plurality of fourth electrical connections (four), and a second solder resist layer is formed on the second structure, the second solder resist Forming a second opening of the I-face in the layer to correspondingly expose the portion of the fourth electrical contact pad 110593 (revision) 36 1365020 ___ * Patent Application No. 97110932 'Revision and Replacement on November 22, 1 16. A method of manufacturing a package substrate embedded with a semiconductor component, comprising: providing a core having a core dielectric opening An electrical layer, wherein the semiconductor dielectric layer has a semiconductor wafer having an active surface and a corresponding inactive surface, and the active surface has a plurality of electrodes 塾' the active surface and the non-active surface system are exposed The core dielectric &quot; layer opening; providing a first dielectric layer, a second dielectric layer, a first metal layer and 第二金屬層,該第一介電層係設置於該核心介電層外 露該半導體晶片主動面之侧,該第一金屬層係設置於 該第一介電層遠離該半導體晶片之側,該第二介電層 係設置於該核心介電層外露該半導體晶片非主動面 之侧’该第二金屬層係設置於該第二介電層遠離該半 導體晶片之侧’壓合該第一金屬層、第一介電層、第 w包層及第一金屬層,使該核心介電層、第一介電 層及第二介電層合成一介電層以固定與嵌埋該半導 體晶片,該介電層之相對二表面分別全面性地覆蓋有 該第金屬層及第二金屬層,且該介電層接觸於該第 金屬層侧為第-表面’接觸於該第二金屬層側為相 對應之第二表面; 子〜第及第一金屬層進行圖案化製程,以於該 介電層之第一表面形成第一線路層,並於該介電層: 第二表面形成第二線路層;以及 層 、移除形成於該半導體晶片之非主動面上之介雷 以露出該半導體晶片之非主動面。 110593(修正版) 37 1365020 第97110932號專利申請案 t 9 1〇〇年11月22日修正替換頁 H·如申請專利範圍第16項之喪埋有半f體元件之 基板製法,其中,於進行壓合前,該第一介電層與第 一金屬層係已預先結合成一第一背膠銅镇,該第二介 電層與第二金屬層係已預先結合成一第二背膠銅‘ 箱|或者,於進行壓合前,該第一介電層與第一金屬-層係各自獨立而分離’該第二介電層與第二 各自獨立而分離。 A如申請專利範圍第16項之嵌埋有半導體元件之封裝 基板製法’其令’該第一介電層及第二介電層係為熱鲁 固性材料,且係以雷射或電漿移除該半導體晶片之非 主動面上的介電層。 19·如申請專利範圍第16項之嵌埋有半導體元件之封裝 基板製法’其中’該第一介電層及第二介電層係為感 光性材料,且係以曝光顯影之製程移除該 體 之非主動面上的介電層。 2〇·如申請專利範圍第16項之嵌埋有半導體元件之封裝 基板製法,復包括於該介電層之第一表面與該第一線· 路層表面形成有-苐-防焊層,該第一防焊層並形成 有複數第-開孔,以露出該部份之第一線路層 為複數第一電性接觸墊β 仏如申請專利範圍第16項之喪埋有半導體元件之封農 基板製法,復包括於該介電層之第一表面及第一線ς 層上形成至少-第-增層結構,並於該第一增層結構 上形成第-防焊層,該第—增層結構係包括有至少一 110593(修正版) 38 第97110932號專利申請案 筮二入兩I WO年11月22日修正簪埴苜 二$ g、㈣於該第三介電層上之第三線路層、 於第三介電層中之第二導電盲孔,該第二 導電目孔並電性連接該第一及第三線路層,且最外層 之該第三線路層具有複數第三電性接 一增層結構上形成有第一防煜展μ 於該第 成有複數第一開孔,以對二第-防焊層中形 ^應路出該第二電性接觸墊之 。丨4分表面。 U ni:專利a圍第16項之嵌埋有半導體元件之封裝 製法,復包括於該介電層之第二表面盘該第-線 路層表面形成有一 Μ -奸神a 田一逆第一線 複數第UI * 知層,該第二防谭層形成有 為第::出該第二線路層之部份表面,以成 口,以露出該半導體晶片之非主動面。成有第開 23.^=專利範圍第16項之嵌埋有半導體 復包括於該介電層之第二表面及第二線ί 二二 第二增層結構,並於該第二增層-構 二Γ防焊層,且該第二增層結構與“二 並形成有對應之第二開丨万坪層 體晶片之非主動面,口’以露出該半導 ^ izg ^ ® ~弟一增層結構係包括有至少一 第^電層、形成於該第四介電層上之第四線路声、 及稷數形成於第四介電層申之第三導電盲:一 導電盲孔並電性連接誃 孔,該苐二 夕过筮第—及苐四線路層,且最外芦 之ι第四線路層具有複數 &quot; 二增層結構上形成有第二二藝’並於該第 丨万坪層該第二防焊層中形 110593(修正版) 39 第97110932號專利申請案 | 1〇〇午11月22曰修正替換¥ 成有複數第二開孔,以對應露出該第 部分表面。 一種嵌埋有半導體元件之封裝基板製法,係包括: 提供一半導體晶片、具有核心介電層開口之核心 介電層、具有開口區之第二介電層、及具有開口區之 第二金屬層’該第二介電層係位於該核心介電層與第 二金屬層之間,且該核心介電層之核心介電層開口、 該第二介電層之開口區、及該第二金屬層之開口區係 相對應,於該核心介電層之核心介電層開口'該第二 介電層之開口區、及該第二金屬層之開口區中容設該 半導體晶片,該半導體晶片具有一主動面及相對應之 非主動面,且該主動面具有複數電極墊,該主動面係 外露於該核心介電層開口,該非主動面係外露於該第 二金屬層之開口區; 提供一第一介電層、第一金屬層與承載板,該第 一介電層係設置於該核心介電層外露該半導體晶片 主動面之側,該第一金屬層係設置於該第一介電層遠 離忒半導體晶片之侧,該承載板係設置於該第二金屬 層外露该半導體晶片非主動面之侧,壓合該第一金屬 層、第一介電層、核心介電層、第二介電層、第二金 2層及承載板,使該第一介電層、核心介電層及第二 介電層合成一介電層以固定與嵌埋該半導體晶片,該 介電層之相對二表面分別全面性地覆蓋有該第一金 屬層及第二金屬層’該第二金屬層與非主動面係接置 40 110593(修正版) 1365020 第97110932號專利申請案 100年11月22日修正替換^ 於該承載板上,且該介電層接觸於該第—金屬層 第表面,接觸於該第二金屬層側為相對應之第二表 面; 移除該承載板,以露出該半導體晶片之非主動 面;以及 對該第一及第二金屬層進行圖案化製程,以於該 $電層之第-表面形成第一線路層,並於該介電層: 第二表面形成第二線路層。 25.如申凊專利範圍第24項之嵌埋有半導體元件之封袭 基板製法,其中,於進行壓合前,該第一介電層與第 金屬層係已預先結合成一第一背膠銅箔,該第 電層與第二金屬層係已預先έ士人 . ^ Τ 〇頂无、、合成一第二背膠鋼 麻,或者,於進行壓合前,該第—介電層與第一 ::各自獨立而分離,該第二介電層與第二金 各自獨立而分離。 、 利範圍第24項之叙埋有半導體元件之封農 二生’其卜該第一介電層及第二介電層係為妖 固性材料或感光性材料。 巧…、 27·Ϊ^專利範圍第24項之嵌埋有半導體元件之封褒 dr復包括於該介電層之第-表面與該第-線 :層表面形成有一第一防焊層,該第 = 有複數第-開孔,以露出該部份之第 厂 為複數第-電性接觸墊。 _線路層,而成 28.如申請專利範圍第24項之嵌埋有半導體元件之封裝 41 110593(修正版) ^65020 第 97 丨 100年11月22曰修^描可' 基板剪法 &amp; A L·!^】】月22日修^替換i 層上形成1 該介電層之第- 上形^ h第—增層結構’並㈣第—增層結構 笛成第—防焊層,該第-增層結構係包括有至少— :::電層、形成於該第三介電層上之第三線路層、 歿數形成於第三介電層中之第二導電盲孔,該第一 導電盲孔並電性連接#•第。 一 之Mi 第二線路層,且最外層 4二線路層具有複數第三電性 :::結構上形成有第-防焊層,該第-防痒層= « :: 复數第一開孔,以對應露出該第三電性接觸墊之 分表面。 2=申,專利範圍第24項之喪埋有半導體元件之封褒 二丄反製法’復包括於該介電層之第二表面與該第二線 =面形成有一第二防谭層’該第二防焊層形成有 =第—開孔以露出該第二線路層之部份表面,以成 =電性接觸塾,且該第二防焊層並形成有第-開 口,以硌出該半導體晶片之非主動面。 3〇·:!Π請第24項之嵌埋有半導體元件之封|1 至Γ該介電層之第二表面及第二線路 曰上$成至少一弟二增層4士禮 上开Q隹 a s、.°構,並於该第二增層結構 /成第-防卜層’且該第二增層結構與第二防焊層 =有對應之第二開口與第-開口,以露出該半導 S晶片之非主動面’該第二增層結構係包括有至少一 第四”電層、形成於該第四介電層上之第四線路層、 及複數形成於第四介電層中之第三導電盲孔,該第三 110593(修正版) 42 第97110932號專利申請案 |00年11月22日修正替換苜 導笔盲孔並電性連接該第二及第四線^7^^ 之該第四線路層具有複數第四電性接觸墊,並於該^ 二增詹結構上形成有第二防焊層,該第二防焊層^形 成有複數第二開孔’以對應露出該第四電性接觸塾^ 部分表面。 一種嵌埋有半導體元件之封裝基板製法,係包括: 提供一核心板,該核心板並形成有一貫穿之核心 板開口,於該核心板開口中容設半導體晶片該半導 體晶片具有-主動面及相對應之非主動面,該主動面 具有複數電㈣,且該半導體晶片之厚度大於該核心 板之厚度; 提供一第一介電層、第二介電層、第一金屬層與 第二金屬層,該第二介電層中形成有一貫穿之開口 區,該第一介電層係設置於該核心板外露該半導體晶 片主動面之側,該第一金屬層係設置於該第一介電層 遠離該半導體晶片之側,該第二介電層係設置於該核 心板外露該半導體晶片非主動面之側,該第二金屬層 係設置於該第二介電層遠離該半導體晶片之侧,且使 該第二介電層之開口區對應該半導體晶片,壓合該第 一金屬層、第一介電層、核心板、第二介電層及第二 金屬層’使該第一介電層及第二介電層合成一介電 層’並填充於該核心板開口與半導體晶片之間的間隙 中’以將該丰導體晶片固定與嵌埋於該介電層中,該 介電層之相對二表面分別全面性地覆蓋有該第一金 43 110593(修正版) 屬層及第二金屬層,” 料導體晶片之主動面與非主動 刀別面向該第一金屬層與第二金屬層,且該介電 j觸於該第-金屬層側為第—表面,接觸 金屬層側為相對應之第二表面; 弟一 八j該第一及第二金屬層進行圖案化製程,以於該 “!之第一表面形成第一線路層,並於該介電層之 弟一表面形成第二線路層;以及 I 、移除形成於該半導體晶片之非主動面上之介 層以露出該半導體晶片之非主動面。 請專利範圍第31項之嵌埋有半導體元件之封裝 二板製法:其中,於進行I合前,該第—介電層與第 :::層係已預先結合成一第一背膠鋼箔,該第二介 第二金屬層係已預先結合成一第二背膠銅 m ’於進行壓合前’該第一介電層與第-金屬 各自獨☆獨立而》離’該第二介電層與第二金屬層係 各自獨立而分離β 4 33.^ =利範圍第31項之嵌埋有半導體元件之封裝 其令,該第一介電層及第二介電層係為熱 料’且細雷射或f漿移除該半導體晶片之非 主動面上的介電層。 34.=:ΓΓ第31項之喪埋有半導體元件之封裝 該第一介電層及第二介電層係為感 ‘幻糸以曝光顯影之製程移除該半導體晶片 I非主動面上的介電層。 110593(修正版) 44 1365020 第97110932號專利申請案 1〇〇年11月22日修正替換頁 QC ‘由▲主宙α π m„ 100年11月22曰修正替換ί 35·如申s月專利範圍第31狀後埋有半 基板製法,復包括於兮么帝麻 玫思主 電層之第一表面與該第一線 路層表面形成有一第一防 .有複數第-開孔,以露防焊層並形成 n咕 路出6亥部份之第一線路層,而成 為複數第一電性接觸墊。 36.:ΓΐΓ範=31 _埋有半導體元件之封裝 該介電層之第-表面及第-線路 I形成第^度第一增層結構’並於該第一增層結構 上I成第一防;層,續笛—E3L / L 一 日層、.吉構係包括有至少一 第三/丨電層、形成於該第二介 β&lt;_、 —;丨電層上之第三線路層、 及複數形成於第三介電声中 _ 導雷廿發“ 中第一導電盲孔’該第二 導2孔並電性連接該第一及第三線路層,且最外層 之; 亥第^路層具有複數第三電性接觸塾並於 上形成有第,層,該第一防谭層中形 成有複數第一開孔,以對肩 應露出5亥第二電性接觸墊之 口卩为表面。 3 7 ·如申清專利範圍第q 1 A柢^ / 有半導體元件之封裝 包括於該介電層之第二表面與該第二線 複數第二開孔以露出路Γ二防得層形成有 第一,,泉路層之部份表面,以成 為第-電性接觸墊,㈣第二防谭層並 口,以露“㈣體W之較動心 專利範圍第31項之嵌埋有半導體元件之封裝 土 復包括於該介電層之第二表面及第二線路 110593(修正版) 45 第97110932號專利申請案 100年11月22曰修正替換頁 層上形成至少一笛-描恳沾诚 ^^-22曰修 第一增層結構,並於該第二增 上形成第二防焊層,且兮筮—梯麻认 ^ ^層且該第一增層結構與第二防焊層 亚形成有對應之第二開口盥第一 曰 汗』,、乐開口,以露出該半導 體晶片之非主動面,該第二增層結構係包括有至少一 第四介電層、形成於該第四介電層上之第四線路層、 及複數形成於第四介電層中之第三導電盲孔,該第三 導電盲孔並電性連接該第二及第四線路層,且最外層 之該第四線路層具有複數第四電性接觸墊,並於該^ 二增層結構上形成有第二防焊層,該第二防焊層中形 成有複數第一開孔,以對應露出該第四電性接觸墊之 部分表面。 一種嵌埋有半導體元件之封裝基板製法,係包括: 提供一核心板,該核心板並形成有一貫穿之核心 板開口,於該核心板開口中容設半導體晶片,該半導 體晶片具有一主動面及相對應之非主動面,該主動面 具有複數電極墊,且該半導體晶片之厚度大於該核心 板之厚度’該半導體晶片復包括有一黏著層形成於該 非主動面上; 提供一第一介電層、第二介電層、第一金屬層與 第二金屬層,該第二介電層中形成有一貫穿之開口 區’該第一介電層係設置於該核心板外露該半導體晶 片主動面之侧,該第一金屬層係設置於該第一介電層 遠離該半導體晶片之侧’該苐二介電層係設置於該核 心板外露該半導體晶片非主動面之側,該第二金屬層 110593(修正版) 46 係設置於該第二恭 L -… —— 該第二介電屛/ θ ^離該半導體晶片之側,且使 -金屬芦、‘ 區對應該半導體晶片,壓合該第 金屬層,使Γ第介電層、核心板、第二介電層及第二 層,並填充於該核心板丄二 =電層合成一介電 中,以將該半導濟曰Η η 一半導體晶片之間的間隙 半導體曰y _日日片固定與嵌埋於該介電層中,該 St :非主動面係藉由該點著層以接置該第 有該第二二介電層之相對二表面分別全面性地覆蓋 面!非^㉟及第二金屬層’該半導體晶片之主動 /、 面係分別面向該第-金屬層與第二金屬 :組且該&quot;電層接觸於該第一金屬層侧為第一表面, 二金屬層側為相對應之第二表面,該黏著 層係與介電層不具親和性,故溢流之該介電層係形成 於該半導體晶片之非主動面的周緣,而不致於全面性 地形成於半導體晶片之非主動面; 對該第-及第二金屬層進行圖案化製程,以於該 ^電層之第-表面形成第一線路層,並於該介電層之 苐一表面形成第二線路層;以及 移除形成於該半導體晶片之非主動面上之黏著 層以露出該半導體晶片之非主動面。 40.如申凊專利範圍第39項之礙埋有半導體元件之封裝 基板製法’其中’於進行壓合前,該第一介電層與第 一金屬層係已預先結合成一第一背膠銅箔,該第二介 電層與第二金屬層係已預先結合成一第二背膠銅 110593(修正版) 47 1365020 100年11月22日修正替換百 | η β从口珍止苷換自 箔;或者,於進行壓合前,該第一介電層與第一金屬 層係各自獨立而分離,該第二介電層與第二金屬層係 各自獨立而分離。 41·如申請專利範圍第39項之嵌埋有半導體元件之封裝 基板製法,其中,係以加熱或uv光照射移除該半導 體晶片之黏著層。 42.如申請專利範圍第39項之嵌埋有半導體元件之封裝 基板製法,復包括於該介電層之第一表面與該第一線 路層表面形成有-'第一防焊層,該第一防焊層並形成 有複數第一開孔,以露出該部份之第一線路層,而成 為複數第一電性接觸墊。 第二介電層、形成於該第三介電層上之第 及複數形成於第三介電層t之第二導電盲 導電盲孔並電性連接該第一及第三線路層 之5亥第三線路層具有複數第三電性接觸墊 增層結構上形成有第一防焊層,該第一 成有複數第一開孔,以對應露出該第三電 部分表面。 如申明專利範圍第39項之嵌埋有半導體 基板製法,復包括於該介電層之第二表面 43·如巾料利範圍第39項之嵌埋有半導體元件之封裝 基板製法,復包括於該介電層之第一表面.及第一線路 層上形成至少一第一增層結構,並於該第一增層結構 上形成第一防焊層,該第一增層結構係包括有至少一 二線路層、 孔,該第二 ’且最外層 ,並於該第 防焊層中形 性接觸墊之 元件之封裝 與該第二線 110593(修正版) 48 1365020 第97丨10932號專利申請索 路層表面形成有—笛_ 月22日修正_^ 複數第二開孔—防痒I該第二防痒層形成有 為第二電性接觸:二線路層之部份表面’以成 口、:接觸墊,且該第二防焊層並形成有第—門 45·如申請專之非主動面。 基板製法,復包括於”之嵌埋有半導體元件之封裝 層上形成至少-第一層之第二表面及第二線路 上形成第二防^結構,並於該第二增層結構 並形成有對應之第二開口鱼第一 構弋一防卜層 靜曰u&amp; 興弟開口,以露出該半導 第曰曰人♦動面’該第二增層結構係包括有至少-】:=!、形成於該第四介電層上之第四線路層、 邋㈣ '於第四介電層中之第三導電盲孔,該第三 孔並電性連接該第二及第四線路層,且最外層 之第四線路層具有複數第四電性接觸墊,並於該第-a 增層結構上形成有第-防焊M 、第一 H也風有弟一防&gt;層,该第二防焊層中形成 有複數第二開孔’以對應露出該第四電性接觸墊之部 分表面。 46·如申請專利範圍第39項之嵌埋有半導體元件之封裝 基板製法,該核心板係為具有線路之線路板或絕緣 板。 47.如申請專利範圍第39項之嵌埋有半導體元件之封裝 基板製法,其中,該核心板復包括形成有一設於該核 心板開口周緣之阻膠框,且該具有阻膠框之核心板製 法,係包括: 110593(修正版) 49 1365020 第97110932號專利申請案 100年11月22日修正替換頁 提供一核心板’該核心板具有相對應之第三及第 四表面,經圖案化製程以於該核心板之第三表面上形 成有第五線路層,而於該第四表面上則形成有第六線 路層以及一阻膠框; 於該第四表面上形成第二阻層,且該第二阻層形 成有開口區域以露出該第四表面之第六線路層; 層,使該阻膠框之厚度高於該第五及第 薄化未為该第二阻層所覆蓋之第五線路層與第 /、線路層,以成為第五薄化線路層與第六薄化線路 六薄化線路· 層;以及a second metal layer, the first dielectric layer is disposed on a side of the core dielectric layer exposed to the active surface of the semiconductor wafer, and the first metal layer is disposed on a side of the first dielectric layer away from the semiconductor wafer, a second dielectric layer is disposed on the side of the core dielectric layer exposing the inactive surface of the semiconductor wafer. The second metal layer is disposed on a side of the second dielectric layer away from the semiconductor wafer to press the first metal a layer, a first dielectric layer, a w-th cladding layer and a first metal layer, wherein the core dielectric layer, the first dielectric layer and the second dielectric layer are combined to form a dielectric layer to fix and embed the semiconductor wafer, The opposite surfaces of the dielectric layer are respectively covered with the first metal layer and the second metal layer, and the dielectric layer is in contact with the first metal layer side, and the first surface is in contact with the second metal layer side. Corresponding second surface; the sub-first and first metal layers are patterned to form a first wiring layer on the first surface of the dielectric layer, and a second wiring is formed on the second surface of the dielectric layer a layer; and a layer, removed to form the semiconductor crystal The dielectric on the inactive surface of the sheet exposes the inactive surface of the semiconductor wafer. 110593 (Revised Edition) 37 1365020 Patent Application No. 97110932 t 9 November 22nd Amendment Replacement Page H. The substrate manufacturing method for burying a half-f body component as in claim 16 of the patent application scope, wherein Before the pressing, the first dielectric layer and the first metal layer are pre-combined into a first backing copper town, and the second dielectric layer and the second metal layer are pre-combined into a second backing copper. The box|or, before the press-bonding, the first dielectric layer and the first metal-layer are separated independently of each other' the second dielectric layer and the second each are separated independently. A method for manufacturing a package substrate embedded with a semiconductor device according to claim 16 of the patent application, wherein the first dielectric layer and the second dielectric layer are thermally-lubricated materials, and are laser or plasma The dielectric layer on the inactive surface of the semiconductor wafer is removed. 19. The method of manufacturing a package substrate embedded with a semiconductor device according to claim 16 wherein the first dielectric layer and the second dielectric layer are photosensitive materials, and the process is removed by exposure and development. The dielectric layer on the inactive surface of the body. 2. The method of manufacturing a package substrate embedded with a semiconductor device according to claim 16 of the patent application, comprising: forming a 苐-solderproof layer on the first surface of the dielectric layer and the surface of the first line and the road layer; The first solder resist layer is formed with a plurality of first opening-to-opening holes to expose the first circuit layer of the portion as a plurality of first electrical contact pads β, such as the semiconductor component sealed in claim 16 of the patent application scope. The agricultural substrate manufacturing method further comprises forming at least a first-germ-layer structure on the first surface of the dielectric layer and the first wire layer, and forming a first solder resist layer on the first build-up structure, the first The build-up structure includes at least one 110593 (revision) 38 patent application No. 97110932 筮 two into two I WO year November 22 amended $ two g, (d) on the third dielectric layer a third conductive layer, a second conductive via hole in the third dielectric layer, the second conductive mesh and electrically connected to the first and third circuit layers, and the third circuit layer of the outermost layer has a plurality of third a first anti-cracking layer is formed on the electrical connection layer forming structure, and the first opening has a plurality of first openings Bis - ^ solder resist layer should be formed out of the second passage conductive pads of.丨 4 points surface. U ni: Patent No. 16 of Patent A is a method of encapsulating a semiconductor device, and a second surface plate of the dielectric layer is formed on the surface of the first-line layer of the dielectric layer. The plurality of UI* layers, the second anti-tank layer is formed to be: a portion of the surface of the second circuit layer to be formed in a mouth to expose the inactive surface of the semiconductor wafer. The semiconductor embedded in the semiconductor device of the sixth aspect of the invention is included in the second surface of the dielectric layer and the second second layer of the second layer, and in the second layer - Constructing a second solder resist layer, and the second build-up structure is formed with a corresponding non-active surface of the second open-top layer wafer to expose the semi-conducting ^izg ^ ® The build-up structure includes at least one electrical layer, a fourth line sound formed on the fourth dielectric layer, and a number of turns formed on the fourth dielectric layer, the third conductive blind: a conductive blind hole Electrically connected to the pupil, the second day of the 苐 筮 筮 苐 苐 苐 苐 苐 苐 苐 苐 , , , , , , , , 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四丨万平层 The second solder mask medium shape 110593 (revision) 39 Patent No. 97110932 | 1 noon November 22 曰 correction replacement ¥ has a plurality of second openings to correspondingly expose the first part A method for manufacturing a package substrate embedded with a semiconductor component, comprising: providing a semiconductor wafer with a core dielectric a core dielectric layer having a layer opening, a second dielectric layer having an open region, and a second metal layer having an open region between the core dielectric layer and the second metal layer, and The core dielectric layer of the core dielectric layer, the open region of the second dielectric layer, and the open region of the second metal layer correspond to the core dielectric layer opening of the core dielectric layer The semiconductor wafer is accommodated in the open region of the second dielectric layer and the open region of the second metal layer. The semiconductor wafer has an active surface and a corresponding inactive surface, and the active surface has a plurality of electrode pads. The surface is exposed to the opening of the core dielectric layer, the inactive surface is exposed in the open area of the second metal layer; a first dielectric layer, a first metal layer and a carrier plate are provided, and the first dielectric layer is disposed Exposed on the side of the active surface of the semiconductor wafer, the first metal layer is disposed on a side of the first dielectric layer away from the semiconductor wafer, and the carrier is disposed on the second metal layer to expose the semiconductor Side of the inactive surface of the wafer, pressure The first metal layer, the first dielectric layer, the core dielectric layer, the second dielectric layer, the second gold layer, and the carrier layer, the first dielectric layer, the core dielectric layer and the second dielectric layer Forming a dielectric layer to fix and embed the semiconductor wafer, the opposite surfaces of the dielectric layer are respectively covered with the first metal layer and the second metal layer respectively. The second metal layer is coupled to the inactive surface </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The layer side is a corresponding second surface; the carrier plate is removed to expose the inactive surface of the semiconductor wafer; and the first and second metal layers are patterned to form the first layer of the electric layer The surface forms a first wiring layer, and the dielectric layer: the second surface forms a second wiring layer. 25. The method of claim 24, wherein the first dielectric layer and the third metal layer are pre-bonded into a first backing copper before pressing. The foil, the first electrical layer and the second metal layer have been pre-warriage. ^ 〇 〇 无 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , One: separates and separates, and the second dielectric layer and the second gold are separated from each other independently. In the 24th item of the benefit range, the semiconductor element is buried in the second section. The first dielectric layer and the second dielectric layer are enchanting materials or photosensitive materials. The package of the semiconductor device embedded in the semiconductor device of claim 24 includes a first solder resist layer formed on the first surface of the dielectric layer and the surface of the first wire: No. = There are a plurality of first-opening holes to expose the first part of the part as a plurality of electrical-contact pads. _Circuit layer, made 28. As packaged in the 24th article of the patented semiconductor package 41 110593 (Revised Edition) ^65020 97 丨 100 November 22 曰 ^ 可 ' 'Substrate Shearing &amp; AL·!^]] On the 22nd of the month, the ^ layer is formed to replace the first layer of the dielectric layer, the upper layer is formed, and the fourth layer is formed into a first layer. The first-layered structure includes at least a :::: an electrical layer, a third wiring layer formed on the third dielectric layer, and a second conductive blind via formed in the third dielectric layer. A conductive blind hole and electrically connected #•第. a second second circuit layer, and the outermost layer 4 two circuit layers have a plurality of third electrical properties::: a first anti-welding layer is formed on the structure, the first anti-itch layer = « :: a plurality of first openings, Correspondingly exposing the surface of the third electrical contact pad. 2=申, the patent of the scope of the 24th buried semiconductor component sealing method, the second method of the second layer of the dielectric layer and the second line = surface formed a second anti-tank layer The second solder resist layer is formed with a first opening to expose a portion of the surface of the second wiring layer to form an electrical contact, and the second solder resist layer is formed with a first opening to extract the The inactive surface of the semiconductor wafer. 3〇·:!Please enclose the sealing of the semiconductor component in the 24th item|1 to the second surface of the dielectric layer and the second line to be at least one of the second layer of the second layer.隹as, .°, and in the second build-up structure / into the first - anti-layer layer and the second build-up structure and the second solder mask = corresponding second opening and the first opening to expose The non-active surface of the semiconductor S-chip includes at least a fourth electrical layer, a fourth wiring layer formed on the fourth dielectric layer, and a plurality of dielectric layers formed on the fourth dielectric layer The third conductive blind hole in the layer, the third 110593 (revision) 42 patent application No. 97110932|November 22, 00, the correction of the blind hole of the guide pen and the electrical connection of the second and fourth lines ^ The fourth circuit layer of 7^^ has a plurality of fourth electrical contact pads, and a second solder resist layer is formed on the second soldering layer, and the second solder resist layer is formed with a plurality of second openings And correspondingly exposing the surface of the fourth electrical contact portion. The method for manufacturing a package substrate embedded with a semiconductor component comprises: providing a core board, the core The board is formed with a through-core board opening, and a semiconductor wafer is accommodated in the core board opening. The semiconductor chip has an active surface and a corresponding inactive surface, the active surface has a plurality of electric (four), and the thickness of the semiconductor wafer is greater than a thickness of the core plate; providing a first dielectric layer, a second dielectric layer, a first metal layer and a second metal layer, wherein the second dielectric layer is formed with a through opening region, the first dielectric layer The first metal layer is disposed on a side of the first dielectric layer away from the semiconductor wafer, and the second dielectric layer is disposed on the core plate. a side of the inactive surface of the semiconductor wafer, the second metal layer is disposed on a side of the second dielectric layer away from the semiconductor wafer, and the opening region of the second dielectric layer is corresponding to the semiconductor wafer, and the first a metal layer, a first dielectric layer, a core plate, a second dielectric layer, and a second metal layer 'the first dielectric layer and the second dielectric layer are combined into a dielectric layer' and filled in the core plate opening and Semiconductor wafer The first conductor 43 110593 (revision) layer and the first layer are respectively covered by the opposite surfaces of the dielectric layer. a second metal layer, wherein the active surface and the non-active blade of the material conductor chip face the first metal layer and the second metal layer, and the dielectric j touches the first metal layer side as a first surface, and contacts the metal layer side Corresponding to the second surface; the first and second metal layers are patterned to form a first circuit layer on the first surface of the device, and a surface of the dielectric layer Forming a second wiring layer; and I, removing a via formed on the inactive surface of the semiconductor wafer to expose an inactive surface of the semiconductor wafer. The method for manufacturing a packaged two-plate embedded with a semiconductor component according to the scope of claim 31, wherein the first dielectric layer and the first::: layer are pre-assembled into a first adhesive steel foil before the I-bonding. The second second metal layer has been previously combined into a second backing copper m' before the pressing. The first dielectric layer and the first metal are independent of each other, and the second dielectric layer is separated from the second dielectric layer. Separating the semiconductor element from the second metal layer independently of the semiconductor layer, wherein the first dielectric layer and the second dielectric layer are hot materials and The fine laser or f paste removes the dielectric layer on the inactive surface of the semiconductor wafer. 34.=: The package of the semiconductor device is buried in the 31st item. The first dielectric layer and the second dielectric layer are removed from the inactive surface of the semiconductor wafer by a process of exposure and development. Dielectric layer. 110593 (Revised Edition) 44 1365020 Patent Application No. 97110932 1 November 22nd revised replacement page QC 'Replaced by ▲ main phase α π m„ 100 November 22曰 ί 35·如申s月 patent After the 31st shape, a half-substrate method is embedded, and the first surface of the main layer of the 线路 帝 麻 玫 玫 与 与 与 与 与 与 与 形成 形成 形成 形成 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一The solder layer forms a first circuit layer of the 6-inch portion of the n-way, and becomes a plurality of first electrical contact pads. 36.: ΓΐΓ范=31 _ buried semiconductor device package the first surface of the dielectric layer And the first line I forms a first degree first layer structure 'and the first layer is formed on the first layered structure; the layer, the whistle-E3L / L day layer, the ji system includes at least one a third/tantalum layer, a third circuit layer formed on the second dielectric layer _, _; the 丨 electric layer, and a plurality of formed in the third dielectric sound _ The second hole 2 is electrically connected to the first and third circuit layers, and the outermost layer; the second layer has a plurality of third electrical contacts And formed on the first layer, the first anti-Tan layer formed with a plurality of first openings to be exposed on the shoulder mouth Jie Hai 5 of the second electrical contact pad surface. 3 7 · The scope of the patent patent section q 1 A 柢 ^ / package with a semiconductor component is included in the second surface of the dielectric layer and the second opening of the second line to expose the layer of the barrier layer First, part of the surface of the spring road layer to become the first electrical contact pad, (4) the second anti-tan layer parallel port, to expose the "(four) body W of the temperament patent range of the 31st embedded semiconductor components The encapsulation layer is included in the second surface of the dielectric layer and the second line 110593 (revision) 45. Patent application No. 97110932, November 22, 2005, the replacement page layer is formed to form at least one flute-trace ^^-22 repairing the first build-up structure, and forming a second solder resist layer on the second increase, and the first build-up structure and the second solder resist layer Forming a corresponding second opening 盥 first 曰 sweat, opening a hole to expose an inactive surface of the semiconductor wafer, the second build-up structure comprising at least one fourth dielectric layer formed on the fourth a fourth circuit layer on the dielectric layer, and a plurality of third conductive blind holes formed in the fourth dielectric layer, a third conductive via hole and electrically connected to the second and fourth circuit layers, wherein the fourth circuit layer of the outermost layer has a plurality of fourth electrical contact pads, and a second protection layer is formed on the second layer structure a plurality of first openings are formed in the second solder mask to expose a portion of the surface of the fourth electrical contact pad. The method for manufacturing a package substrate embedded with a semiconductor component comprises: providing a core board The core board is formed with a through-core board opening, and a semiconductor wafer is received in the core board opening, the semiconductor chip has an active surface and a corresponding inactive surface, the active surface has a plurality of electrode pads, and the semiconductor The thickness of the wafer is greater than the thickness of the core plate. The semiconductor wafer includes an adhesive layer formed on the inactive surface; a first dielectric layer, a second dielectric layer, a first metal layer and a second metal layer are provided. An opening region is formed in the second dielectric layer. The first dielectric layer is disposed on a side of the core plate exposed to the active surface of the semiconductor wafer, and the first metal layer is disposed on the first metal layer The second dielectric layer 110593 (modified version) 46 is disposed on the second side of the semiconductor chip L -... —— the second dielectric 屛 / θ ^ away from the side of the semiconductor wafer, and the - metal reed, 'region corresponding to the semiconductor wafer, press-bonded the metal layer, so that the first dielectric layer, the core board a second dielectric layer and a second layer, and are filled in the core plate =2=electric layer to form a dielectric to the gap semiconductor between the semiconductor wafers 曰y_day The sheet is fixed and embedded in the dielectric layer, and the St: inactive surface is fully covered by the point layer to connect the opposite surfaces of the second dielectric layer. The active/surface of the semiconductor wafer faces the first metal layer and the second metal: respectively, and the electrical layer contacts the first metal layer side as a first surface. The second metal layer side is a corresponding second surface, and the adhesive layer has no affinity with the dielectric layer, so the dielectric layer overflowing is formed on the periphery of the inactive surface of the semiconductor wafer without comprehensiveness. Forming on the inactive surface of the semiconductor wafer; patterning the first and second metal layers to form a first wiring layer on the first surface of the electrical layer and on a surface of the dielectric layer Forming a second wiring layer; and removing an adhesive layer formed on an inactive surface of the semiconductor wafer to expose an inactive surface of the semiconductor wafer. 40. The method according to claim 39, wherein the first dielectric layer and the first metal layer are pre-assembled into a first adhesive copper before the pressing is performed. The foil, the second dielectric layer and the second metal layer have been previously combined to form a second backing copper 110593 (revision) 47 1365020 November 22, 100 modified replacement hundred | η β from the mouth of the glycoside exchanged from the foil Or, before the pressing, the first dielectric layer and the first metal layer are separated independently, and the second dielectric layer and the second metal layer are separated independently. The method of manufacturing a package substrate in which a semiconductor element is embedded in claim 39, wherein the adhesive layer of the semiconductor wafer is removed by heating or uv light irradiation. 42. The method according to claim 39, wherein the first surface of the dielectric layer and the surface of the first circuit layer are formed with a first solder resist layer, the first method A solder mask is formed with a plurality of first openings to expose the first circuit layer of the portion to form a plurality of first electrical contact pads. a second dielectric layer, a plurality of second conductive interlayer conductive vias formed on the third dielectric layer, and electrically connected to the first and third circuit layers The third circuit layer has a plurality of third electrical contact pad buildup structures formed with a first solder mask layer, and the first layer has a plurality of first openings to correspondingly expose the surface of the third electrical portion. The method for fabricating a semiconductor substrate embedded in claim 39 of the patent scope is further included in the second surface of the dielectric layer 43. The method for manufacturing a package substrate embedded with a semiconductor device according to item 39 of the scope of the invention is included in Forming at least one first build-up structure on the first surface of the dielectric layer and the first circuit layer, and forming a first solder resist layer on the first build-up structure, the first build-up structure including at least a second circuit layer, a hole, the second 'and outermost layer, and a package of components of the contact pad in the first solder resist layer and the second line 110593 (revision) 48 1365020 Patent No. 97 丨 10932 The surface of the cableway layer is formed with a flute _ _ 22nd correction _ ^ plural second opening - anti-itch I the second anti-itch layer is formed for the second electrical contact: part of the surface of the two circuit layer 'to the mouth And a contact pad, and the second solder resist layer is formed with a first door 45. The substrate manufacturing method comprises: forming at least a second surface of the first layer on the encapsulation layer embedded with the semiconductor element; and forming a second anti-structure on the second line, and forming the second enhancement structure Corresponding to the second open fish first configuration, an anti-layer, static u&amp; Xingdi opening, to expose the semi-conducting third person ♦ moving surface 'the second build-up structure includes at least -】:=! a fourth circuit layer formed on the fourth dielectric layer, and a fourth conductive via hole in the fourth dielectric layer, the third hole is electrically connected to the second and fourth circuit layers, And the fourth circuit layer of the outermost layer has a plurality of fourth electrical contact pads, and a first anti-welding M, a first H, and a second anti-welding layer are formed on the first-a build-up structure, the first A plurality of second openings are formed in the second solder resist layer to correspondingly expose a portion of the surface of the fourth electrical contact pad. 46. The method of manufacturing a package substrate embedded with a semiconductor component according to claim 39 of the patent application scope, the core board It is a circuit board or an insulating board with a line. 47. The embedded semiconductor is embedded in item 39 of the patent application. The method for manufacturing a package substrate, wherein the core plate comprises a resistive frame formed on a periphery of the opening of the core plate, and the core plate having the plastic frame comprises: 110593 (revision) 49 1365020, 97110932 Patent Application No. November 22, 100, revised replacement page provides a core board having a corresponding third and fourth surface, and a patterned process for forming a fifth surface on the third surface of the core board a circuit layer, and a sixth circuit layer and a resistive plastic frame are formed on the fourth surface; a second resist layer is formed on the fourth surface, and the second resist layer is formed with an opening region to expose the fourth a sixth circuit layer of the surface; the layer is such that the thickness of the resistive frame is higher than the fifth and the thinned fifth circuit layer and the //the circuit layer covered by the second resist layer to become the fifth Thinning circuit layer and sixth thinning line six thinning lines and layers; 形成I穿該核心 板之核 並於該阻膠桓所圍構之空間令 心板開口。 110593(修正版&gt; 50Forming a core penetrating the core plate and opening the core in the space surrounded by the resisting film. 110593 (Revised Edition &gt; 50
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