CN104851870B - 封装基板及封装结构 - Google Patents

封装基板及封装结构 Download PDF

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CN104851870B
CN104851870B CN201410089672.4A CN201410089672A CN104851870B CN 104851870 B CN104851870 B CN 104851870B CN 201410089672 A CN201410089672 A CN 201410089672A CN 104851870 B CN104851870 B CN 104851870B
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line layer
package substrate
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layer
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CN104851870A (zh
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林长甫
姚进财
庄旻锦
刘科震
黄富堂
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Siliconware Precision Industries Co Ltd
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Abstract

一种封装基板及封装结构，该封装基板包括多个介电层及多个与各该介电层交互堆栈的线路层，其中，至少二该线路层具有厚度差。本发明能有效避免基板的翘曲现象。

Description

封装基板及封装结构
技术领域
本发明涉及一种封装基板及封装结构，尤指一种包括多个交互堆栈的介电层与线路层的封装基板及封装结构。
背景技术
现行的覆晶技术因具有缩小芯片封装面积及缩短讯号传输路径等优点，目前已经广泛应用于芯片封装领域，例如：芯片尺寸构装（Chip Scale Package，CSP）、芯片直接贴附封装（Direct Chip Attached，DCA）以及多芯片模块封装（Multi-Chip Module，MCM）等型态的封装模块，其均可利用覆晶技术而达到封装的目的。
图1所示者，为现有的覆晶式封装基板的剖视图，如图所示，该封装基板1的内部具有多个线路层11，且各该线路层11的厚度均相同，例如19微米（μm）的厚度。
然而，于覆晶封装制程的温度循环（temperature cycle）测试中，因为芯片与封装基板的热膨胀系数的差异甚大或受热不对称等原因，所以封装基板容易发生翘曲（warpage），导致许多问题，例如：芯片外围的凸块无法与封装基板上对应的接点形成良好的接合，进而使得产品良率降低。
虽然增加所有该线路层的厚度可减缓封装基板的翘曲现象，但却会使得封装基板的整体厚度增加，进而导致最终封装结构的整体厚度增加，不符合现今电子产品的轻薄短小的趋势。
因此，如何避免上述现有技术中的种种问题，实为目前业界所急需解决的课题。
发明内容
有鉴于上述现有技术的缺失，本发明提供一种封装基板及封装结构，能有效避免基板的翘曲现象。
本发明的封装基板包括：多个介电层；以及多个与各该介电层交互堆栈的线路层，其中，至少二该线路层具有厚度差。
本发明还提供一种封装结构，包括：封装基板，其包括多个介电层及多个与各该介电层交互堆栈的线路层，至少二该线路层具有厚度差；以及芯片，其接置于该封装基板的上表面上。
于前述的封装基板与封装结构中，位于或接近该封装基板的上表面的该线路层的厚度大于位于或接近该封装基板的下表面的该线路层的厚度，该上表面与下表面分别为置晶侧与非置晶侧，最接近该上表面的线路层的厚度大于其它所有该线路层的厚度，最接近该下表面的线路层的厚度小于其它所有该线路层的厚度，除最接近该上表面的线路层与最接近下表面的线路层外，其余的线路层具有相同的厚度。
于另一实施例中，该等线路层的厚度由该上表面逐渐往该下表面减少，接近该上表面的半数的线路层的厚度总和大于接近该下表面的半数的线路层的厚度总和。
于本发明的封装基板与封装结构中，该等线路层中的最厚者与最薄者的厚度的比为1.2：1至2：1，该等线路层中的最厚者与最薄者的厚度的比较佳为1.5：1。
所述的封装基板与封装结构中，该等线路层中的最厚者与最薄者的厚度的差为3至15微米，该等线路层中的最厚者与最薄者的厚度的差较佳为5至10微米。
又依上所述的封装基板与封装结构，该等线路层的数量为单数或双数。一该介电层为核心板，且该等线路层以该核心板为中心的方式对称分布于该核心板的相对两表面上。
由上可知，本发明通过调整封装基板中的部分线路层的厚度，使部分线路层的厚度较厚，以增加封装基板的整体刚性，减少基板翘曲的发生；此外，由于部分线路层的厚度较薄，故可使所有线路层的厚度总和不增加，进而能避免封装基板及封装结构的整体厚度增加。
附图说明
图1所示者为现有的覆晶式封装基板的剖视图。
图2所示者为本发明的封装基板的剖视图。
图3所示者为本发明的封装结构的剖视图。
主要组件符号说明
1 封装基板
11、22 线路层
2 封装基板
2a 上表面
2b 下表面
21 介电层
21’ 核心板
31 芯片
32 封装胶体。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
请参阅图2，其为本发明的封装基板的剖视图。如图所示，该封装基板2包括：多个介电层21；以及多个与各该介电层21交互堆栈的线路层22，其中，至少二该线路层22具有厚度差，其中，一该介电层21可为核心板21’，且该等线路层22以该核心板21’为中心的方式对称分布于该核心板21’的相对两表面上。
前述的封装基板中，位于或接近该封装基板2的上表面2a的该线路层22的厚度大于位于或接近该封装基板2的下表面2b的该线路层22的厚度，该上表面2a与下表面2b分别为置晶侧与非置晶侧。
依前所述的封装基板，最接近该上表面2a的线路层22的厚度大于其它所有该线路层22的厚度，最接近该下表面2b的线路层22的厚度小于其它所有该线路层22的厚度，除最接近该上表面2a的线路层22与最接近下表面2b的线路层22外，其余的线路层22具有相同的厚度。例如，该等线路层22的层数为6，该等线路层22的厚度由该上表面2a至该下表面2b分别是26微米、19微米、19微米、19微米、19微米与12微米。
于另一实施例中，该等线路层22的厚度由该上表面2a逐渐往该下表面2b减少。例如，该等线路层22的层数为6，该等线路层22的厚度由该上表面2a至该下表面2b分别是26微米、23微米、19微米、19微米、15微米与12微米。
于另一实施例中，接近该上表面2a的半数的线路层22的厚度总和大于接近该下表面2b的半数的线路层22的厚度总和。例如，该等线路层22的层数为6，该等线路层22的厚度由该上表面2a至该下表面2b分别是26微米、24微米、20微米、18微米、14微米与12微米。
此外，于一实施例中，如图2所示，该等线路层22的层数为6，该等线路层22的厚度由该上表面2a至该下表面2b分别是22微米、22微米、22微米、16微米、16微米与16微米。
又依前所述的封装基板，该等线路层22中的最厚者与最薄者的厚度的比为1.2：1至2：1，该等线路层22中的最厚者与最薄者的厚度的比较佳为1.5：1。
又于所述的封装基板中，该等线路层22中的最厚者与最薄者的厚度的差为3至15微米，该等线路层22中的最厚者与最薄者的厚度的差较佳为5至10微米。
于本发明的封装基板中，该等线路层22的数量为单数或双数。
请参阅图3，其为本发明的封装结构的剖视图。如图所示，其主要通过于本发明的封装基板2的上表面2a上接置有芯片31，并形成有包覆该芯片31的封装胶体32，至于其余技术特征大致如前所述，故不再为文赘述。
综上所述，相较于现有技术，本发明通过调整封装基板中的部分线路层的厚度，使部分线路层的厚度较厚，以增加封装基板的整体刚性，减少基板翘曲的发生（约减少5至25%），进而提高产品的良率；此外，由于并非增厚所有线路层的厚度，或者，由于可使部分线路层的厚度减少，即部分线路层的厚度较薄，故可使所有线路层的厚度总和不增加，进而能避免封装基板及封装结构的整体厚度增加，而能符合现今电子产品的轻薄短小的趋势。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (19)

1.一种封装基板，包括：
多个介电层；以及
多个与各该介电层交互堆栈的线路层，其中，至少二该线路层具有厚度差，其中，位于或接近该封装基板的上表面的该线路层的厚度大于位于或接近该封装基板的下表面的该线路层的厚度，且最接近该上表面的线路层的厚度大于其它所有该线路层的厚度，最接近该下表面的线路层的厚度小于其它所有该线路层的厚度，除最接近该上表面的线路层与最接近下表面的线路层外，其余的线路层具有相同的厚度。
2.根据权利要求1所述的封装基板，其特征在于，该上表面与下表面分别为置晶侧与非置晶侧。
3.根据权利要求1所述的封装基板，其特征在于，所述线路层的厚度由该上表面逐渐往该下表面减少。
4.根据权利要求1所述的封装基板，其特征在于，接近该上表面的半数的线路层的厚度总和大于接近该下表面的半数的线路层的厚度总和。
5.根据权利要求1所述的封装基板，其特征在于，所述线路层中的最厚者与最薄者的厚度的比为1.2：1至2：1。
6.根据权利要求5所述的封装基板，其特征在于，所述线路层中的最厚者与最薄者的厚度的比为1.5：1。
7.根据权利要求1所述的封装基板，其特征在于，所述线路层中的最厚者与最薄者的厚度的差为3至15微米。
8.根据权利要求7所述的封装基板，其特征在于，所述线路层中的最厚者与最薄者的厚度的差为5至10微米。
9.根据权利要求1所述的封装基板，其特征在于，所述线路层的数量为单数或双数。
10.根据权利要求1所述的封装基板，其特征在于，一该介电层为核心板，且所述线路层以该核心板为中心的方式对称分布于该核心板的相对两表面上。
11.一种封装结构，包括：
封装基板，其包括多个介电层及多个与各该介电层交互堆栈的线路层，至少二该线路层具有厚度差，其中，位于或接近该封装基板的上表面的该线路层的厚度大于位于或接近该封装基板的下表面的该线路层的厚度，且最接近该上表面的线路层的厚度大于其它所有该线路层的厚度，最接近该下表面的线路层的厚度小于其它所有该线路层的厚度，除最接近该上表面的线路层与最接近下表面的线路层外，其余的线路层具有相同的厚度；以及
芯片，其接置于该封装基板的上表面上。
12.根据权利要求11所述的封装结构，其特征在于，所述线路层的厚度由该上表面逐渐往该下表面减少。
13.根据权利要求11所述的封装结构，其特征在于，接近该上表面的半数的线路层的厚度总和大于接近该下表面的半数的线路层的厚度总和。
14.根据权利要求11所述的封装结构，其特征在于，所述线路层中的最厚者与最薄者的厚度的比为1.2：1至2：1。
15.根据权利要求14所述的封装结构，其特征在于，所述线路层中的最厚者与最薄者的厚度的比为1.5：1。
16.根据权利要求11所述的封装结构，其特征在于，所述线路层中的最厚者与最薄者的厚度的差为3至15微米。
17.根据权利要求16所述的封装结构，其特征在于，所述线路层中的最厚者与最薄者的厚度的差为5至10微米。
18.根据权利要求11所述的封装结构，其特征在于，所述线路层的数量为单数或双数。
19.根据权利要求11所述的封装结构，其特征在于，一该介电层为核心板，且所述线路层以该核心板为中心的方式对称分布于该核心板的相对两表面上。
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