CN104103602B - 半导体封装件及其制法 - Google Patents

半导体封装件及其制法 Download PDF

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CN104103602B
CN104103602B CN201310146074.1A CN201310146074A CN104103602B CN 104103602 B CN104103602 B CN 104103602B CN 201310146074 A CN201310146074 A CN 201310146074A CN 104103602 B CN104103602 B CN 104103602B
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CN104103602A (zh
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刘鸿汶
许习彰
张江城
陈威宇
纪杰元
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Siliconware Precision Industries Co Ltd
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Abstract

一种半导体封装件及其制法，该半导体封装件包括：嵌埋有半导体组件的封装体、形成于该封装体中并位于该半导体组件外围的多个支撑部、以及连结于各该支撑部之间的强化部。通过该支撑部与该强化部的设计，以增加该封装体的强度，进而增加半导体封装件的结构强度。

Description

半导体封装件及其制法
技术领域
本发明涉及一种半导体封装件，尤指一种无封装基板的半导体封装件及其制法。
背景技术
随着半导体技术的演进，半导体产品已开发出不同封装产品型态，而为追求半导体封装件的轻薄短小，因而发展出一种芯片级封装件(chip scale package,CSP)，其特征在于此种芯片级封装件仅具有与芯片尺寸相等或略大的尺寸。
如图1A至图1E，其为现有无封装基板的芯片级的半导体封装件1的制法的剖面示意图。
如图1A所示，形成一热化离型胶层（thermal release tape）100于一承载件10上。
如图1B所示，置放多个半导体芯片11于该热化离型胶层100上，该些半导体芯片11具有相对的主动面11a与非主动面11b，各该主动面11a上均具有多个电极垫110，且各该主动面11a粘着于该热化离型胶层100上。
如图1C所示，以模压（molding）方式形成绝缘材12于该热化离型胶层100上，以包覆该半导体芯片11。
如图1D所示，进行烘烤工艺以硬化该绝缘材12而成为封装体13，而同时该热化离型胶层100因受热后会失去粘性，所以可一并移除该热化离型胶层100与该承载件10，以外露该半导体芯片11的主动面11a。
如图1E所示，进行线路重布层（Redistribution layer,RDL）工艺，形成一线路重布结构18于该封装体13与该半导体芯片11的主动面11a上，令该线路重布结构18电性连接该半导体芯片11的电极垫110。之后，将整片的封装体13进行切单作业，以完成一无封装基板的封装结构。通过免除该封装基板，使该封装件达到轻薄短小的目的，以符合现代电子产品潮流的产品。
然而，现有半导体封装件1的制法中，以封胶材料(Molding compound)作为绝缘材12，其杨氏系数(Young's modulus)大，因而较硬较脆，所以该半导体封装件1的翘曲（warpage）程度较大，致使后续形成的线路重布结构18与该半导体芯片11的电极垫110间的对位将产生偏移，而当偏移公差过大时，该线路重布结构18将无法与该半导体芯片11的电极垫110连接，导致该线路重布结构18与该半导体芯片11间的电性连接受到极大影响，因而造成良率过低及产品可靠度不佳等问题。
此外，仅于该封装体13的一侧形成线路重布结构18，已无法符合终端产品的多任务需要。
因此，遂研发出如图1’及图1”所示的结构，以使该封装体13的两侧可接置电路板、半导体芯片、被动组件1b或其它封装件1a。
如图1’及图1”所示，现有半导体封装件1’于一封装体13的第一表面13a内侧嵌埋一半导体芯片11，且于该封装体13中具有连通其第一与第二表面13a,13b的导电通孔14，并于该封装体13的第一与第二表面13a,13b上分别形成第一与第二线路重布结构15,16，以令该第一线路重布结构15电性连接该半导体芯片11，且该导电通孔14电性连接该第一与第二线路重布结构15,16，致使该半导体芯片11电性连接该导电通孔14与第二线路重布结构16。再于该第一线路重布结构15上形成如焊球的导电组件17，以接置如电路板的电子装置（图未示），又于该第二线路重布结构16上接置如半导体芯片、被动组件1b或另一封装件1a的电子结构。
其中，该半导体封装件1’的工艺中，将如ABF（Ajinomoto Build-up Film）或其它杨氏系数较小的介电材作为绝缘材12以压合该半导体芯片11，所以可避免因翘曲过大而无法进行后续的RDL等工艺。
但是，于该半导体封装件1’的工艺中，因使用杨氏系数较小的介电材，致使该半导体封装件1’的结构强度不佳，因而于后续接置半导体芯片、被动组件1b或其它封装件1a时，会使下方的封装体13的结构发生翘曲或该第二线路重布结构16发生塌陷(如图1”的虚线范围A)等缺点。
此外，因该半导体芯片11与介电材的杨氏系数相差过大，致使应力会集中于该第一线路重布结构15的部分区域，而使该第一线路重布结构15发生碎裂（crack）（如图1’及图1”的虚线范围B）的问题。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失，本发明的主要目的在于提供一种半导体封装件及其制法，以增加该封装体的强度，进而增加半导体封装件的结构强度。
本发明的半导体封装件，其包括：封装体，其具有相对的第一表面与第二表面，且该封装体自其第一表面嵌埋有至少一半导体组件，该半导体组件具有相对的主动面与非主动面，且于该主动面上具有多个电极垫；多个支撑部，形成于该封装体中并位于该半导体组件的外围；以及强化部，其连结于各该支撑部之间。
本发明还提供一种半导体封装件的制法，其包括：提供一具有相对的第一表面与第二表面的封装体，且该封装体自其第一表面嵌埋有至少一半导体组件，该半导体组件具有相对的主动面与非主动面，且于该主动面上具有多个电极垫；形成连通该第一表面与第二表面的多个穿孔于该封装体中，且形成连通于各该穿孔之间的沟槽，又该些穿孔位于该半导体组件的外围；以及形成支撑部于各该穿孔中，且形成强化部于该沟槽中，以令各该支撑部之间通过该强化部相连结。
前述的制法中，该封装体的工艺包括：设置该半导体组件于一承载件上；将绝缘材包覆该半导体组件，以形成该封装体，且该封装体的第一表面结合于该承载件上；以及移除该承载件。
前述的半导体封装件及其制法中，该封装体为矩形体，且该些穿孔位于该矩形体的四个角落处。
前述的半导体封装件及其制法中，该半导体组件的主动面齐平于该封装体的第一表面。
前述的半导体封装件及其制法中，该支撑部的材质为金属。
前述的半导体封装件及其制法中，该些支撑部均未电性连接该半导体组件，且该些强化部均未电性连接该半导体组件。又该强化部的材质为金属。
前述的半导体封装件及其制法中，还包括第一线路重布结构，其设于该封装体的第一表面上，且该第一线路重布结构电性连接该半导体组件。
另外，前述的半导体封装件及其制法中，还包括第二线路重布结构，其设于该封装体的第二表面上，且该第二线路重布结构电性连接该半导体组件。
由上可知，本发明的半导体封装件及其制法，通过不具电性功能的支撑部与强化部的设计，以增加该封装体的强度，进而增加半导体封装件的结构强度，所以不论采用杨氏系数较大或较小的绝缘材，均可避免现有技术的种种问题。
附图说明
图1A至图1E为现有半导体封装件的制法的剖视示意图；
图1’及图1”为现有半导体封装件的其它态样的剖视示意图；
图2A至图2G为本发明的半导体封装件的制法的剖视示意图；其中，图2C’为图2C的上视图；
图3A为图2D的立体外观示意图；以及
图3B为图3A的另一实施例的立体示意图。
符号说明
1,1’,2 半导体封装件
1a 封装件
1b 被动组件
10,20 承载件
100 热化离型胶层
11 半导体芯片
11a,21a 主动面
11b,21b 非主动面
110,210 电极垫
12,22 绝缘材
13,23 封装体
13a,23a 第一表面
13b,23b 第二表面
14 导电通孔
15,25 第一线路重布结构
16,26 第二线路重布结构
17,27 导电组件
18 线路重布结构
200 结合层
21 半导体组件
24,24’ 支撑部
240 穿孔
34 强化部
340 沟槽
A,B 虚线范围。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2G为本发明的半导体封装件2的制法的剖面示意图。
如图2A所示，提供一具有一结合层200的承载件20，且设置多个半导体组件21于该结合层200上，再通过绝缘材22包覆该些半导体组件21，以形成一封装体23。
于本实施例中，该承载件20的尺寸可依需求选择晶圆型基板（Wafer formsubstrate）或一般整版面型基板（Panel form substrat），且该结合层200为离型膜或胶材。
此外，该封装体23具有相对的第一表面23a与第二表面23b，且该些半导体组件21嵌埋于该封装体23的第一表面23a内侧。
又，该半导体组件21为芯片，其具有相对的主动面21a与非主动面21b，该主动面21a结合于该结合层200，并于该主动面21a上具有多个电极垫210。
另外，该些半导体组件21的主动面21a齐平于该封装体23的第一表面23a。
如图2B所示，移除该承载件20及结合层200，以外露该封装体23的第一表面23a与该半导体组件21的主动面21a。
如图2C所示，形成连通该第一表面23a与第二表面23b的多个穿孔240于该封装体23中，且该些穿孔240位于该些半导体组件21的外围。
于本实施例中，该封装体23为矩形体，且该些穿孔240至少位于该矩形体的四个角落处，如图2C’所示。
此外，还形成连通于各该穿孔240之间的沟槽340，如图3B所示。
如图2D所示，形成支撑部24于各该穿孔240中，且于形成该些穿孔240时，于该封装体23的第一表面23a及/或第二表面23b上还形成强化部34于该沟槽340中，如图3A所示，以令各该支撑部24之间通过该强化部34相连结。
于本实施例中，该支撑部24为金属柱，例如铜柱，且该强化部34的材质为金属，例如铜。
此外，如图3B所示，于另一实施例中，多个支撑部24’排列成环状形成立方体支架，即除了位于该封装体23的四个角落处，还位于该封装体23的四个边缘处。因此，利用分离(No-Contact)方式设计该立方体支架，当该支撑部24’越多时，该封装体23的强度越高。
又，该强化部34可依需求形成于该封装体23的单侧（即位于该第一表面23a或第二表面23b的其中一者）或双侧（即位于该第一表面23a及第二表面23b）。
如图2E所示，进行线路重布层（Redistribution layer,RDL）工艺，即形成第一线路重布结构25于该封装体23的第一表面23a与该半导体组件21的主动面21a上，令该第一线路重布结构25电性连接至该半导体组件21的电极垫210。
于本实施例中，该支撑部24,24’或该强化部34虽可依需求连接该第一线路重布结构25，如图中的粗斜线处，但不会电性导通至该半导体组件21，所以该些支撑部24,24’及该强化部34均未电性连接该半导体组件21。
如图2F所示，进行线路重布层（RDL）工艺，即形成第二线路重布结构26于该封装体23的第二表面23b上，且该第二线路重布结构26可依需求利用导电孔的技术，令该第二线路重布结构26电性连接该第一线路重布结构25或导通至该半导体组件21。
于本实施例中，该支撑部24,24’或该强化部34可依需求连接该第二线路重布结构26，如图中的粗斜线处，但不会电性导通至该半导体组件21，所以该些支撑部24,24’及该强化部34均未电性连接该半导体组件21。
如图2G所示，形成如焊球的导电组件27于该第一线路重布结构25上，以令该导电组件27电性连接至该半导体组件21。
本发明通过不具电性功能的支撑部24,24’的设计，以增加该封装体23边缘的强度，进而增加半导体封装件2的结构强度，所以即使采用材质较软（或杨氏系数较小）的绝缘材22，仍可避免现有因杨氏系数较小的介电材而使封装件的结构强度不佳的问题。因此，于后续接置半导体芯片、被动组件或其它封装件时，本发明的半导体封装件2不会发生翘曲，且该第二线路重布结构26不会发生塌陷。
此外，当该半导体组件21与绝缘材22的杨氏系数相差过大时，通过该支撑部24,24’增加该封装体23边缘的强度，使应力会分散于该支撑部24,24’，所以应力不会集中于该第一线路重布结构25的部分区域，因而能避免该第一线路重布结构25发生碎裂的问题。
又，本发明也可使用杨氏系数较大或与该半导体组件21的杨氏系数相接近的绝缘材22，虽其较硬较脆，但通过该支撑部24,24’增加该封装体23边缘的强度，所以可降低该半导体封装件2的翘曲程度。因此，于形成该第一线路重布结构25时，能避免该第一线路重布结构25与该半导体组件21的电极垫210间的对位产生偏移，因而能避免该第一线路重布结构25与该半导体组件21间的电性连接受到极大影响，所以能避免良率过低及产品可靠度不佳等问题。
另外，在该些支撑部24,24’之间以该强化部34作连接，藉以能增加刚性。因此，本发明通过该强化部34所构成（或其与部分第一及第二线路重布结构25,26所构成）的环状结构配合该支撑部24,24’而形成立方体支架的设计，能大幅增加该封装体23的强度，进而增加该半导体封装件2的结构强度。
本发明的半导体封装件2包括：具有相对的第一表面23a与第二表面23b的封装体23、形成于该封装体23中且连通该第一表面23a与第二表面23b的多个支撑部24,24’、以及连结于各该支撑部24,24’之间的强化部34。
所述的封装体23的第一表面23a嵌埋有多个半导体组件21，且该封装体23为矩形体，以令该些支撑部24,24’位于该矩形体的四个角落处。
所述的半导体组件21具有相对的主动面21a与非主动面21b，且于该主动面21a上具有多个电极垫210，又该半导体组件21的主动面21a齐平于该封装体23的第一表面23a。
所述的支撑部24,24’位于该半导体组件21的外围，且该些支撑部24,24’均未电性连接该半导体组件21，又该支撑部24,24’的材质为金属。
所述的强化部34未电性连接该半导体组件21，且该强化部34的材质为金属。
于一实施例中，所述的半导体封装件2还包括第一线路重布结构25，其设于该封装体23的第一表面23a上，且该第一线路重布结构25电性连接该半导体组件21。
于一实施例中，所述的半导体封装件2还包括第二线路重布结构26，其设于该封装体23的第二表面23b上，且该第二线路重布结构26电性连接该半导体组件21。
综上所述，本发明的半导体封装件及其制法，主要通过不具电性功能的支撑部与强化部的设计，以增加该封装体的强度，进而增加半导体封装件的结构强度。
此外，通过环状结构（由支撑部与强化部所构成）的设计，更能增加该封装体的强度，进而增加该半导体封装件的结构强度。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (13)

1.一种半导体封装件，其包括：
封装体，其为矩形体并具有相对的第一表面与第二表面，且该封装体自其第一表面嵌埋有至少一半导体组件，该半导体组件具有相对的主动面与非主动面，且于该主动面上具有多个电极垫；
第一线路重布结构，其设于该封装体的第一表面上，且该第一线路重布结构电性连接该半导体组件；
多个支撑部，形成于该封装体中并位于该半导体组件的外围且位于该矩形体的四个角落处；以及
强化部，其连结于各该支撑部之间以构成环状结构，且该环状结构连接该第一线路重布结构的线路重布层。
2.根据权利要求1所述的半导体封装件，其特征在于，该半导体组件的主动面齐平于该封装体的第一表面。
3.根据权利要求1所述的半导体封装件，其特征在于，该支撑部的材质为金属。
4.根据权利要求1所述的半导体封装件，其特征在于，该些支撑部均未电性连接该半导体组件，且该些强化部均未电性连接该半导体组件。
5.根据权利要求1所述的半导体封装件，其特征在于，该强化部的材质为金属。
6.根据权利要求1所述的半导体封装件，其特征在于，该半导体封装件还包括第二线路重布结构，其设于该封装体的第二表面上，且该第二线路重布结构电性连接该半导体组件。
7.一种半导体封装件的制法，其包括：
提供一具有相对的第一表面与第二表面的封装体，且该封装体为矩形体并自其第一表面嵌埋有至少一半导体组件，该半导体组件具有相对的主动面与非主动面，且于该主动面上具有多个电极垫；
形成连通该第一表面与第二表面的多个穿孔于该封装体中，且形成连通于各该穿孔之间的沟槽，又该些穿孔位于该半导体组件的外围且位于该矩形体的四个角落处；
形成支撑部于各该穿孔中，且形成强化部于该沟槽中，以令各该支撑部之间通过该强化部相连结以构成环状结构；以及
形成第一线路重布结构于该封装体的第一表面上，且该第一线路重布结构电性连接该半导体组件，该环状结构连接该第一线路重布结构的线路重布层。
8.根据权利要求7所述的半导体封装件的制法，其特征在于，该封装体的工艺包括：
设置该半导体组件于一承载件上；
将绝缘材包覆该半导体组件，以形成该封装体，且该封装体的第一表面结合于该承载件上；以及
移除该承载件。
9.根据权利要求7所述的半导体封装件的制法，其特征在于，该半导体组件的主动面齐平于该封装体的第一表面。
10.根据权利要求7所述的半导体封装件的制法，其特征在于，该支撑部的材质为金属。
11.根据权利要求7所述的半导体封装件的制法，其特征在于，该些支撑部均未电性连接该半导体组件，且该些强化部均未电性连接该半导体组件。
12.根据权利要求7所述的半导体封装件的制法，其特征在于，该强化部的材质为金属。
13.根据权利要求7所述的半导体封装件的制法，其特征在于，该制法还包括形成第二线路重布结构于该封装体的第二表面上，且该第二线路重布结构未电性连接该支撑部。
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