TW201440184A - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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TW201440184A
TW201440184A TW102112469A TW102112469A TW201440184A TW 201440184 A TW201440184 A TW 201440184A TW 102112469 A TW102112469 A TW 102112469A TW 102112469 A TW102112469 A TW 102112469A TW 201440184 A TW201440184 A TW 201440184A
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redistribution structure
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electrically connected
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TWI492344B (zh
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劉鴻汶
許習彰
張江城
陳威宇
紀傑元
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矽品精密工業股份有限公司
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Abstract

一種半導體封裝件係包括：嵌埋有半導體元件之封裝體、形成於該封裝體中並位於該半導體元件外圍之複數支撐部、以及連結於各該支撐部之間的強化部。藉由該支撐部與該強化部之設計，以增加該封裝體之強度，進而增加半導體封裝件之結構強度。本發明復提供該半導體封裝件之製法。

Description

半導體封裝件及其製法
本發明係有關一種半導體封裝件，尤指一種無封裝基板之半導體封裝件及其製法。
隨著半導體技術的演進，半導體產品已開發出不同封裝產品型態，而為追求半導體封裝件之輕薄短小，因而發展出一種晶片級封裝件(chip scale package,CSP)，其特徵在於此種晶片級封裝件僅具有與晶片尺寸相等或略大的尺寸。
如第1A至1E圖，係為習知無封裝基板之晶片級之半導體封裝件1之製法之剖面示意圖。
如第1A圖所示，形成一熱化離型膠層(thermal release tape)100於一承載件10上。
如第1B圖所示，置放複數半導體晶片11於該熱化離型膠層100上，該些半導體晶片11具有相對之主動面11a與非主動面11b，各該主動面11a上均具有複數電極墊110，且各該主動面11a黏著於該熱化離型膠層100上。
如第1C圖所示，以模壓(molding)方式形成絕緣材 12於該熱化離型膠層100上，以包覆該半導體晶片11。
如第1D圖所示，進行烘烤製程以硬化該絕緣材12而成為封裝體13，而同時該熱化離型膠層100因受熱後會失去黏性，故可一併移除該熱化離型膠層100與該承載件10，以外露該半導體晶片11之主動面11a。
如第1E圖所示，進行線路重佈層(Redistribution layer,RDL)製程，係形成一線路重佈結構18於該封裝體13與該半導體晶片11之主動面11a上，令該線路重佈結構18電性連接該半導體晶片11之電極墊110。之後，將整片之封裝體13進行切單作業，以完成一無封裝基板之封裝結構。藉由免除該封裝基板，使該封裝件達到輕薄短小之目的，以符合現代電子產品潮流之產品。
然而，習知半導體封裝件1之製法中，係以封膠材料(Molding compound)作為絕緣材12，其楊氏係數(Young's modulus)大，因而較硬較脆，故該半導體封裝件1之翹曲(warpage)程度較大，致使後續形成之線路重佈結構18與該半導體晶片11之電極墊110間的對位將產生偏移，而當偏移公差過大時，該線路重佈結構18將無法與該半導體晶片11之電極墊110連接，導致該線路重佈結構18與該半導體晶片11間之電性連接受到極大影響，因而造成良率過低及產品可靠度不佳等問題。
再者，僅於該封裝體13之一側形成線路重佈結構18，已無法符合終端產品之多工需要。
因此，遂研發出如第1’及1”圖所示之結構，以使該封 裝體13之兩側可接置電路板、半導體晶片、被動元件1b或其它封裝件1a。
如第1’及1”圖所示，習知半導體封裝件1’係於一封裝體13之第一表面13a內側嵌埋一半導體晶片11，且於該封裝體13中具有連通其第一與第二表面13a,13b之導電通孔14，並於該封裝體13之第一與第二表面13a,13b上分別形成第一與第二線路重佈結構15,16，以令該第一線路重佈結構15電性連接該半導體晶片11，且該導電通孔14電性連接該第一與第二線路重佈結構15,16，致使該半導體晶片11電性連接該導電通孔14與第二線路重佈結構16。再於該第一線路重佈結構15上形成如銲球之導電元件17，以接置如電路板之電子裝置(圖未示)，又於該第二線路重佈結構16上接置如半導體晶片、被動元件1b或另一封裝件1a之電子結構。
其中，該半導體封裝件1’之製程中，係將如ABF(Ajinomoto Build-up Film)或其它楊氏係數較小之介電材作為絕緣材12以壓合該半導體晶片11，故可避免因翹曲過大而無法進行後續之RDL等製程。
惟，於該半導體封裝件1’之製程中，因使用楊氏係數較小之介電材，致使該半導體封裝件1’之結構強度不佳，因而於後續接置半導體晶片、被動元件1b或其它封裝件1a時，會使下方之封裝體13之結構發生翹曲或該第二線路重佈結構16發生塌陷(如第1”圖之虛線範圍A)等缺點。
再者，因該半導體晶片11與介電材之楊氏係數相差過 大，致使應力會集中於該第一線路重佈結構15之部分區域，而使該第一線路重佈結構15發生碎裂(crack)(如第1’及1”圖之虛線範圍B)之問題。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種半導體封裝件，係包括：封裝體，係具有相對之第一表面與第二表面，且該封裝體自其第一表面嵌埋有至少一半導體元件，該半導體元件係具有相對之主動面與非主動面，且於該主動面上具有複數電極墊；複數支撐部，形成於該封裝體中並位於該半導體元件之外圍；以及強化部，係連結於各該支撐部之間。
本發明復提供一種半導體封裝件之製法，係包括：提供一具有相對之第一表面與第二表面之封裝體，且該封裝體自其第一表面嵌埋有至少一半導體元件，該半導體元件係具有相對之主動面與非主動面，且於該主動面上具有複數電極墊；形成連通該第一表面與第二表面之複數穿孔於該封裝體中，且形成連通於各該穿孔之間的溝槽，又該些穿孔位於該半導體元件之外圍；以及形成支撐部於各該穿孔中，且形成強化部於該溝槽中，以令各該支撐部之間藉由該強化部相連結。
前述之製法中，該封裝體之製程係包括：設置該半導體元件於一承載件上；將絕緣材包覆該半導體元件，以形 成該封裝體，且該封裝體之第一表面結合於該承載件上；以及移除該承載件。
前述之半導體封裝件及其製法中，該封裝體係為矩形體，且該些穿孔位於該矩形體之四個角落處。
前述之半導體封裝件及其製法中，該半導體元件之主動面係齊平於該封裝體之第一表面。
前述之半導體封裝件及其製法中，該支撐部之材質係為金屬。
前述之半導體封裝件及其製法中，該些支撐部均未電性連接該半導體元件，且該些強化部均未電性連接該半導體元件。又該強化部之材質係為金屬。
前述之半導體封裝件及其製法中，復包括第一線路重佈結構，係設於該封裝體之第一表面上，且該第一線路重佈結構電性連接該半導體元件。
另外，前述之半導體封裝件及其製法中，復包括第二線路重佈結構，係設於該封裝體之第二表面上，且該第二線路重佈結構電性連接該半導體元件。
由上可知，本發明之半導體封裝件及其製法，係藉由不具電性功能之支撐部與強化部之設計，以增加該封裝體之強度，進而增加半導體封裝件之結構強度，故不論採用楊氏係數較大或較小之絕緣材，均可避免習知技術之種種問題。
1,1’,2‧‧‧半導體封裝件
1a‧‧‧封裝件
1b‧‧‧被動元件
10,20‧‧‧承載件
100‧‧‧熱化離型膠層
11‧‧‧半導體晶片
11a,21a‧‧‧主動面
11b,21b‧‧‧非主動面
110,210‧‧‧電極墊
12,22‧‧‧絕緣材
13,23‧‧‧封裝體
13a,23a‧‧‧第一表面
13b,23b‧‧‧第二表面
14‧‧‧導電通孔
15,25‧‧‧第一線路重佈結構
16,26‧‧‧第二線路重佈結構
17,27‧‧‧導電元件
18‧‧‧線路重佈結構
200‧‧‧結合層
21‧‧‧半導體元件
24,24’‧‧‧支撐部
240‧‧‧穿孔
34‧‧‧強化部
340‧‧‧溝槽
A,B‧‧‧虛線範圍
第1A至1E圖係為習知半導體封裝件之製法的剖視示 意圖；第1’及1”圖係為習知半導體封裝件之其它態樣的剖視示意圖；第2A至2G圖係為本發明之半導體封裝件之製法之剖視示意圖；其中，第2C’圖係為第2C圖之上視圖；第3A圖係為第2D圖之的立體外觀示意圖；以及第3B圖係為第3A圖之另一實施例的立體示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2G圖係為本發明之半導體封裝件2之製法的剖面示意圖。
如第2A圖所示，提供一具有一結合層200之承載件20，且設置複數半導體元件21於該結合層200上，再藉由絕緣材22包覆該些半導體元件21，以形成一封裝體23。
於本實施例中，該承載件20之尺寸可依需求選擇晶圓型基板(Wafer form substrate)或一般整版面型基板(Panel form substrat)，且該結合層200係為離型膜或膠材。
再者，該封裝體23具有相對之第一表面23a與第二表面23b，且該些半導體元件21係嵌埋於該封裝體23之第一表面23a內側。
又，該半導體元件21係為晶片，其具有相對之主動面21a與非主動面21b，該主動面21a結合於該結合層200，並於該主動面21a上具有複數電極墊210。
另外，該些半導體元件21之主動面21a係齊平於該封裝體23之第一表面23a。
如第2B圖所示，移除該承載件20及結合層200，以外露該封裝體23之第一表面23a與該半導體元件21之主動面21a。
如第2C圖所示，形成連通該第一表面23a與第二表面23b之複數穿孔240於該封裝體23中，且該些穿孔240位於該些半導體元件21之外圍。
於本實施例中，該封裝體23係為矩形體，且該些穿孔240係至少位於該矩形體之四個角落處，如第2C’圖所示。
再者，復形成連通於各該穿孔240之間的溝槽340，如第3B圖所示。
如第2D圖所示，形成支撐部24於各該穿孔240中，且於形成該些穿孔240時，於該封裝體23之第一表面23a及/或第二表面23b上復形成強化部34於該溝槽340中，如第3A圖所示，以令各該支撐部24之間藉由該強化部34相連結。
於本實施例中，該支撐部24係為金屬柱，例如銅柱，且該強化部34之材質係為金屬，例如銅。
再者，如第3B圖所示，於另一實施例中，複數支撐部24’係排列成環狀形成立方體支架，即除了位於該封裝體23之四個角落處，還位於該封裝體23之四個邊緣處。因此，利用分離(No-Contact)方式設計該立方體支架，當該支撐部24’越多時，該封裝體23之強度越高。
又，該強化部34可依需求形成於該封裝體23之單側(即位於該第一表面23a或第二表面23b之其中一者)或雙側(即位於該第一表面23a及第二表面23b)。
如第2E圖所示，進行線路重佈層(Redistribution layer,RDL)製程，即形成第一線路重佈結構25於該封裝體23之第一表面23a與該半導體元件21之主動面21a上，令該第一線路重佈結構25電性連接至該半導體元件21之電極墊210。
於本實施例中，該支撐部24,24’或該強化部34雖可依需求連接該第一線路重佈結構25，如圖中之粗斜線處，但不會電性導通至該半導體元件21，故該些支撐部24,24’及該強化部34均未電性連接該半導體元件21。
如第2F圖所示，進行線路重佈層(RDL)製程，即形成第二線路重佈結構26於該封裝體23之第二表面23b上，且該第二線路重佈結構26可依需求利用導電孔之技術，令該第二線路重佈結構26電性連接該第一線路重佈結構25或導通至該半導體元件21。
於本實施例中，該支撐部24,24’或該強化部34係可依需求連接該第二線路重佈結構26，如圖中之粗斜線處，但不會電性導通至該半導體元件21，故該些支撐部24,24’及該強化部34均未電性連接該半導體元件21。
如第2G圖所示，形成如銲球之導電元件27於該第一線路重佈結構25上，以令該導電元件27電性連接至該半導體元件21。
本發明藉由不具電性功能之支撐部24,24’之設計，以增加該封裝體23邊緣之強度，進而增加半導體封裝件2之結構強度，故即使採用材質較軟(或楊氏係數較小)之絕緣材22，仍可避免習知因楊氏係數較小之介電材而使封裝件之結構強度不佳之問題。因此，於後續接置半導體晶片、被動元件或其它封裝件時，本發明之半導體封裝件2不會發生翹曲，且該第二線路重佈結構26不會發生塌陷。
再者，當該半導體元件21與絕緣材22之楊氏係數相差過大時，藉由該支撐部24,24’增加該封裝體23邊緣之強度，使應力會分散於該支撐部24,24’，故應力不會集中於該第一線路重佈結構25之部分區域，因而能避免該第一線路重佈結構25發生碎裂之問題。
又，本發明亦可使用楊氏係數較大或與該半導體元件21之楊氏係數相接近之絕緣材22，雖其較硬較脆，但藉由該支撐部24,24’增加該封裝體23邊緣之強度，故可降低該半導體封裝件2之翹曲程度。因此，於形成該第一線路重佈結構25時，能避免該第一線路重佈結構25與該半導體元件21之電極墊210間的對位產生偏移，因而能避免該第一線路重佈結構25與該半導體元件21間之電性連接受到極大影響，故能避免良率過低及產品可靠度不佳等問題。
另外，在該些支撐部24,24’之間以該強化部34作連接，藉以能增加剛性。因此，本發明藉由該強化部34所構成(或其與部分第一及第二線路重佈結構25,26所構成)之環狀結構配合該支撐部24,24’而形成立方體支架的設計，能大幅增加該封裝體23之強度，進而增加該半導體封裝件2之結構強度。
本發明之半導體封裝件2係包括：具有相對之第一表面23a與第二表面23b之封裝體23、形成於該封裝體23中且連通該第一表面23a與第二表面23b之複數支撐部24,24’、以及連結於各該支撐部24,24’之間的強化部34。
所述之封裝體23之第一表面23a嵌埋有複數半導體元件21，且該封裝體23係為矩形體，以令該些支撐部24,24’位於該矩形體之四個角落處。
所述之半導體元件21係具有相對之主動面21a與非主動面21b，且於該主動面21a上具有複數電極墊210，又該半導體元件21之主動面21a係齊平於該封裝體23之第一 表面23a。
所述之支撐部24,24’係位於該半導體元件21之外圍，且該些支撐部24,24’均未電性連接該半導體元件21，又該支撐部24,24’之材質係為金屬。
所述之強化部34係未電性連接該半導體元件21，且該強化部34之材質係為金屬。
於一實施例中，所述之半導體封裝件2復包括第一線路重佈結構25，係設於該封裝體23之第一表面23a上，且該第一線路重佈結構25電性連接該半導體元件21。
於一實施例中，所述之半導體封裝件2復包括第二線路重佈結構26，係設於該封裝體23之第二表面23b上，且該第二線路重佈結構26電性連接該半導體元件21。
綜上所述，本發明之半導體封裝件及其製法，主要藉由不具電性功能之支撐部與強化部之設計，以增加該封裝體之強度，進而增加半導體封裝件之結構強度。
再者，藉由環狀結構(由支撐部與強化部所構成)的設計，更能增加該封裝體之強度，進而增加該半導體封裝件之結構強度。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧半導體封裝件
21‧‧‧半導體元件
23‧‧‧封裝體
23a‧‧‧第一表面
23b‧‧‧第二表面
24‧‧‧支撐部
240‧‧‧穿孔
25‧‧‧第一線路重佈結構
26‧‧‧第二線路重佈結構
27‧‧‧導電元件

Claims (17)

  1. 一種半導體封裝件，係包括：封裝體，係具有相對之第一表面與第二表面，且該封裝體自其第一表面嵌埋有至少一半導體元件，該半導體元件係具有相對之主動面與非主動面，且於該主動面上具有複數電極墊；複數支撐部，形成於該封裝體中並位於該半導體元件之外圍；以及強化部，係連結於各該支撐部之間。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中，該封裝體係為矩形體，且該些支撐部位於該矩形體之四個角落處。
  3. 如申請專利範圍第1項所述之半導體封裝件，其中，該半導體元件之主動面係齊平於該封裝體之第一表面。
  4. 如申請專利範圍第1項所述之半導體封裝件，其中，該支撐部之材質係為金屬。
  5. 如申請專利範圍第1項所述之半導體封裝件，其中，該些支撐部均未電性連接該半導體元件，且該些強化部均未電性連接該半導體元件。
  6. 如申請專利範圍第1項所述之半導體封裝件，其中，該強化部之材質係為金屬。
  7. 如申請專利範圍第1項所述之半導體封裝件，復包括第一線路重佈結構，係設於該封裝體之第一表面上， 且該第一線路重佈結構電性連接該半導體元件。
  8. 如申請專利範圍第1或7項所述之半導體封裝件，復包括第二線路重佈結構，係設於該封裝體之第二表面上，且該第二線路重佈結構電性連接該半導體元件。
  9. 一種半導體封裝件之製法，係包括：提供一具有相對之第一表面與第二表面之封裝體，且該封裝體自其第一表面嵌埋有至少一半導體元件，該半導體元件係具有相對之主動面與非主動面，且於該主動面上具有複數電極墊；形成連通該第一表面與第二表面之複數穿孔於該封裝體中，且形成連通於各該穿孔之間的溝槽，又該些穿孔位於該半導體元件之外圍；以及形成支撐部於各該穿孔中，且形成強化部於該溝槽中，以令各該支撐部之間藉由該強化部相連結。
  10. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，該封裝體之製程係包括：設置該半導體元件於一承載件上；將絕緣材包覆該半導體元件，以形成該封裝體，且該封裝體之第一表面結合於該承載件上；以及移除該承載件。
  11. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，該封裝體係為矩形體，且該些穿孔位於該矩形體之四個角落處。
  12. 如申請專利範圍第9項所述之半導體封裝件之製法， 其中，該半導體元件之主動面係齊平於該封裝體之第一表面。
  13. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，該支撐部之材質係為金屬。
  14. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，該些支撐部均未電性連接該半導體元件，且該些強化部均未電性連接該半導體元件。
  15. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，該強化部之材質係為金屬。
  16. 如申請專利範圍第9項所述之半導體封裝件之製法，復包括形成第一線路重佈結構於該封裝體之第一表面上，且該第一線路重佈結構電性連接該半導體元件。
  17. 如申請專利範圍第9或16項所述之半導體封裝件之製法，復包括形成第二線路重佈結構於該封裝體之第二表面上，且該第二線路重佈結構未電性連接該支撐部。
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