TWI548043B - 封裝結構及其製法 - Google Patents

封裝結構及其製法 Download PDF

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Publication number
TWI548043B
TWI548043B TW103139710A TW103139710A TWI548043B TW I548043 B TWI548043 B TW I548043B TW 103139710 A TW103139710 A TW 103139710A TW 103139710 A TW103139710 A TW 103139710A TW I548043 B TWI548043 B TW I548043B
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Taiwan
Prior art keywords
layer
cladding layer
circuit
package structure
carrier
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TW103139710A
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English (en)
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TW201620087A (zh
Inventor
周信宏
林畯棠
邱世冠
陳仕卿
賴顗喆
張宏達
劉鴻汶
劉亦瑋
許習彰
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矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW103139710A priority Critical patent/TWI548043B/zh
Priority to CN201410763635.7A priority patent/CN105742256A/zh
Priority to US14/940,554 priority patent/US9607974B2/en
Publication of TW201620087A publication Critical patent/TW201620087A/zh
Application granted granted Critical
Publication of TWI548043B publication Critical patent/TWI548043B/zh

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Description

封裝結構及其製法
本發明係有關一種封裝製程，特別是關於一種嵌埋電子元件之封裝結構及其製法。
隨著半導體技術的演進，半導體產品已開發出不同封裝產品型態，而為追求半導體封裝件之輕薄短小，因而發展出一種晶片級封裝件(chip scale package,CSP)，其特徵在於此種晶片級封裝件僅具有與晶片尺寸相等或略大的尺寸。
第1A至1H圖係為習知半導體封裝件1之製法的剖面示意圖。
如第1A圖所示，提供一具有一結合層100之第一承載件10a，且設置複數半導體元件11於該結合層100上。該半導體元件11具有相對之主動面11a與非主動面11b，該主動面11a結合於該結合層100，並於該主動面11a上具有複數電極墊110。
如第1B圖所示，形成一包覆層13以包覆該些半導體元件11，且該包覆層13之第二表面13b上設有第二承載 件10b。
如第1C圖所示，移除該第一承載件10a及結合層100，以外露該包覆層13之第一表面13a與該半導體元件11之主動面11a。
如第1D圖所示，形成一線路結構12於該包覆層13之第一表面13a與該半導體元件11之主動面11a上，且該線路結構12電性連接該半導體元件11之電極墊110。
如第1E圖所示，設置第三承載件10c於該線路結構12上，再移除該第二承載件10b。之後以雷射方式形成複數貫穿該包覆層13之通孔140，以外露出該線路結構12。
如第1F圖所示，於該通孔140中電鍍形成導電柱14，以電性連接該線路結構12。
如第1G圖所示，形成線路重佈層(redistribution layer，簡稱RDL)15於該包覆層13之第二表面13b上，且該線路重佈層15電性連接各該導電柱14。
如第1H圖所示，移除該第三承載件10c，再進行切單製程，並形成複數如銲球之導電元件17於該線路結構12上，以令該導電元件17電性連接該線路結構12。
惟，於該半導體封裝件1之製法中，以雷射方式形成通孔140，不僅速度慢(特別是孔數較多時)而耗時，且於形成該通孔140之過程中所產生之殘留物(如該包覆層13之殘膠等)極易堆積於該通孔140之底部，以致於後續製程中需先清洗該通孔140內部，才能將導電材料填入該通孔140中，導致製程步驟繁多。
再者，雷射開孔方式會造成該通孔140之壁面呈現凹凸不平，造成後續電鍍之導電材無法有效附著於該通孔140之壁面上而發生脫落(peeling)現象，導致該半導體封裝件1之可靠度不佳。
又，雷射鑽孔製程需由該包覆層13之第二表面13b上進行鑽孔，但受限於該包覆層13不透光，故雷射鑽孔設備無法偵測該包覆層13下之線路結構12，因而需以特殊製程及設備進行對位鑽孔，致使製程步驟增多及提高製作成本。
另外，雷射鑽孔製程之雷射光束會產生熱影響區(Heat Affact Zone)之問題，亦即當該通孔140之位置需靠近該半導體元件11時，雷射光束之高熱會破壞半導體元件11，故該導電柱14之位置需與該半導體元件11保持一定距離，因而無法縮小該半導體封裝件1之尺寸，致使產品難以符合微小化之需求。
另一方面，於該半導體封裝件1之製法中，需多次(至少三次)進行結合/移除承載件(即該第一至第三承載件10a-10c)之步驟，致使製程步驟繁多，不僅耗時，且需消耗承載件之料數，而增加產品之製作成本。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明提供一種封裝結構，係包括：包覆層，係具有相對之第一表面與第二表 面；線路層，係嵌埋於該包覆層之第一表面；至少一電子元件，係嵌埋於該包覆層中；以及複數導電柱，係嵌埋於該包覆層中並立設於該線路層上，且該導電柱具有相對之第一端及第二端，並以其第一端結合至該線路層。
本發明復提供一種封裝結構之製法，係包括：準備一具有線路層之第一承載件；形成複數具有相對之第一端及第二端之導電柱於該線路層上，且各該導電柱以其第一端結合至該線路層，並設置至少一電子元件於該第一承載件上；形成具有相對之第一表面及第二表面之包覆層於該第一承載件上，以令該包覆層包覆該些導電柱、該線路層與該電子元件，且該包覆層之第一表面係結合至該第一承載件上；以及移除該第一承載件。
前述之封裝結構及其製法中，該線路層之表面係齊平該包覆層之第一表面。
前述之封裝結構及其製法中，該電子元件之表面係齊平該包覆層之第一表面，或該電子元件係外露於該包覆層之第二表面。
前述之封裝結構及其製法中，復包括於移除該第一承載件後，形成線路結構於該包覆層之第一表面上，且令該線路結構電性連接該電子元件與該線路層。又包括於移除該第一承載件前，先設置一第二承載件於該包覆層之第二表面上，待形成該線路結構後，移除該第二承載件。
前述之封裝結構及其製法中，復包括形成至少一線路重佈層於該包覆層之第二表面上，且令該線路重佈層電性 連接各該導電柱之第二端。
另外，前述之封裝結構及其製法中，復包括堆疊至少一電子裝置於該包覆層之第二表面上，使該電子裝置電性連接各該導電柱之第二端。
由上可知，本發明封裝結構及其製法中，藉由先形成該線路層與導電柱，再形成該包覆層，故無需進行開孔製程，因而無需以雷射方式形成通孔，更無需進行習知清洗孔洞、於通孔中電鍍導電材等製程。因此，本發明之製法不僅省時，且能避免因通孔之壁面凹凸不平而發生導電柱脫落之問題，故能提升該封裝結構之可靠度。
再者，本發明之製法無需進行鑽孔對位之步驟，因而能省略特殊製程及設備，以減少製程步驟及降低製作成本。
又，因無需進行雷射鑽孔製程，故不會產生熱影響區之問題，因此，可依需求設計該導電柱之位置，使該導電柱與該電子元件之距離可依需求縮短，以符合微小化之需求。
另外，因無需進行開孔製程，故能一次完成該包覆層之同一側上之所有製程，因而只需兩次進行結合/移除承載件(即該第一及第二承載件)之步驟。因此，本發明之製法能能簡化製程，且同時降低製作成本。
1‧‧‧半導體封裝件
10a,20a‧‧‧第一承載件
10b,20b‧‧‧第二承載件
10c‧‧‧第三承載件
100,201,203‧‧‧結合層
11‧‧‧半導體元件
11a,21a‧‧‧主動面
11b,21b,21b’,21b”‧‧‧非主動面
110,210‧‧‧電極墊
12,26‧‧‧線路結構
13,23‧‧‧包覆層
13a,23a‧‧‧第一表面
13,23b‧‧‧第二表面
14,24‧‧‧導電柱
140‧‧‧通孔
15,25,25’‧‧‧線路重佈層
17,27,280‧‧‧導電元件
2,2’‧‧‧封裝結構
200,202‧‧‧板體
21‧‧‧電子元件
22‧‧‧線路層
230‧‧‧開口
24a‧‧‧第一端
24b‧‧‧第二端
260‧‧‧介電層
261,263‧‧‧線路
28‧‧‧電子裝置
281‧‧‧晶片
29‧‧‧絕緣保護層
S‧‧‧切割路徑
第1A至1H圖係為習知半導體封裝件之製法的剖面示意圖；以及第2A至2H圖係為本發明封裝結構之製法之剖視示意 圖；其中，第2G’、2H’及2H”圖係為第2G圖之其它態樣。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2H圖係為本發明封裝結構2之製法之剖視示意圖。
如第2A圖所示，準備一具有一線路層22之第一承載件20a。
於本實施例中，該第一承載件20a係包含如半導體材、介電材、陶瓷材、玻璃或金屬材之板體200，但不限於此，且該第一承載件20a之尺寸可依需求選擇晶圓型基 板(Wafer form substrate)或一般整版面型基板(Panel form substrat)。
再者，該第一承載件20a復包含如離型膜或膠材之結合層201，且該結合層201以塗佈或貼合方式形成於該板體200上。
又，該線路層22係具有複數電性接觸墊與複數導電跡線。
如第2B圖所示，形成複數具有相對之第一端24a及第二端24b的導電柱24於該線路層22之電性接觸墊上，且該導電柱24以其第一端24a結合至該線路層22。之後，設置複數電子元件21於該第一承載件20a之結合層201上。
於本實施例中，各該電子元件21係平面相鄰排設，且該電子元件21係為主動元件(如半導體晶片)或被動元件(如電容)，其具有相對之主動面21a與非主動面21b，該主動面21a上具有複數電極墊210，並以該主動面21a結合至該結合層201。
如第2C圖所示，形成具有相對之第一表面23a及第二表面23b之一包覆層23於該第一承載件20a之結合層201上，以令該包覆層23包覆各該導電柱24、該線路層22與該些電子元件21，且該包覆層23之第一表面23a係結合至該第一承載件20a之結合層201上，而該些導電柱24之第二端24b係外露於該包覆層23之第二表面23b。
於本實施例中，該包覆層23之製程可選擇液態封膠 (liquid compound)、噴塗(injection)、壓合(lamination)或模壓(compression molding)。
再者，該包覆層23係覆蓋該些電子元件21之非主動面21b。
如第2D圖所示，形成一線路重佈層(redistribution layer，簡稱RDL)25於該包覆層23之第二表面23b上，且該線路重佈層25係電性連接各該導電柱24之第二端24b，使該線路重佈層25經由該導電柱24電性連接該線路層22。
於本實施例中，該線路重佈層25係為一層；於其它實施例中，可依需求製作多層線路重佈層(RDL)25’於該包覆層23之第二表面23b上，如2G’圖所示。
如第2E圖所示，設置一第二承載件20b於該包覆層23之第二表面23b與該線路重佈層25上。接著，移除該第一承載件20a，以外露該線路層22、該包覆層23之第一表面23a與該電子元件21之主動面21a。
於本實施例中，該第二承載件20b係包含如半導體材、介電材、陶瓷材、玻璃或金屬材之板體202，但不限於此，且該第二承載件20b之尺寸可依需求選擇晶圓型基板(Wafer form substrate)或一般整版面型基板(Panel form substrat)。
再者，該第二承載件20b復包含如離型膜或膠材之結合層203，且該結合層203以塗佈或貼合方式形成於該板體202上，並將該結合層203壓合於該包覆層23之第二表 面23b上，使該線路重佈層25嵌埋於該結合層203內側。
又，該電子元件21之主動面21a係齊平該包覆層23之第一表面23a，且該線路層22之外露表面亦齊平該包覆層23之第一表面23a。
如第2F圖所示，進行線路重佈層(RDL)製程，以形成一線路結構26於該包覆層23之第一表面23a上，且該線路結構26電性連接該電子元件21之電極墊210與該線路層22。
於本實施例中，該線路結構26係具有複數介電層260與複數線路261,263。
如第2G圖所示，先移除該第二承載件20b以外露出該線路重佈層25，再形成一如防銲層之絕緣保護層29於該包覆層23之第二表面23b上並外露部分該線路重佈層25，俾供作為外接墊。之後沿如第2F圖所示之切割路徑S進行切單製程，且形成複數如銲球之導電元件27於該線路結構26之最外層線路263上，使該導電元件27電性連接該線路結構26之線路263，並藉由該些導電元件27接置如電路板之電子裝置(圖略)。
如第2H圖所示，堆疊一電子裝置28於該包覆層23之第二表面23b上，使該電子裝置28電性連接該線路重佈層25，以成為堆疊式封裝結構2’。
於本實施例中，該電子裝置28係為封裝件、晶片或基板等，並無特別限制。例如，該電子裝置28係具有打線式晶片281；於其它實施例中，該電子裝置亦可具有覆晶式 晶片，但晶片之設置方式不限於上述。
再者，該電子裝置28係以如銲錫凸塊、銅凸塊之導電元件280電性連接該線路重佈層25。
又，於其它實施例中，該電子元件21之非主動面21b上方之該包覆層23之第二表面23b處可設計為非佈線區，即該非佈線區上不會形成線路。因此，可依需求於第2C圖之製程中形成開口230於該非佈線區上，故於移除該第二承載件20b後，各該電子元件21之非主動面21b’會外露於該包覆層23之第二表面23b，如第2H’圖所示，俾供散熱或外接元件之用(例如，該導電元件280接觸及設置於該電子元件21之非主動面21b’上)。
或者，如第2H”圖所示，該電子元件21之非主動面21b”亦可齊平該包覆層23之第二表面23b以外露於該包覆層23之第二表面23b。
本發明之製法中，藉由先形成該線路層22與導電柱24，再形成該包覆層23，故無需進行開孔製程，因而無需以雷射方式形成通孔，更無需進行習知清洗孔洞、於通孔中電鍍導電材等製程。因此，本發明之製法不僅省時，且能避免因通孔之壁面凹凸不平而發生導電柱脫落(peeling)之問題，故能提升該封裝結構2之可靠度。
再者，本發明之製法因先形成該線路層22與導電柱24，再形成該包覆層23，故無鑽孔對位之步驟，因而能省略特殊製程及設備，以減少製程步驟及降低製作成本。
又，因無需進行雷射鑽孔製程，故不會產生熱影響區 之問題，因此，可依需求設計該導電柱24之位置，使該導電柱24與該電子元件21之距離可依需求縮短，因而能縮小該封裝結構2之尺寸，以令產品能符合微小化之需求。
另外，因無需進行開孔製程，故能一次完成該包覆層23之同一側上之所有製程，因而只需兩次進行結合/移除承載件(即該第一及第二承載件20a,20b)之步驟。因此，相較於習知技術，本發明之製法能減少進行結合/移除承載件之步驟次數，因而能簡化製程，且同時降低製作成本。
本發明提供一種封裝結構2,2’，係包括：一包覆層23、一線路層22、至少一電子元件21、複數導電柱24以及至少一線路重佈層25,25’。
所述之包覆層23係具有相對之第一表面23a與第二表面23b。
所述之線路層22係嵌埋於該包覆層23之第一表面23a。
所述之電子元件21係嵌埋於該包覆層23中，且該電子元件21之表面(如主動面21a)係齊平該包覆層23之第一表面23a。
所述之導電柱24係嵌埋於該包覆層23中並立設於該線路層22上，且該導電柱24具有相對之第一端24a及第二端24b，並以其第一端24a結合至該線路層22。
所述之線路重佈層25,25’係設於該包覆層23之第二表面23b上並電性連接各該導電柱24之第二端24b。
於一實施例中，該線路層22之表面係齊平該包覆層 23之第一表面23a。
於一實施例中，該電子元件21之表面(如非主動面21b’,21b”)係外露於該包覆層23之第二表面23b。
於一實施例中，所述之封裝結構2,2’復包括一線路結構26，係設於該包覆層23之第一表面23a上並電性連接該電子元件21與該線路層22。
於一實施例中，所述之封裝結構2’復包括至少一電子裝置28，係堆疊於該包覆層23之第二表面23b上，且該電子裝置28藉由該線路重佈層25,25’電性連接至各該導電柱24之第二端24b。
綜上所述，本發明封裝結構及其製法，主要藉由先形成該線路層與導電柱，再形成該包覆層，故無需進行開孔製程，因而不僅省時、減少製程步驟及降低製作成本，且能提升該封裝結構之可靠度，並能縮小該封裝結構之尺寸。
再者，因無需進行開孔製程，故減少進行結合/移除承載件之步驟次數，因而能簡化製程，且同時降低製作成本。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧封裝結構
21‧‧‧電子元件
22‧‧‧線路層
23‧‧‧包覆層
23a‧‧‧第一表面
23b‧‧‧第二表面
24‧‧‧導電柱
24a‧‧‧第一端
24b‧‧‧第二端
25‧‧‧線路重佈層
26‧‧‧線路結構
263‧‧‧線路
27‧‧‧導電元件
29‧‧‧絕緣保護層

Claims (15)

  1. 一種封裝結構，係包括：包覆層，係具有相對之第一表面與第二表面；線路層，係自該包覆層之第一表面嵌埋於該包覆層；至少一電子元件，係嵌埋於該包覆層中；以及複數導電柱，係嵌埋於該包覆層中並立設於該線路層上，且該導電柱具有相對之第一端及第二端，並以其第一端結合至該線路層。
  2. 如申請專利範圍第1項所述之封裝結構，其中，該線路層之一表面係齊平該包覆層之第一表面。
  3. 如申請專利範圍第1項所述之封裝結構，其中，該電子元件之表面係齊平該包覆層之第一表面。
  4. 如申請專利範圍第1項所述之封裝結構，其中，該電子元件係外露於該包覆層之第二表面。
  5. 如申請專利範圍第1項所述之封裝結構，復包括線路結構，係形成於該包覆層之第一表面上並電性連接該電子元件與該線路層。
  6. 如申請專利範圍第1項所述之封裝結構，復包括至少一線路重佈層，係形成於該包覆層之第二表面上並電性連接各該導電柱之第二端。
  7. 如申請專利範圍第1項所述之封裝結構，復包括至少一電子裝置，係堆疊於該包覆層之第二表面上，且該電子裝置電性連接各該導電柱之第二端。
  8. 一種封裝結構之製法，係包括：準備一具有線路層之第一承載件；形成複數具有相對之第一端及第二端之導電柱於該線路層上，且各該導電柱以其第一端結合至該線路層，並設置至少一電子元件於該第一承載件上；形成具有相對之第一表面及第二表面之包覆層於該第一承載件上，以令該包覆層包覆該些導電柱、該線路層與該電子元件，且該包覆層之第一表面係結合至該第一承載件上；以及移除該第一承載件。
  9. 如申請專利範圍第8項所述之封裝結構之製法，其中，該線路層之表面係齊平該包覆層之第一表面。
  10. 如申請專利範圍第8項所述之封裝結構之製法，其中，該電子元件之表面係齊平該包覆層之第一表面。
  11. 如申請專利範圍第8項所述之封裝結構之製法，其中，該電子元件係外露於該包覆層之第二表面。
  12. 如申請專利範圍第8項所述之封裝結構之製法，復包括移除該第一承載件後，形成線路結構於該包覆層之第一表面上，且令該線路結構電性連接該電子元件與該線路層。
  13. 如申請專利範圍第12項所述之封裝結構之製法，復包括於移除該第一承載件前，先設置一第二承載件於該包覆層之第二表面上，待形成該線路結構後，移除該第二承載件。
  14. 如申請專利範圍第8項所述之封裝結構之製法，復包括形成至少一線路重佈層於該包覆層之第二表面上，且令該線路重佈層電性連接各該導電柱之第二端。
  15. 如申請專利範圍第8項所述之封裝結構之製法，復包括堆疊至少一電子裝置於該包覆層之第二表面上，使該電子裝置電性連接各該導電柱之第二端。
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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI584430B (zh) * 2014-09-10 2017-05-21 矽品精密工業股份有限公司 半導體封裝件及其製法
TWI552282B (zh) * 2014-11-03 2016-10-01 矽品精密工業股份有限公司 封裝結構及其製法
US9679873B2 (en) * 2015-06-18 2017-06-13 Qualcomm Incorporated Low profile integrated circuit (IC) package comprising a plurality of dies
CN107579061B (zh) 2016-07-04 2020-01-07 晟碟信息科技（上海）有限公司 包含互连的叠加封装体的半导体装置
TWI591739B (zh) * 2016-07-13 2017-07-11 矽品精密工業股份有限公司 封裝堆疊結構之製法
US10141276B2 (en) * 2016-09-09 2018-11-27 Powertech Technology Inc. Semiconductor package structure and manufacturing method thereof
CN106558574A (zh) * 2016-11-18 2017-04-05 华为技术有限公司 芯片封装结构和方法
TWI604542B (zh) * 2017-01-12 2017-11-01 矽品精密工業股份有限公司 封裝基板及其製法
CN106601702A (zh) * 2017-01-23 2017-04-26 合肥雷诚微电子有限责任公司 无基板高散热性的多芯片线性功率放大器结构及其制作方法
US10784220B2 (en) 2017-03-30 2020-09-22 Taiwan Semiconductor Manufacturing Co., Ltd. Plurality of semiconductor devices encapsulated by a molding material attached to a redistribution layer
CN108695284A (zh) * 2017-04-07 2018-10-23 晟碟信息科技（上海）有限公司 包括纵向集成半导体封装体组的半导体设备
CN109860126A (zh) * 2019-02-13 2019-06-07 中国科学院微电子研究所 一种大尺寸扇出封装结构及方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8236608B2 (en) * 2008-09-25 2012-08-07 King Dragon International Inc. Stacking package structure with chip embedded inside and die having through silicon via and method of the same
TW201415593A (zh) * 2012-10-11 2014-04-16 Ind Tech Res Inst 封裝基板及其製法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200302685A (en) * 2002-01-23 2003-08-01 Matsushita Electric Ind Co Ltd Circuit component built-in module and method of manufacturing the same
US9064936B2 (en) * 2008-12-12 2015-06-23 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US20120020040A1 (en) * 2010-07-26 2012-01-26 Lin Paul T Package-to-package stacking by using interposer with traces, and or standoffs and solder balls
KR101712043B1 (ko) * 2010-10-14 2017-03-03 삼성전자주식회사 적층 반도체 패키지, 상기 적층 반도체 패키지를 포함하는 반도체 장치 및 상기 적층 반도체 패키지의 제조 방법
US8546193B2 (en) * 2010-11-02 2013-10-01 Stats Chippac, Ltd. Semiconductor device and method of forming penetrable film encapsulant around semiconductor die and interconnect structure
JP2011082583A (ja) * 2011-01-25 2011-04-21 Aoi Electronics Co Ltd 半導体装置および半導体装置の製造方法
US9095085B2 (en) * 2013-03-29 2015-07-28 Kinsus Interconnect Technology Corp. Method of manufacturing a stacked multilayer structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8236608B2 (en) * 2008-09-25 2012-08-07 King Dragon International Inc. Stacking package structure with chip embedded inside and die having through silicon via and method of the same
TW201415593A (zh) * 2012-10-11 2014-04-16 Ind Tech Res Inst 封裝基板及其製法

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