TW201507098A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TW201507098A
TW201507098A TW103110231A TW103110231A TW201507098A TW 201507098 A TW201507098 A TW 201507098A TW 103110231 A TW103110231 A TW 103110231A TW 103110231 A TW103110231 A TW 103110231A TW 201507098 A TW201507098 A TW 201507098A
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Taiwan
Prior art keywords
semiconductor wafer
bump electrode
wafer
electrode
formation layer
Prior art date
Application number
TW103110231A
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English (en)
Inventor
Mitsuhisa Watanabe
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Ps4 Luxco Sarl
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Publication date
Application filed by Ps4 Luxco Sarl filed Critical Ps4 Luxco Sarl
Publication of TW201507098A publication Critical patent/TW201507098A/zh

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    • H—ELECTRICITY
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Abstract

本發明的半導體裝置的晶片層積體11，具有；與第1半導體晶片(中間記憶體晶片2b)和第2半導體晶片(IF晶片3)層積的構成。第1半導體晶片，具有：形成在一方之面的電路形成層及第1凸塊電極(表面凸塊電極22a)；和形成在另一方之面的第2凸塊電極(背面凸塊電極23a)。第2半導體晶片，具有：形成在一方之面的電路形成層及第3凸塊電極(表面凸塊電極22b)；和形成在另一方之面的第4凸塊電極(背面凸塊電極23b)。以與第1半導體晶片的電路形成層和第2半導體晶片的電路形成層相對向，且與第1凸塊電極和第3凸塊電極電性連接的方式，與第1半導體晶片和第2半導體晶片層積。

Description

半導體裝置及其製造方法
本發明是有關一種半導體裝置及其製造方法。
近年隨著電子機器的小型化和高機能化，提供一種層積具有電極的複數個半導體晶片的CoC(Chip on Chip：疊晶)型的半導體裝置。
作為此種半導體裝置之製造方法的其中一例，將具有電極的半導體晶片彼此，將互相的凸塊電極彼此一邊連接、一邊層積而形成晶片層積體，將晶片層積體搭載在配線基板之一方的面而形成半導體裝置的方法，是揭示於專利文獻1(日本特開第2011-129684號公報)。於晶片層積體，以未因熱應力而發生各半導體晶片的電極彼此的連接部的破斷和半導體晶片本身的裂痕之方式，且以覆蓋已層積的半導體晶片彼此之間與各半導體晶片之周圍的方式，填充底層填材及密封樹脂層。
[先行技術文獻] [專利文獻]
[專利文獻1]日本特開第2011-129684號公報
在專利文獻1揭示的CoC型的半導體裝置中，與第1半導體晶片和第2半導體晶片層積的晶片層積體，是以與形成第2半導體晶片的電路形成層之一方的面和配線基板之一方的面相對向的方式，搭載在配線基板之一方的面。其中一例，第1半導體晶片為記憶體晶片、第2半導體晶片為IF(Interface：介面)晶片。在晶片層積體之形成時，為了將與第2半導體晶片的配線基板相對向的面呈相反側的面，亦即未電路形成層之另一方的面，層積在其他的半導體晶片之上，形成第2半導體晶片的電路形成層之一方的面，是藉由接合工具被吸引保持。接合工具，是用來吸引保持形成第2半導體晶片的電路形成層之一方的面，有可能會發生第2半導體晶片的電路形成層的損傷，亦即在電路形成層內的電路的切斷，使半導體裝置的可靠性降低。
為了達成前述之目的的本發明之半導體裝置，包含：與第1半導體晶片和第2半導體晶片層積的晶片層積體。第1半導體晶片，具有：基板；和形成在基板 之一方的面的電路形成層；和形成於配置在電路形成層的電極銲墊上的第1凸塊電極；和形成在基板之另一方的面的第2凸塊電極；和與第1凸塊電極和第2凸塊電極電性連接的第1貫通電極。第2半導體晶片，具有：基板；和形成在基板之一方的面的電路形成層；和形成於配置在電路形成層的電極銲墊上的第3凸塊電極；和形成在基板之另一方的面的第4凸塊電極；和與第3凸塊電極和第4凸塊電極電性連接的第2貫通電極。以與第1半導體晶片的電路形成層和第2半導體晶片的電路形成層相對向，且與第1凸塊電極和第3凸塊電極電性連接的方式，與第1半導體晶片和第2半導體晶片層積。
若藉由本發明，以第2半導體晶片之一方的面的電路形成層為與第1半導體晶片相對向的方式，層積第1半導體晶片和第2半導體晶片。因此，在與第1半導體晶片和第2半導體晶片的層積時，保持未形成第2半導體晶片的電路形成層之另一方的面側，使第2半導體晶片層積在第1半導體晶片上。形成電路形成層的第2半導體晶片之形成電路形成層的一方的面側未被保持，因此第2半導體晶片的電路形成層難以損傷。
1‧‧‧半導體裝置
3‧‧‧IF晶片(第2半導體晶片)
2b‧‧‧中間記憶體晶片(第1半導體晶片)
2a‧‧‧最上段記憶體晶片(第3半導體晶片)
11‧‧‧晶片積層體
12‧‧‧配線基板
12a‧‧‧絕緣基材(例如：玻璃環氧基板)
12b‧‧‧絕緣膜：(例如：抗焊膜)
13‧‧‧底層填材
14‧‧‧密封樹脂
15‧‧‧連接銲墊
16‧‧‧焊盤
17‧‧‧焊球
18‧‧‧焊線凸塊
19‧‧‧接著構件
21‧‧‧矽基板
22a‧‧‧表面凸塊電極(第1凸塊電極)
22b‧‧‧表面凸塊電極(第3凸塊電極)
22c‧‧‧表面凸塊電極(第5凸塊電極)
23a‧‧‧背面凸塊電極(第2凸塊電極)
23b‧‧‧背面凸塊電極(第4凸塊電極)
24‧‧‧補強凸塊電極
25a‧‧‧貫通電極
25b‧‧‧貫通電極
26‧‧‧焊料層
27‧‧‧電路形成層
29‧‧‧鍍Ni層
33‧‧‧配線
34‧‧‧接合平台
34a‧‧‧吸引孔
35‧‧‧接合工具
35a‧‧‧吸引孔
35b‧‧‧凸塊排除溝
36‧‧‧分配器
37‧‧‧塗佈平台
38‧‧‧塗佈用薄片
39‧‧‧切割線
[第1圖]表示本發明之一實施形態的半導體裝置的剖面圖。
[第2圖]表示第1圖所示的半導體裝置的凸塊電極彼此的連接部的放大剖面圖。
[第3a圖]表示記憶體晶片之一方的面的平面圖。
[第3b圖]表示IF晶片之另一方的面的底面圖。
[第4a圖]表示層積複數個記憶體晶片及IF晶片而形成晶片層積體的工程的剖面圖。
[第4b圖]表示層積複數個記憶體晶片及IF晶片而形成晶片層積體的工程的剖面圖。
[第4c圖]表示層積複數個記憶體晶片及IF晶片而形成晶片層積體的工程的剖面圖。
[第4d圖]表示層積複數個記憶體晶片及IF晶片而形成晶片層積體的工程的剖面圖。
[第5圖]表示將第1圖所示的半導體裝置的IF晶片層積在記憶體晶片之上時的凸塊電極彼此的連接部的放大圖。
[第6a圖]表示形成半導體裝置的工程的剖面圖。
[第6b圖]表示形成半導體裝置的工程的剖面圖。
[第6c圖]表示形成半導體裝置的工程的剖面圖。
[第6d圖]表示形成半導體裝置的工程的剖面圖。
[第6e圖]表示形成半導體裝置的工程的剖面圖。
[第7a圖]表示層積複數個記憶體晶片及IF晶片而形成晶片層積體的工程的變形例的剖面圖。
[第7b圖]表示層積複數個記憶體晶片及IF晶片而形成晶片層積體的工程的變形例的剖面圖。
[第7c圖]表示層積複數個記憶體晶片及IF晶片而形成晶片層積體的工程的變形例的剖面圖。
[第7d圖]表示層積複數個記憶體晶片及IF晶片而形成晶片層積體的工程的變形例的剖面圖。
以下針對本發明的實施形態參照圖面做說明。
第1圖是表示本發明的CoC型的半導體裝置的剖面圖。
半導體裝置1，是在配線基板12之一方的面搭載著IF晶片3(第2半導體晶片)，且在IF晶片3之一方的面上，層積著三片的中間記憶體晶片2b(第1半導體晶片)和一片的最上段記憶體晶片2a(第3半導體晶片)的構成。IF晶片3、最上段記憶體晶片2a、中間記憶體晶片2b，是構成晶片層積體11。在晶片層積體11的各晶片彼此之間隙填充底層填材13。在與配線基板12和IF晶片3之間填充接著構件19。密封樹脂14覆蓋晶片層積體11的周圍。
以下，詳細說明半導體裝置1的構成。
配線基板12，具有：於兩面形成圖未表示的配線的矩形絕緣基材12a(例如玻璃環氧基板)，各配 線，除了後述的連接銲墊15和焊盤(land)16之外，皆覆蓋在絕緣膜12b(例如抗焊膜)。與成為外部端子的焊球17連接的複數個焊盤16是以既定的間隔形成在配線基板12之另一方的面。與一方的面的連接銲墊15和另一方的面的焊盤16，是藉由形成在絕緣基材12a之內部的配線電性連接。
如第1圖及第2圖所示，與連接銲墊15和晶 片層積體11的IF晶片3之另一方的面的背面凸塊電極23b(第4凸塊電極)，是以隔著焊線凸塊18電性連接的方式，使晶片層積體11搭載在配線基板12之一方的面。 此時，以與配線基板12之一方的面和未形成IF晶片3的電路形成層27之另一方的面相對向的方式，使晶片層積體11搭載在配線基板12。晶片層積體11，是具有：於層積在配線基板12的順序觀看，使一片的IF晶片3、三片的中間記憶體晶片2b、一片的最上段記憶體晶片2a層積的構成。以與IF晶片3之一方的面的電路形成層27和中間記憶體晶片2b之一方的面的電路形成層27相對向，且使中間記憶體晶片2b之一方的面的表面凸塊電極22a(第1凸塊電極)，連接在IF晶片3之一方的面的表面凸塊電極22b(第3凸塊電極)的方式，使中間記憶體晶片2b層積在IF晶片3之上。以使第二片的中間記憶體晶片2b之一方的面的表面凸塊電極22a，連接在第一片的中間記憶體晶片2b之另一方的面的背面凸塊電極23a(第2凸塊電極)方式，使中間記憶體晶片2b彼此層 積。而且，第三片的中間記憶體晶片2b，是與第二片的中間記憶體晶片2b同樣的層積。進而，以與未形成第三片的中間記憶體晶片2b的電路形成層27之另一方的面和形成最上段記憶體晶片2a的電路形成層27之一方的面相對向，且使最上段記憶體晶片2a之一方的面的表面凸塊電極22c(第5凸塊電極)，連接在第三片的中間記憶體晶片2b之另一方的面的背面凸塊電極23a的方式，使第三片的中間記憶體晶片2b和最上段記憶體晶片2a層積。
於晶片的層積方向觀看，最上段記憶體晶片 2a的厚度，是為了提高對於在後述的晶片層積體11內所發生的應力的剛性，因此比中間記憶體晶片2b的厚度還厚。若舉其中一例，最上段記憶體晶片2a是厚度100μm，中間記憶體晶片2b和IF晶片3是厚度50μm。在本實施形態中，晶片層積體11雖是以五片的晶片構成，但晶片層積體11，也可以為藉由四片以下，或六片以上的晶片構成。
由環氧系樹脂等製成的底層填材13，是填充 在晶片層積體11之所層積的晶片彼此之間及其周圍。例如NCP(Non Conductive Paste：非導電性絕緣膠)等的接著構件19，是填充在配線基板12和晶片層積體11的IF晶片3之間。密封樹脂14，是形成覆蓋搭載在配線基板12之一方的面的晶片層積體11的周圍。密封樹脂14，於平面觀看，形成在與配線基板12相同範圍。
第3a圖是表示構成晶片層積體11的記憶體 晶片2a、2b之一方的面的平面圖。記憶體晶片2a、2b，是以矩形的矽基板21構成，在矽基板21之一方的面，使電路形成層27及絕緣膜12b(參照第2圖)全面設置。 在矽基板21之一方的面的中央區域，複數個表面凸塊電極22a、22c，是形成位於配置在電路形成層27的電極銲墊28上，成為平行於矽基板21之一邊的列。而且，複數個補強凸塊電極24，是形成在沿著矽基板21之一對的邊，成為平行於表面凸塊電極22a、22c之列的列。該補強凸塊電極24，是作為凸塊電極的補強，或是連接在電源和GND作為電源和GND的補強。如第2圖所示，各個的表面凸塊電極22a、22b，是形成例如：由Cu(銅)製成的圓柱狀，設成自矽基板21之一方的面突出。而且，使Cu(銅)擴散防止用的鍍Ni(鎳)層2和氧化防止用的鍍Au(金)層30，形成在各個的表面凸塊電極22a、22b上。
中間記憶體晶片2b，具有：從一方的面的表 面凸塊電極22a向著另一方的面貫通的貫通電極25a。在中間記憶體晶片2b的矽基板21之另一方的面，複數個背面凸塊電極23a，是在與一方的面的表面凸塊電極22a對應的位置成列而形成。背面凸塊電極23a，是與露出於另一方的面的貫通電極25a電性連接。亦即，中間記憶體晶片2b的貫通電極25a及背面凸塊電極23a，是於平面觀看配置於重疊在表面凸塊電極22a的位置。各個的背面凸塊電極23a，是例如：由Cu(銅)製成的圓柱狀，設成自矽 基板21之另一方的面突出。在中間記憶體晶片2b的背面凸塊電極23a的表面上，設有例如：由Sn(錫)/Ag(金)焊料製成的導電性的焊料層26。而且，與一方的面同樣的，複數個補強凸塊電極24，是形成沿著矽基板21之一對的邊，成為平行於表面凸塊電極22a之列的列。另一方的面的補強凸塊電極24，是隔著貫通電極25a與一方的面的補強凸塊電極24連接。
在最上段記憶體晶片2a之另一方的面，如第1圖所示，未設背面凸塊電極及補強凸塊電極。而且，為了提高晶片的剛性不設貫通電極。
第3b圖是表示構成晶片層積體11的IF晶片3之另一方的面的底面圖。IF晶片3，是以平面比記憶體晶片2a、2b還小型的矩形矽基板21構成，在矽基板21之一方的面，將電路形成層27及絕緣膜12b(參照第2圖)全面設置。而且，在矽基板21之一方的面，複數個表面凸塊電極22b，是在配置在電路形成層27的電極銲墊上，形成在與設有記憶體晶片2a、2b之一方的面的表面凸塊電極22a、22c的位置相對應的位置。在矽基板21之另一方的面，與設有記憶體晶片2a、2b之一方的面的表面凸塊電極22a、22c的位置相比，在靠近矽基板21的端部側的位置，成為平行於矽基板之一邊的列的方式，形成複數個背面凸塊電極23b。IF晶片3的背面凸塊電極23b比表面凸塊電極22b還少，背面凸塊電極23b的列內的背面凸塊電極23b彼此的間隔，比表面凸塊電極22b的 列內的表面凸塊電極22b彼此的間隔還寬。
IF晶片3，具有：由另一方的面的背面凸塊電極23b向一方的面貫通，且成列而形成的貫通電極25b。與形成在一方的面的表面凸塊電極22b和露出於IF晶片3之一方的面之對應的貫通電極25b，是再利用配線33電性連接。而且，IF晶片3的貫通電極25b是與背面凸塊電極23b的數量相等，比表面凸塊電極22b的數量還少。IF晶片3的貫通電極25b及背面凸塊電極23b，是於平面觀看配置在未與表面凸塊電極22b重疊的位置。而且，IF晶片3的貫通電極25b的列內的貫通電極25b彼此的間隔，比中間記憶體晶片2b的貫通電極25a的列內的貫通電極25a彼此的間隔還寬。若舉其中一例，IF晶片3的貫通電極25b彼此的間隔，是構成200μm以上。
在一般的CoC型的半導體裝置1中，周圍環境的溫度變高溫，藉此貫通電極25會受到連繫設在晶片之一方的面與另一方的面的電極彼此產生膨脹，應力集中在晶片層積體11的最上段及最下段的晶片。在CoC型的半導體裝置1中，位於最下段的IF晶片3，一旦設在IF晶片3的貫通電極25b彼此的間隔狹小，即有容易因所發生的應力而產生晶片裂痕的課題。
對此，在本實施形態中，IF晶片3的貫通電極25b的數量少，列內的貫通電極25b彼此的間隔寬，由於對於在半導體裝置1之內部所發生的應力的IF晶片3的剛性提高，因此裂痕難以進入到貫通電極25b彼此之 間。因此，半導體裝置1的可靠性提升。除此之外，IF晶片3的電路形成層27，是配置成未相對向於配線基板12之一方的面，因此寄生電容的發生受抑制。
其次，針對製造具有以上說明的構成的半導體裝置1的工程，參照第4a圖~第6e圖做說明。
首先，為了形成晶片層積體11，如第4a圖所示，在具有吸引孔34a的接合平台34，以未形成最上段記憶體晶片2a的電路形成層27的另一方之面接觸的方式，配置最上段記憶體晶片2a。像這樣配置的最上段記憶體晶片2a，會因吸引孔34a所發生的負壓被保持在接合平台34。
一方面，中間記憶體晶片2b，會因接合工具35的吸引孔35a所發生的負壓被保持在接合工具35，接合工具35會使中間記憶體晶片2b往接合平台34的正上方移動。此時，不會與形成接合工具35和中間記憶體晶片2b的電路形成層27之一方的面接觸，會與接合工具35和表面凸塊電極22a接觸。而且，以與最上段記憶體晶片2a的表面凸塊電極22c和中間記憶體晶片2b的背面凸塊電極23a連接的方式，使中間記憶體晶片2b層積在最上段記憶體晶片2a之上。此時，以與未形成中間記憶體晶片2b的電路形成層27之另一方的面和形成最上段記憶體晶片2a的、電路形成層27之一方的面相對向的方式，使中間記憶體晶片2b和最上段記憶體晶片2a層積。按同樣的順序，使第二片及第三片的中間記憶體晶片2b 層積在第一片的中間記憶體晶片2b之上。
接著，如第4b圖所示，層積IF晶片3。IF晶 片3，即使因吸引孔35a所發生的負壓被保持在另一個接合工具35，接合工具35仍會使IF晶片3往接合平台34的正上方移動。此時，如第5圖所示，IF晶片3的表面凸塊電極22b，被收容在另一個接合工具35的凸塊排除溝35b，與另一個接合工具35和未形成IF晶片3的電路形成層27之另一方的面接觸。而且，以與IF晶片3之一方的面的電路形成層27和第三片的中間記憶體晶片2b之一方的面的電路形成層27相對向，且與中間記憶體晶片2b的表面凸塊電極22a和IF晶片3的表面凸塊電極22b連接的方式，使IF晶片3層積在第三片的中間記憶體晶片2b之上。如此一來，只要層積各晶片，就能使具有各晶片的各個焊料層26硬化。如以上，層積複數個晶片，形成晶片層積體11。
已形成的晶片層積體11，如第4c圖所示，一 方的面是配置在以塗佈用薄片38覆蓋的塗佈平台37。而且，底層填材13會藉由分配器36被填充在晶片層積體11的間隙。作為塗佈用薄片38，可使用氟系薄片和塗佈矽系接著劑的薄片等，對底層填材之濕潤性小的材料。然後，晶片層積體11全體，是以既定的溫度例如：150℃左右被熱處理，只要底層填材硬化就能從塗佈平台37被取出。按此，如第4d圖所示，形成填充底層填材13的晶片層積體11。在本實施形態中，作為塗佈用薄片38，使用 由：對底層填材13之濕潤性小的材料製成的薄片，因此，底層填材硬化時，底層填材13難以附著在塗佈用薄片38。
其次，如第6a圖所示，準備配線基板12。作 為配線基板12，可使用於兩面形成圖未表示的配線的絕緣基材12a(例如玻璃環氧基板)。在絕緣基材12a之一方的面，形成：複數個連接銲墊15；和設在連接銲墊15的表面供與IF晶片3連接的焊線凸塊18。在絕緣基材12a之另一方的面，與成為外部端子的焊球17連接的複數個焊盤16是以既定的間隔形成例如：格子狀。複數個連接銲墊15和複數個焊盤16，是以貫通絕緣基材12a的配線電性連接。絕緣基材12a的兩面的各配線，除了連接銲墊15與焊盤16之外，皆利用抗焊膜等的絕緣膜12b覆蓋。而且，配線基板12，是利用切割線39分割成為半導體裝置1的區域。
在配線基板12之一方的面，以覆蓋連接銲墊 15及焊線凸塊18的方式，塗佈未硬化的接著構件19例如：NCP(非導電性絕緣膠)。在已塗佈的接著構件19硬化之前，如第6b圖所示，以與配線基板12之一方的面和未形成晶片層積體11的IF晶片3的電路形成層27之另一方的面相對向的方式，使晶片層積體11層積在配線基板12。此時，配線基板12的焊線凸塊18和晶片層積體11的IF晶片3的表面凸塊電極22b，是隔著焊料層26連接。而且，像這樣使晶片層積體11搭載在配線基板12 之一方的面，使晶片層積體11的最上段記憶體晶片2a配置在離配線基板12最遠的位置。
使晶片層積體11搭載在配線基板12之後， 配線基板12，為了以密封樹脂14覆蓋晶片層積體11，因此安裝在由圖未表示的移轉成型裝置的上模和下模製成的模具。在模具的上模，形成一併覆蓋複數個晶片的圖未表示的模槽，在該模槽內收容晶片層積體11。然後，對模槽內注入已加熱溶融的密封樹脂14，晶片層積體11在模槽內被密封樹脂14覆蓋。作為密封樹脂14，可使用例如：環氧樹脂等的熱硬化性樹脂。
接著，在將模槽內以密封樹脂14填充的狀態 下，以既定的溫度(例如180℃左右)使密封樹脂14硬化。像這樣，如第6c圖所示，形成覆蓋搭載在配線基板12之一方的面的晶片層積體11的密封樹脂14，以既定的溫度烘烤密封樹脂14，使密封樹脂14硬化。在本實施形態中，各晶片彼此之間的間隙利用底層填材13及接著構件19填充之後，形成密封樹脂14，因此能抑制起因於存在在各晶片彼此之間的間隙的空氣所產生的氣泡。
使密封樹脂14形成在配線基板12之一方的 面之後，如第6d圖所示，使成為半導體裝置1之外部端子的導電性的金屬球例如：焊球17，連接於形成在配線基板12之另一方的面的焊盤16。複數個焊球17，可以藉由具備形成與配線基板12的各焊盤16之位置一致的複數個吸附孔之圖未表示的植球工具吸附保持，且一併搭載在 各焊盤16上。接著，將配線基板12全體進行回焊，與各焊盤16和各焊球17連接。使焊球17連接在焊盤16之後，如第6e圖所示，配線基板12沿著既定的切割線39被切斷分離，形成複數個CoC型的半導體裝置1。
一旦藉由此製造方法，如第4b圖所示，在IF 晶片3層積在中間記憶體晶片2b之際，未形成IF晶片3的電路形成層27的另一方之面被保持在接合工具35。此結果，電路形成層27未接觸到接合工具35，因此難以傷及IF晶片3的電路形成層27。因此，形成在電路形成層27的電路難以被切斷，半導體裝置1的可靠性提升。
第7a圖~第7d圖是表示形成以上說明的半導體裝置1的晶片層積體11的工程的變形例的剖面圖。
在本變形例中，如第7a圖、第7b圖所示，使設有中間記憶體晶片2b之NCF(Non Conductive Film：非導電性薄膜)的另一方的面，層積在最上段記憶體晶片2a之上。同樣的，如第7c圖所示，使設有IF晶片3之NCF的一方的面，層積在第三片的中間記憶體晶片2b之上。NCF，是薄膜狀的環氧系等的樹脂，晶片彼此之接合時，為了使凸塊電極彼此良好連接含有助溶劑活性材。作為助溶劑活性材，舉例有例如：有機酸和胺。而且，在NCF含有助溶劑活性材，因此以覆蓋各晶片的凸塊電極的方式，設置NCF之後，即使連接晶片彼此，凸塊電極彼此仍會良好連接。
按此所形成的晶片層積體11，如第7d圖所 示，由於已經在晶片彼此之間填充NCF，因此不必填充底層填材13。因而，填充底層填材13的工程省略，因此製造效率提升，半導體裝置1的製造成本受抑制。
以上，雖是針對本發明之半導體裝置的具體 構成根據各實施形態做說明，但本發明並不限於前述的實施形態，在不脫離本發明之主旨的範圍，當然可對前述的實施形態做各種的變更。例如，在前述的各實施形態中，雖是針對由四片的記憶體晶片和一片的IF晶片製成的晶片層積體做說明，但只要是層積記憶體晶片和邏輯晶片的層積體等複數個半導體晶片的構成，即適用本發明。
1‧‧‧半導體裝置
2a‧‧‧最上段記憶體晶片
2b‧‧‧中間記憶體晶片
3‧‧‧IF晶片
11‧‧‧晶片層積體
12‧‧‧配線基板
12a‧‧‧絕緣基材
12b‧‧‧絕緣膜
13‧‧‧底層填材
14‧‧‧密封樹脂
15‧‧‧銲墊
16‧‧‧焊盤
17‧‧‧焊球
18‧‧‧焊線凸塊
19‧‧‧接著構件
22a、22b、22c‧‧‧表面凸塊電極
23a、23b‧‧‧背面凸塊電極
24‧‧‧補強凸塊電極
25a、25b‧‧‧貫通電極
26‧‧‧焊料層

Claims (11)

  1. 一種半導體裝置，其設有：具有：基板；和形成在前述基板之一方的面的電路形成層；和形成於配置在前述電路形成層的電極銲墊上的第1凸塊電極；和形成在前述基板之另一方的面的第2凸塊電極；和與前述第1凸塊電極和前述第2凸塊電極電性連接的第1貫通電極的第1半導體晶片；和具有：基板；和形成在前述基板之一方的面的電路形成層；和形成於配置在前述電路形成層的電極銲墊上的第3凸塊電極；和形成在前述基板之另一方的面的第4凸塊電極；和與前述第3凸塊電極和前述第4凸塊電極電性連接的第2貫通電極的第2半導體晶片；包含：以與前述第1半導體晶片的前述電路形成層和前述第2半導體晶片的前述電路形成層相對向，且與前述第1凸塊電極和前述第3凸塊電極電性連接的方式，與前述第1半導體晶片和前述第2半導體晶片層積的晶片層積體。
  2. 如申請專利範圍第1項所記載的半導體裝置，其中，以具有使連接銲墊形成在一方的面的配線基板，與前述配線基板之前述一方的面和未形成前述第2半導體晶片的前述電路形成層之前述另一方的面相對向，且與前述連接銲墊和前述第4凸塊電極電性連接的方式，使前述晶片層積體搭載在前述配線基板之前述一方的面。
  3. 一種半導體裝置，其特徵為：設有：具有：基板；和形成在前述基板之一方的面的電路形成層；和形成於配置在前述電路形成層的電極銲墊上的第1凸塊電極；和形成在前述基板之另一方的面的第2凸塊電極；和與前述第1凸塊電極和前述第2凸塊電極電性連接的第1貫通電極的第1半導體晶片；和基板；和形成在前述基板之一方的面的電路形成層；和形成於配置在前述電路形成層的電極銲墊上的第3凸塊電極；和形成在前述基板之另一方的面的第4凸塊電極；和與前述第3凸塊電極和前述第4凸塊電極電性連接的第2貫通電極的第2半導體晶片；和具有：基板；和形成在前述基板之一方的面的電路形成層；和形成於配置在前述電路形成層的電極銲墊上的第5凸塊電極的第3半導體晶片；和由絕緣基材製成，使連接銲墊形成在一方的面的配線基板；以與前述第1半導體晶片的前述電路形成層和前述第2半導體晶片的前述電路形成層相對向，且與前述第1凸塊電極和前述第3凸塊電極電性連接的方式，使前述第1半導體晶片和前述第2半導體晶片層積，以與未形成前述第1半導體晶片的前述電路形成層之前述另一方的面和前述第3半導體晶片的前述電路形成層相對向，且與前述第2凸塊電極和前述第5凸塊電極電性連接的方式，使前述 第3半導體晶片層積在前述第1半導體晶片，形成晶片層積體；以與前述配線基板之前述一方的面和未形成前述第2半導體晶片的前述電路形成層之前述另一方的面相對向，且與前述連接銲墊和前述第4凸塊電極電性連接的方式，使前述晶片層積體搭載在前述配線基板之前述一方的面。
  4. 如申請專利範圍第3項所記載的半導體裝置，其中，於前述第1半導體晶片與前述第3半導體晶片的層積方向觀看，前述第3半導體晶片的厚度比前述第1半導體晶片的厚度還厚。
  5. 如申請專利範圍第1項至第4項之任一項所記載的半導體裝置，其中，前述第4凸塊電極比前述第3凸塊電極還少。
  6. 如申請專利範圍第1項至第5項之任一項所記載的半導體裝置，其中，前述第2貫通電極比前述第1貫通電極還少。
  7. 如申請專利範圍第1項至第6項之任一項所記載的半導體裝置，其中，前述第1半導體晶片之前述第1貫通電極及第2凸塊電極，於平面觀看配置於重疊在前述第1凸塊電極的位置；前述第2半導體晶片的前述第2貫通電極及第4凸塊電極，於平面觀看配置在未重疊於前述第3凸塊電極的位 置。
  8. 一種半導體裝置之製造方法，針對包含：層積著在一方之面形成第1凸塊電極及電路形成層，在另一方之面形成第2凸塊電極的第1半導體晶片；和在一方之面形成第3凸塊電極及電路形成層，在另一方之面形成第4凸塊電極的第2半導體晶片；和在一方之面形成第5凸塊電極及電路形成層的第3半導體晶片的構成的晶片層積體的半導體裝置之製造方法中，其包含：以與未形成前述第1半導體晶片的前述電路形成層之前述另一方的面和前述第3半導體晶片的前述電路形成層相對向，且與前述第2凸塊電極和前述第5凸塊電極電性連接的方式，層積前述第1半導體晶片和前述第3半導體晶片的工程；和以與前述第1半導體晶片的前述電路形成層和前述第2半導體晶片的前述電路形成層相對向，且與前述第1凸塊電極和前述第3凸塊電極電性連接的方式，使前述第2半導體晶片層積在前述第1半導體晶片之前述一方的面的工程；和以與形成配線基板的連接銲墊之一方的面和未形成前述第2半導體晶片的前述電路形成層的另一方之面相對向，且與前述連接銲墊和前述第4凸塊電極電性連接的方式，將與前述第1半導體晶片、前述第2半導體晶片、前述第3半導體晶片層積而構成的晶片層積體，搭載在前述配線基板之前述一方的面的工程。
  9. 如申請專利範圍第8項所記載的半導體裝置之製造方法，其中，於前述第1半導體晶片與前述第3半導體晶片的層積方向觀看，前述第3半導體晶片的厚度比前述第1半導體晶片的厚度還厚。
  10. 如申請專利範圍第8項或第9項所記載的半導體裝置之製造方法，其中，前述第4凸塊電極比前述第3凸塊電極還少。
  11. 如申請專利範圍第8項至第10項之任一項所記載的半導體裝置之製造方法，其中，在將前述第2半導體晶片層積在前述第1半導體晶片的工程中，包含：將未形成前述第2半導體晶片的前述電路形成層的前述另一方之面，藉由接合工具保持，層積在前述第1半導體晶片之上。
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