JP2012146853A - 半導体装置の製造方法 - Google Patents
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Abstract
【解決手段】キャリア基板10の上に複数の半導体チップ11a〜11dを積層したチップ積層体3Aを形成する工程と、キャリア基板10及び複数の半導体チップ11a〜11dの各隙間に第1の封止体4を充填しながら、チップ積層体3Aを第1の封止体4で封止する工程と、配線基板2となる部分が複数並んで形成された母配線基板の一面に、この母配線基板とキャリア基板10との間で複数の半導体チップ11a〜11dを挟み込むように、チップ積層体3Aを配線基板2となる部分毎に実装する工程と、第1の封止体4で封止されたチップ積層体3Aの全体を覆うように母配線基板の一面側を第2の封止体5で封止する工程と、母配線基板を配線基板2となる部分毎に切断することによって個々の半導体装置1に分割する工程とを含む。
【選択図】図1
Description
なお、以下の説明で用いる図面は、特徴をわかりやすくするために、便宜上特徴となる部分を拡大して示している場合があり、各構成要素の寸法比率などが実際と同じであるとは限らない。また、以下の説明において例示される材料、寸法等は一例であって、本発明はそれらに必ずしも限定されるものではなく、その要旨を変更しない範囲で適宜変更して実施することが可能である。
先ず、本発明を適用して製造される半導体装置の一例として、図1に示すCoC型の半導体パッケージ1について説明する。
この半導体パッケージ1は、図1に示すように、配線基板2と、この配線基板2の一面(上面)に実装されたチップ積層体3Aと、このチップ積層体3Aを封止する第1の封止体4と、この第1の封止体4を覆った状態で配線基板2の一面を封止する第2の封止体5と、配線基板2の他面(下面)に配置された複数のはんだボール(外部接続端子)6とを備えることによって、BGA(Ball Grid Array)と呼ばれるパッケージ構造を有している。
次に、本発明を適用した半導体装置の製造方法として、上記図1に示す半導体パッケージ1の製造工程について説明する。
上記半導体パッケージ1を製造する際は、先ず、図2A〜図2Dに示すように、キャリア基板10の上に複数の半導体チップ11a〜11eを積層したチップ積層体3Aを形成する。
例えば、上記実施形態では、上記チップ積層体3Aを第1の封止体4で封止する工程を、母キャリア基板10Aを切断して個々のチップ積層体3Aに分割する工程の前に行う場合について説明したが、本発明では、上記チップ積層体3Aを第1の封止体4で封止する工程を、母キャリア基板10Aを切断して個々のチップ積層体3Aに分割する工程の後に行うことも可能である。
Claims (9)
- キャリア基板の上に複数の半導体チップを積層したチップ積層体を形成する工程と、
前記キャリア基板及び前記複数の半導体チップの各隙間に第1の封止体を充填しながら、前記チップ積層体を第1の封止体で封止する工程と、
前記配線基板となる部分が複数並んで形成された母配線基板の一面に、この母配線基板と前記キャリア基板との間で前記複数の半導体チップを挟み込むように、前記チップ積層体を前記配線基板となる部分毎に実装する工程と、
前記第1の封止体で封止されたチップ積層体の全体を覆うように前記母配線基板の一面側を第2の封止体で封止する工程と、
前記母配線基板を前記配線基板となる部分毎に切断することによって個々の半導体装置に分割する工程とを含むことを特徴とする半導体装置の製造方法。 - 前記チップ積層体を形成する工程は、前記キャリア基板となる部分が複数並んで設けられた母キャリア基板の一面に、前記複数の半導体チップを順次積層しながら前記キャリア基板となる部分毎に実装する工程と、
前記母キャリア基板を前記キャリア基板となる部分毎に切断することによって個々のチップ積層体に分割する工程とを含むことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記チップ積層体を前記第1の封止体で封止する工程を、前記母キャリア基板を切断して個々のチップ積層体に分割する工程の前に行うことを特徴とする請求項1又は2に記載の半導体装置の製造方法。
- 前記チップ積層体を前記第1の封止体で封止する工程を、前記母キャリア基板を切断して個々のチップ積層体に分割する工程の後に行うことを特徴とする請求項1又は2に記載の半導体装置の製造方法。
- 前記チップ積層体を形成する工程は、一面側に第1の接続端子を有するキャリア基板と、一面側に第1の接続端子及び他面側に第2の接続端子と、これら第1の接続端子と第2の接続端子との間を接続する貫通電極とを有する複数の半導体チップとを用意し、それぞれの一面と他面とを対向させながら、それぞれの間にある前記第1の接続端子と前記第2の接続端子とを接合して積層することにより行うことを特徴とする請求項1〜4の何れか一項に記載の半導体装置の製造方法。
- 前記チップ積層体を前記母配線基板に実装する工程は、前記配線基板となる部分に第3の接続端子が設けられた母配線基板を用意し、この母配線基板の前記配線基板となる部分毎に、前記チップ積層体の最上層に位置する半導体チップを下方に向けた状態で、この半導体チップの一面と前記配線基板となる部分とを対向させながら、その間にある前記第3の接続端子と前記第1の接続端子とを接合することにより行うことを特徴とする請求項1〜5の何れか一項に記載の半導体装置の製造方法。
- 前記キャリア基板と前記配線基板には、同じ材質のものを用いることを特徴とする請求項1〜6の何れか一項に記載の半導体装置の製造方法。
- 前記チップ積層体を前記配線基板となる部分毎に実装する際に、前記チップ積層体と前記配線基板となる部分との間に接着部材を設け、この接着部材を介して前記チップ積層体を前記配線基板となる部分に接着固定することを特徴とする請求項1〜7の何れか一項に記載の半導体装置の製造方法。
- 前記母配線基板を切断する工程の前に、前記母配線基板の他面側に前記配線基板となる部分毎に外部接続端子を配置する工程を含むことを特徴とする請求項1〜8の何れか一項に記載の半導体装置の製造方法。
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014183278A (ja) * | 2013-03-21 | 2014-09-29 | Toshiba Corp | 半導体装置及びその製造方法 |
CN104916551A (zh) * | 2014-03-14 | 2015-09-16 | 株式会社东芝 | 半导体装置的制造方法及半导体装置 |
KR20160100923A (ko) * | 2013-12-23 | 2016-08-24 | 인텔 코포레이션 | 쓰루 바디 비아 격리된 동축 커패시터 및 그 형성 기술 |
US9595507B2 (en) | 2015-03-11 | 2017-03-14 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
US9601465B2 (en) | 2013-10-16 | 2017-03-21 | Samsung Electronics Co., Ltd. | Chip-stacked semiconductor package and method of manufacturing the same |
KR20170098586A (ko) * | 2016-02-22 | 2017-08-30 | 삼성전자주식회사 | 반도체 패키지 |
US9905550B2 (en) | 2014-07-11 | 2018-02-27 | Samsung Electronics Co., Ltd. | Semiconductor package and method of fabricating the same |
-
2011
- 2011-01-13 JP JP2011004758A patent/JP2012146853A/ja not_active Withdrawn
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014183278A (ja) * | 2013-03-21 | 2014-09-29 | Toshiba Corp | 半導体装置及びその製造方法 |
US9601465B2 (en) | 2013-10-16 | 2017-03-21 | Samsung Electronics Co., Ltd. | Chip-stacked semiconductor package and method of manufacturing the same |
US9905538B2 (en) | 2013-10-16 | 2018-02-27 | Samsung Electronics Co., Ltd. | Chip-stacked semiconductor package and method of manufacturing the same |
KR20160100923A (ko) * | 2013-12-23 | 2016-08-24 | 인텔 코포레이션 | 쓰루 바디 비아 격리된 동축 커패시터 및 그 형성 기술 |
KR102230011B1 (ko) * | 2013-12-23 | 2021-03-19 | 인텔 코포레이션 | 쓰루 바디 비아 격리된 동축 커패시터 및 그 형성 기술 |
CN104916551A (zh) * | 2014-03-14 | 2015-09-16 | 株式会社东芝 | 半导体装置的制造方法及半导体装置 |
US9905550B2 (en) | 2014-07-11 | 2018-02-27 | Samsung Electronics Co., Ltd. | Semiconductor package and method of fabricating the same |
US9595507B2 (en) | 2015-03-11 | 2017-03-14 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
KR20170098586A (ko) * | 2016-02-22 | 2017-08-30 | 삼성전자주식회사 | 반도체 패키지 |
KR102579876B1 (ko) | 2016-02-22 | 2023-09-18 | 삼성전자주식회사 | 반도체 패키지 |
US11894346B2 (en) | 2016-02-22 | 2024-02-06 | Samsung Electronics Co., Ltd. | Semiconductor package having a high reliability |
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