JP2012212786A - 半導体装置の製造方法 - Google Patents
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Abstract
【解決手段】複数の半導体チップ11a〜11bの互いの接続端子12a,12bを熱圧着により接合しながら、これら複数の半導体チップ11a〜11eを積層したチップ積層体3Aを作製する工程と、複数の半導体チップ11a〜11eの各隙間にアンダーフィル材4を充填した後、このアンダーフィル材4を熱硬化させることで、チップ積層体3Aをアンダーフィル材4で封止する工程とを含み、チップ積層体3Aを作製する工程と、チップ積層体3Aをアンダーフィル材4で封止する工程との間で、チップ積層体3Aの温度を所定以上に保持する。
【選択図】図1
Description
なお、以下の説明で用いる図面は、特徴をわかりやすくするために、便宜上特徴となる部分を拡大して示している場合があり、各構成要素の寸法比率などが実際と同じであるとは限らない。また、以下の説明において例示される材料、寸法等は一例であって、本発明はそれらに必ずしも限定されるものではなく、その要旨を変更しない範囲で適宜変更して実施することが可能である。
(半導体装置)
先ず、第1の実施形態として図1に示すCoC型の半導体パッケージ1Aについて説明する。
この半導体パッケージ1Aは、図1に示すように、配線基板2と、この配線基板2の一面(上面)に実装されたチップ積層体3Aと、このチップ積層体3Aを覆うアンダーフィル材(第1の封止体)4と、このアンダーフィル材4を覆うモールド樹脂(第2の封止体)5と、配線基板2の他面(下面)に配置された複数のはんだボール(外部接続端子)6とを備えることによって、BGA(Ball Grid Array)と呼ばれるパッケージ構造を有している。
次に、上記図1に示す半導体パッケージ1Aの製造工程について説明する。
上記半導体パッケージ1Aを製造する際は、先ず、図2A〜図2Cに示すように、上記複数の半導体チップ11a〜11eを積層したチップ積層体3Aを作製する。
(半導体装置)
次に、第2の実施形態として図11に示すCoC型の半導体パッケージ1Bについて説明する。なお、以下の説明では、上記図1に示す半導体パッケージ1Aと同等の部位については、図面において同じ符号を付すものとする。
上記半導体パッケージ1Bを製造する際は、先ず、図12A〜図12Cに示すように、上記複数のメモリーチップ11a〜11eを積層したチップ積層体3Bを作製する。
例えば、図23A〜図23Dに示すように、更なる製造効率の向上を図るため、上記チップ積層体3Aを作製する工程と、上記アンダーフィル材4を充填する工程とを一貫して行える装置構成とし、上記チップ積層体3Aを作製した後、このチップ積層体3Aを加温した状態のまま、アンダーフィル4を充填することも可能である。
Claims (8)
- 複数の半導体チップの互いの接続端子を熱圧着により接合しながら、これら複数の半導体チップを積層したチップ積層体を作製する工程と、
前記複数の半導体チップの各隙間にアンダーフィル材を充填した後、このアンダーフィル材を熱硬化させることで、前記チップ積層体を前記アンダーフィル材で封止する工程とを含み、
前記チップ積層体を作製する工程と、前記チップ積層体を前記アンダーフィル材で封止する工程との間で、前記チップ積層体の温度を所定以上に保持することを特徴とする半導体装置の製造方法。 - 前記チップ積層体を加温しながら、このチップ積層体の温度を少なくとも常温以上に保持することを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記アンダーフィル材が硬化するまでの間、前記チップ積層体を加温することを特徴とする請求項2に記載の半導体装置の製造方法。
- 更に、配線基板となる部分が複数並んで形成された母配線基板の一面に、前記アンダーフィル材で封止されたチップ積層体を前記配線基板となる部分毎に実装する工程と、
前記アンダーフィル材で封止されたチップ積層体の全体を覆うように前記母配線基板の一面側をモールド樹脂で封止する工程と、
前記母配線基板を前記配線基板となる部分毎に切断することによって個々の半導体装置に分割する工程とを含むことを特徴とする請求項1〜3の何れか一項に半導体装置の製造方法。 - 前記チップ積層体を作製する際は、一面側に第1の接続端子と他面側に第2の接続端子とを有する複数の半導体チップを、それぞれの一面と他面とを対向させながら、それぞれの間にある前記第1の接続端子と前記第2の接続端子とを接合して積層することを特徴とする請求項1〜4の何れか一項に記載の半導体装置の製造方法。
- 前記チップ積層体を前記母配線基板に実装する際は、前記配線基板となる部分に第3の接続端子が設けられた母配線基板を用意し、この母配線基板の前記配線基板となる部分毎に、前記チップ積層体の最上層に位置する半導体チップを下方に向けた状態で、この半導体チップの一面と前記配線基板となる部分とを対向させながら、その間にある前記第3の接続端子と前記第1の接続端子とを接合することにより行うことを特徴とする請求項1〜5の何れか一項に記載の半導体装置の製造方法。
- 前記チップ積層体を前記配線基板となる部分毎に実装する際に、前記チップ積層体と前記配線基板となる部分との間に接着部材を設け、この接着部材を介して前記チップ積層体を前記配線基板となる部分に接着固定することを特徴とする請求項1〜6の何れか一項に記載の半導体装置の製造方法。
- 前記母配線基板を切断する前に、この母配線基板の他面側に前記配線基板となる部分毎に外部接続端子を配置する工程を含むことを特徴とする請求項1〜7の何れか一項に記載の半導体装置の製造方法。
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Application Number | Priority Date | Filing Date | Title |
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JP2011077738A JP2012212786A (ja) | 2011-03-31 | 2011-03-31 | 半導体装置の製造方法 |
US13/430,148 US20120252165A1 (en) | 2011-03-31 | 2012-03-26 | Method for manufacturing a semiconductor device |
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JP2011077738A JP2012212786A (ja) | 2011-03-31 | 2011-03-31 | 半導体装置の製造方法 |
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Cited By (2)
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JP2015177007A (ja) * | 2014-03-14 | 2015-10-05 | 株式会社東芝 | 半導体装置の製造方法及び半導体装置 |
JP2016171124A (ja) * | 2015-03-11 | 2016-09-23 | 株式会社東芝 | 半導体装置及びその製造方法 |
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WO2013071399A1 (en) * | 2011-11-14 | 2013-05-23 | Mosaid Technologies Incorporated | Package having stacked memory dies with serially connected buffer dies |
KR102107961B1 (ko) | 2013-11-14 | 2020-05-28 | 삼성전자 주식회사 | 반도체 장치 및 이의 제조 방법 |
US10535633B2 (en) | 2015-07-02 | 2020-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip package having die structures of different heights and method of forming same |
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US10840209B2 (en) * | 2018-12-28 | 2020-11-17 | Micron Technology, Inc. | Methods and systems for manufacturing semiconductor devices |
US10840210B2 (en) * | 2018-12-28 | 2020-11-17 | Micron Technology, Inc. | Methods and systems for manufacturing semiconductor devices |
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EP1030349B2 (de) * | 1999-01-07 | 2013-12-11 | Kulicke & Soffa Die Bonding GmbH | Verfahren und Vorrichtung zum Behandeln von auf einem Substrat angeordneten elektronischen Bauteilen, insbesondere von Halbleiterchips |
US7491582B2 (en) * | 2004-08-31 | 2009-02-17 | Seiko Epson Corporation | Method for manufacturing semiconductor device and semiconductor device |
JP4191167B2 (ja) * | 2005-05-16 | 2008-12-03 | エルピーダメモリ株式会社 | メモリモジュールの製造方法 |
JP4983049B2 (ja) * | 2005-06-24 | 2012-07-25 | セイコーエプソン株式会社 | 半導体装置および電子機器 |
KR100844997B1 (ko) * | 2006-12-29 | 2008-07-09 | 삼성전자주식회사 | 반도체 패키지, 반도체 스택 패키지, 패키지들을 제조하는방법 |
JP2008294367A (ja) * | 2007-05-28 | 2008-12-04 | Nec Electronics Corp | 半導体装置およびその製造方法 |
JP5159273B2 (ja) * | 2007-11-28 | 2013-03-06 | ルネサスエレクトロニクス株式会社 | 電子装置の製造方法 |
JP5388341B2 (ja) * | 2009-03-31 | 2014-01-15 | ナミックス株式会社 | アンダーフィル用液状樹脂組成物、フリップチップ実装体およびその製造方法 |
JP5543125B2 (ja) * | 2009-04-08 | 2014-07-09 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置および半導体装置の製造方法 |
US7871860B1 (en) * | 2009-11-17 | 2011-01-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of semiconductor packaging |
-
2011
- 2011-03-31 JP JP2011077738A patent/JP2012212786A/ja not_active Withdrawn
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2012
- 2012-03-26 US US13/430,148 patent/US20120252165A1/en not_active Abandoned
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015177007A (ja) * | 2014-03-14 | 2015-10-05 | 株式会社東芝 | 半導体装置の製造方法及び半導体装置 |
JP2016171124A (ja) * | 2015-03-11 | 2016-09-23 | 株式会社東芝 | 半導体装置及びその製造方法 |
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