JP2015177007A - 半導体装置の製造方法及び半導体装置 - Google Patents

半導体装置の製造方法及び半導体装置 Download PDF

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JP2015177007A
JP2015177007A JP2014052125A JP2014052125A JP2015177007A JP 2015177007 A JP2015177007 A JP 2015177007A JP 2014052125 A JP2014052125 A JP 2014052125A JP 2014052125 A JP2014052125 A JP 2014052125A JP 2015177007 A JP2015177007 A JP 2015177007A
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semiconductor chip
electrode pad
substrate
adhesive
bonded
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直幸 小牟田
Naoyuki Komuda
直幸 小牟田
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Toshiba Corp
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Toshiba Corp
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Priority to JP2014052125A priority Critical patent/JP2015177007A/ja
Priority to TW103125585A priority patent/TWI555099B/zh
Priority to US14/475,315 priority patent/US9449949B2/en
Priority to CN201410453506.8A priority patent/CN104916552A/zh
Publication of JP2015177007A publication Critical patent/JP2015177007A/ja
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Abstract

【課題】はんだ接合部にクラックが発生することを防止できる半導体装置の製造方法を提供する。
【解決手段】第１電極パッドを有する第１半導体チップに、第１貫通ビア及び当該ビアに接合する第２電極パッドを有する第２半導体チップを、第１−第２電極パッドを位置合わせして搭載する。第２半導体チップに、第２貫通ビア、一方の面に前記ビアに接合する第３電極パッド、他方の面に前記ビアに接合するよう保護膜を介し形成された配線及び前記配線に接合するよう形成された第４電極パッドを有する第３半導体チップを、第２−第３電極パッドを位置合わせして搭載する。第１〜第３電極パッドを接合して第１〜第３半導体チップ間を電気的に接続し、第１〜第３半導体チップを備える積層体の隙間に樹脂を充填する。基板上のはんだバンプと各積層体の第４電極パッドとを位置合わせして接合すると共に複数の積層体を接着材で固着する。最後に、積層体及び基板の一方の面をモールド樹脂で封止してから複数の積層体をパッケージダイシングして個片化する。
【選択図】図１０

Description

本発明の実施形態は、複数の半導体チップを有する積層体を基板に接続した半導体装置の製造方法及び半導体装置に関する。
半導体装置には、複数の半導体チップを積層した積層体を基板に搭載するものがある（チップ・オン・チップ型）。積層体の間に位置する半導体チップには、例えばＴＳＶ（Through Silicon Via）と称されるような貫通ビアが形成されており、その貫通ビアに接合される金属電極が設けられている。そして、各半導体チップの金属電極が接合されることで各チップ間が電気的に接続される。最上層の半導体チップには、電極に繋がる再配線が（ＲＤＬ:Re-Distribution Layer）が保護膜と共に形成されている。
基板上には、複数のはんだバンプが形成され、そのはんだバンプと、隙間にＵＦ（Under Fill）樹脂が充填された積層体の上下を転置させた最上層の再配線の電極とをフリップ・チップ接続し、全体を樹脂モールドすることで半導体装置が完成する。
米国特許出願公開２０１０／０２５８９３３号明細書
ここで、基板の厚さは一般に百数十μｍ以下と薄く、はんだバンプを介して積層体を基板に接続した際に、基板が熱収縮して変形し反りが発生すると、はんだ接合部にクラックが生じて破断するおそれがある。
そこで、はんだ接合部にクラックが発生することを抑制できる半導体装置の製造方法及び半導体装置を提供する。
本実施形態の半導体装置の製造方法によれば、第１電極パッドを有する第１半導体チップに対し、第１貫通ビア及び当該第１貫通ビアに接合する第２電極パッドを有する少なくとも一枚の第２半導体チップを、第１電極パッドと第２電極パッドとを位置合わせして搭載する。次に、第２半導体チップに対し、第２貫通ビア、一方の面に前記第２貫通ビアに接合する第３電極パッド、他方の面に前記第２貫通ビアに接合するように保護膜を介して形成された配線及び前記配線に接合するように形成された第４電極パッドを有する第３半導体チップを、第２電極パッドと第３電極パッドとを位置合わせして搭載する。
それから、第１から第３電極パッドを接合することで、第１半導体チップ，第２半導体チップ及び第３半導体チップ間を電気的に接続し、第１半導体チップ，第２半導体チップ及び第３半導体チップを備える積層体の隙間に樹脂を充填する。そして、一方の面側にはんだバンプが形成されると共に接着材が配置されている基板上に、積層体を複数搭載するため、基板上のはんだバンプと各積層体の第４電極パッドとを位置合わせして接合すると共に、複数の積層体を接着材で固着する。最後に、積層体及び基板の一方の面を、モールド樹脂で封止してから、複数の積層体をパッケージダイシングして個片化する。
第１実施形態であり、積層体を構成する各半導体チップ及び金属基板の分解断面図 第１実施形態であり、中間半導体チップの（ａ）平面図、（ｂ）底面図 第１実施形態であり、最上段半導体チップの（ａ）平面図、（ｂ）底面図 第１実施形態であり、各半導体チップ及び金属基板を積層した状態を示す断面図 第１実施形態であり、各半導体チップの隙間にＵＦ樹脂を充填して積層体を構成した状態を示す断面図 第１実施形態であり、基板上にはんだバンプと共に接着材を搭載した状態を示す平面図 第１実施形態であり、積層体を基板にはんだ付けすると共に、接着材により四隅を固定した状態を示す断面図 第１実施形態であり、基板上の積層体をモールド樹脂により封止した状態を示す断面図 第１実施形態であり、基板の下面側にはんだボールを接合した状態を示す断面図 第１実施形態であり、各半導体デバイスをパッケージダイシングにより個片化した状態を示す断面図 基板上にはんだバンプのみを搭載した状態の（ａ）断面図、（ｂ）平面図 基板上に積層体を搭載した状態の断面図 はんだ接合部にクラックが発生した状態を示す断面図 第２実施形態を示す図６相当図 第２実施形態を示す図７相当図 第３実施形態を示す図６相当図
（第１実施形態）
以下、第１実施形態について図１から図１３を参照して説明する。図１及び図４に示すように、金属基板１の上には、最下段の半導体チップ（例えばシリコンチップ）２が搭載される。例えば数ｍｍ〜十数ｍｍ角程度の矩形状をなす半導体チップ２の上面側には、素子又は回路（例えばメモリセル及びその周辺回路など）が形成されており（図示せず）、その素子又は回路を他のチップに形成されている素子又は回路と電気的に接続するために、金属電極パッド３がチップの中央部分に形成されている。
図１では１枚のみ図示する半導体チップ４は、上記半導体チップ２と、最上段の半導体チップ５との中間に位置するように積層される。半導体チップ４には、半導体チップ２の金属電極パッド３の形成位置に対応するよう、中央部分に貫通ビア６が形成されている。貫通ビア６は、ビアホール６Ｈと、ビアホール６Ｈ内に絶縁膜（図示せず）を介して充填材６Ｍ（例えば銅）を充填して形成されている。半導体チップ４の上面側と下面側とには、貫通ビア６に接合された金属電極パッド７Ｕ，７Ｄがそれぞれ形成されている（図２（ａ），（ｂ）参照）。
最上段の半導体チップ５にも、半導体チップ４と同様にして貫通ビア８が形成されている。そして、半導体チップ５の下面には、貫通ビア８に接合する金属電極パッド９が形成され、上面には、保護膜１０を介して貫通ビア８に接合するように再配線１１（最上層配線）が形成されている。再配線１１には、後述する基板１２と電気的に接続するため、金属電極パッド１３が形成されている（図３（ａ），（ｂ）参照）。ここで、図１等に示している断面は、図３（ａ）のＡ−Ａ’断面である。また、各半導体チップ２，４，５の厚さは、例えば３０μｍ〜５０μｍ程度である。
図４は、金属基板１，最下段の半導体チップ２，２枚の中間半導体チップ４及び最上段の半導体チップ５が互いに接合された状態，つまり積層体１４を示している。最下段の半導体チップ２は、金属基板１に例えばダイ・アタッチ・フィルムのような接着材により接着されている。各半導体チップ２,４,５は、それぞれが有している金属電極パッド３，７，９の位置を合わせるようにして搭載され、各金属電極パッド３，７，９は熱圧着により接合されている。そして、図５に示すように、各半導体チップ２,４,５の隙間にＵＦ樹脂１５が充填される。
図６に示すように、積層体１４を搭載する前の状態の基板１２には、はんだバンプ１６が、半導体チップ５の金属電極パッド１３が形成されている位置に合わせて配置されている。例えば１つの積層体１４に対して１６個のはんだバンプ１６が、それらを配置した外形が矩形状をなすようにして配置領域１７が形成されている。また、基板１２には、複数（この例では２つ）の積層体１４を搭載するため、はんだバンプ１６の形成領域１７も２つ設けられている。
そして、本実施形態では、はんだバンプ１６と共に接着材１８を基板１２に配置しておく。接着材１８は、上述のように、１６個のはんだバンプ１６の配置外形が矩形状をなしている場合、その配置領域１７の四隅に対応するはんだバンプ１６Ａ〜１６Ｄの外側近傍に位置するように、接着材１８Ａ〜１８Ｄをそれぞれ対応させて配置する。換言すれば、接着材１８Ａ〜１８Ｄは、配置領域の対角線の延長線上に係るように配置されている。また、接着材１８Ａ〜１８Ｄは、図７に示すように、積層体１４を基板１２上に搭載した際に、積層体１４側の半導体チップ５の四隅に係るように配置する。
図７の右側は、積層体１４を基板１２に搭載（接合）する直前の状態を示しており、図７の左側は、積層体１４を基板１２に搭載した直後の状態を示している。この時、２つの積層体１４が、上下を転置した状態で、それぞれの半導体チップ５の金属電極パッド１３の位置を、対応するはんだバンプ１６の形成位置と合わせるようにして搭載され、例えば高温状態で荷重を加えて熱圧着し、はんだ付けする。尚、必要に応じて超音波等を用いて加熱しても良い。
そして、接着材１８は、積層体１４を基板１２にはんだ付けする際に加熱され、その後冷却されると固化して積層体１４の四隅を固定する。これにより、基板１２が熱収縮などにより変形しようとした場合でも、積層体１４の四隅が接着材１８により基板１２に固定されていることで変形を防止し、クラックの発生が抑止される。
その後、図８に示すように、基板１２に搭載された積層体１４はモールド樹脂１９により封止される。それから、図９に示すように基板１２の下面側に配置されている電極パッド（図示せず）に合わせてはんだボール２０が接合される。そして、この状態でパッケージダイシングが行われ、図１０に示すように各積層体１４を内包する部分が個片化されて、単体となったＢＧＡ（Ball Grid Array）パッケージの半導体デバイス２１（半導体装置）が完成する。
ここで、本実施形態のように、接着材１８を使用しない場合に発生する問題を、図１１〜図１３を参照して説明する。図１１は図６相当図であり、基板１２にはんだバンプ１６のみを配置している。この状態で、図１２に示すように、基板１２に積層体１４を搭載し、はんだバンプ１６を加熱してはんだ付けすると、接合後の熱収縮により、基板１２が図１３中に矢印で示すように変形する。この変形により、はんだ接合部にクラック２２が生じるおそれがある。本実施形態では、接着材１８により積層体１４の四隅を基板１２に固定しているので、図１３に示すような基板１２の変形、ひいてはクラック２２の発生が抑制される。
以上のように本実施形態によれば、上面に金属電極パッド３を有する半導体チップ２上に、貫通ビア６及び金属電極パッド７を有する半導体チップ４を、互いの電極パッド３，７Ｄを位置合わせして搭載する。次に、半導体チップ４上に、貫通ビア８及び上面に保護膜１０を介して形成された再配線１１並びに金属電極パッド１３を有する半導体チップ５を、互いの電極パッド７Ｕ，９を位置合わせして搭載する。それから、各電極パッド３，７，９を接合することで、半導体チップ２，４，５間を電気的に接続して積層体１４を構成し、積層体１４の隙間にＵＦ樹脂１５を充填する。
一方、基板１２の上面側には、はんだバンプ１６を形成すると共に接着材１８を塗布して配置し、基板１２上に積層体１４を複数搭載するため、基板１２上のはんだバンプ１６と、各積層体１４の半導体チップ５の上面にある金属電極パッド１３とを位置合わせして接合すると共に複数の積層体１４を接着材１８で固着する。それから、積層体１４及び基板１２をモールド樹脂１９で封止すると、複数の積層体１４をパッケージダイシングして個片化して半導体デバイス２１を得た。
すなわち、積層体１４を接着材１８で基板１２に固定したことにより、積層体１４と基板１２とをはんだバンプ１６で接合した際に基板１２が変形することを抑制し、はんだ接合部にクラック２２が発生することを抑制できる。この場合、はんだバンプ１６の複数個による配置外形が矩形の領域１７を成すように基板１２上に形成し、接着材１８Ａ〜１８Ｄを、前記矩形の領域における四隅の外側にそれぞれ配置した。これにより、積層体１４の四隅が接着材１８で基板１２に固定されるので、基板１２の変形を良好に抑制できる。
（第２実施形態）
図１４及び図１５は第２実施形態であり、第１実施形態と同一部分には同一符号を付して説明を省略し、以下異なる部分について説明する。第２実施形態では、図１４に示すように、接着材１８に替えて接着材シート３１を用いている。すなわち、接着材１８Ａ〜１８Ｄに替えて、配置領域１７の四隅に対応するはんだバンプ１６Ａ〜１６Ｄの近傍に位置するように、接着材シート３１Ａ〜３１Ｄをそれぞれ対応させて配置する。また、接着材シート３１Ａ〜３１Ｄは、図７相当図である図１５に示すように、積層体１４側の半導体チップ５の四隅に係るように配置する。その後の工程は、第１実施形態と同様である。
以上のように第２実施形態によれば、第１実施形態の接着材１８に替えて接着材シート３１を用いて積層体１４の四隅を基板１２に固定したので、第１実施形態と同様の効果が得られる。
（第３実施形態）
図１６に示す第３実施形態では、接着材１８を、はんだバンプ１６の矩形配置領域１７について、はんだバンプ１６Ａ，１６Ｂがなす１辺（短辺側）の左側と、はんだバンプ１６Ｃ，１６Ｄがなす１辺の右側とに、直線状を成す接着材１８Ｌ，１８Ｒとして配置されている。そして、これらの接着材１８Ｌ，１８Ｒは、積層体１４側の半導体チップ５の対応する２辺にそれぞれ係るように配置する。
以上のように構成される第３実施形態による場合も、各実施形態と同様の効果が得られる。尚、直線状を成す接着材１８は、はんだバンプ１６Ａ，１６Ｃがなす配置領域１７の１辺（長辺側）の上側と、はんだバンプ１６Ｂ，１６Ｄがなす１辺の下側とに配置しても良い。また、第２実施形態で用いた接着材シート３１を、同様に直線状に配置しても良い。
本発明のいくつかの実施形態を説明したが、これらの実施形態は例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で種々の省略、置き換え、変更を行うことができる。これらの実施形態やその変形は、発明の範囲や要旨に含まれると共に、特許請求の範囲に記載された発明とその均等の範囲に含まれる。
半導体チップは、シリコン以外の材料でも良い。
中間半導体チップ４の積層枚数は３枚に限ることなく、個別の設計に応じて適宜変更すれば良い。また、１枚のみでも良い。
金属基板１は、必要に応じて用いれば良い。
基板の変形を防止できれば、接着材の配置状態は適宜変更して良い。
図面中、２は半導体チップ（第１半導体チップ）、３は金属電極パッド、４は半導体チップ（第２半導体チップ）、５は半導体チップ（第３半導体チップ）、６は貫通ビア、７は金属電極パッド、８は貫通ビア、９は金属電極パッド、１１は再配線、１３は金属電極パッド、１４は積層体、１５はＵＦ樹脂、１６ははんだバンプ、１７は配置領域、１８は接着材、１９はモールド樹脂、２１は半導体デバイス（半導体装置）、３１は接着材シートを示す。

Claims (5)

  1. 第１電極パッドを有する第１半導体チップに対し、第１貫通ビア及び当該第１貫通ビアに接合する第２電極パッドを有する少なくとも一枚の第２半導体チップを、第１電極パッドと第２電極パッドとを位置合わせして搭載し、
    前記第２半導体チップに対し、第２貫通ビア、一方の面に前記第２貫通ビアに接合する第３電極パッド、他方の面に前記第２貫通ビアに接合するように保護膜を介して形成された配線及び前記配線に接合するように形成された第４電極パッドを有する第３半導体チップを、前記第２電極パッドと第３電極パッドとを位置合わせして搭載し、
    前記第１から第３電極パッドを接合することで、前記第１半導体チップ，前記第２半導体チップ及び前記第３半導体チップ間を電気的に接続し、
    前記第１半導体チップ，前記第２半導体チップ及び前記第３半導体チップを備える積層体の隙間に樹脂を充填し、
    一方の面側にはんだバンプが形成されると共に接着材が配置されている基板上に、前記積層体を複数搭載するため、前記基板上のはんだバンプと、各積層体の第４電極パッドとを位置合わせして接合すると共に、前記複数の積層体を前記接着材で固着し、
    前記積層体及び前記基板の一方の面を、モールド樹脂で封止し、
    前記複数の積層体をパッケージダイシングして個片化することを特徴とする半導体装置の製造方法。
  2. 前記はんだバンプは、複数個による配置外形が矩形の領域を成すように前記基板上に形成されており、
    前記接着材は、前記矩形の領域における四隅の外側にそれぞれ配置されていることを特徴とする請求項１記載の半導体装置の製造方法。
  3. 前記はんだバンプは、複数個による配置外形が矩形の領域を成すように前記基板上に形成されており、
    前記接着材は、前記矩形の領域における対向する二辺の外側に直線を成すようにそれぞれ配置されていることを特徴とする請求項１記載の半導体装置の製造方法。
  4. 前記接着材に、接着材シートを用いることを特徴とする請求項１から３の何れか一項に記載の半導体装置の製造方法。
  5. 第１電極パッドを有する第１半導体チップと、
    第１貫通ビア及び当該第１貫通ビアに接合する第２電極パッドを有し、第１電極パッドと第２電極パッドとが位置合わせして搭載されている少なくとも一枚の第２半導体チップと、
    前記第２半導体チップに対し、第２貫通ビア、一方の面に前記第２貫通ビアに接合する第３電極パッド、他方の面に前記第２貫通ビアに接合するように保護膜を介して形成された配線及び前記配線に接合するように形成された第４電極パッドを有し、前記第２電極パッドと第３電極パッドとが位置合わせして搭載されている第３半導体チップと、
    前記第１半導体チップ，前記第２半導体チップ及び前記第３半導体チップ間は、前記第１から第３電極パッドが接合されて電気的に接続されており、
    一方の面側にはんだバンプが形成されると共に接着材が配置されて、前記第１半導体チップ，前記第２半導体チップ及び前記第３半導体チップの隙間に樹脂が充填されてなる積層体が、前記はんだバンプと前記第４電極パッドとが位置合わせして接合されると共に前記接着材で固着されている基板と、
    前記積層体及び前記基板の一方の面が、モールド樹脂で封止されていることを特徴とする半導体装置。
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