JP6753743B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP6753743B2 JP6753743B2 JP2016176671A JP2016176671A JP6753743B2 JP 6753743 B2 JP6753743 B2 JP 6753743B2 JP 2016176671 A JP2016176671 A JP 2016176671A JP 2016176671 A JP2016176671 A JP 2016176671A JP 6753743 B2 JP6753743 B2 JP 6753743B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 32
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- 239000002184 metal Substances 0.000 claims description 38
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- 239000010949 copper Substances 0.000 claims 3
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Description
を多段に積層して樹脂封止する方法が提案されている。各半導体チップは信号取り出しの
伝達速度をより高速化するためにTSV(Through Silicon VIA)方
式による積層方式が注目されている。
た半導体装置の製造方法を提供することである。
以下、第1の実施形態に係る半導体装置について図1乃至図7を参照して説明する。な
お、以下の図面の記載において、同一の部分には同一の符号で表している。ただし、図面
は厚さと平面寸法との関係、比率等は現実のものとは異なり、模式的なものである。
に本実施形態に係る半導体装置は支持基板1、半導体チップ2、貫通電極3、半導体チッ
プ4(ロジックLSI)及び金属バンプ5を含むチップ積層体と、配線基板6、樹脂モー
ルド7を備える。
プ積層体がフリップチップ接続され、半導体チップ2間を含む配線基板6上のチップ積層
体が樹脂でモールドされる。
1bとを有する。支持基板1の第1面1aには、接着剤11を介して半導体チップ2−1
が接着されている。
等が用いられる。接着剤11は例えばダイアタッチフィルムを含む。
属バンプ5は半導体チップ2−2に形成された貫通電極3に電気的に接続されている。ま
た、同様に半導体チップ2−2の貫通電極3は金属バンプ5を介して半導体チップ2−3
に形成された貫通電極3に電気的に接続されている。半導体チップ2−3の配線基板6側
の面には図示しない再配線が形成されている。半導体チップ2−3の貫通電極3は金属バ
ンプ5を介して半導体チップ4と電気的に接続されている。支持基板1、半導体チップ2
及び半導体チップ4を合わせてチップ積層体とする。
チップ2、4はシリコン基板、SiCやGaNなどの基板等を用いることができるが特に
限定されない。
Via:TSV)3は、半導体チップ2−1、2−2に電位や信号を伝える。
通電極3によってチップ積層方向に形成される共通のデータバスに対して、複数の半導体
チップ2のデータ入出力線が並列接続している。
を用いる。または、金属バンプに代えてAu、Ni、Cu、Al、Pd、またはその合金
を含む電極パッドを用いても良い。
は特に限定されない。また、金属バンプ5の数も特に限定されない。
、コア層とビルドアップ層とを有する。配線基板6上には、配線基板6に対して半導体チ
ップ4が最も近く、支持基板1が最も遠くなるようにチップ積層体が搭載されている。
1面6aの反対面である第2面6bを有している。配線基板6の第2面6bには外部接続
端子9が形成されている。半導体装置をBGAパッケージとして使用する場合、外部接続
端子9にはんだボール、はんだメッキ、Auメッキ等を有する突起端子を用いる。半導体
装置をLGAパッケージとして使用する場合には、外部接続端子9に金属ランドを用いる
。
ばはんだバンプ8等を介して半導体チップ4を除いたチップ積層体の最下段の半導体チッ
プ2−3の第1面6a側の面に設けられた電極パッド2−3aに接続される。内部接続端
子10はチップ積層体との接続時に接続部(接続パッド)として機能するものであり、配
線基板6の配線網を介して外部接続端子9と電気的に接続されている。
8は全体が樹脂モールド7で覆われ封止されている。
ップ積層体との間に接着剤13を設けても良い。これにより、半導体チップ2間、及び配
線基板6とチップ積層体との接続が強固になり、ズレを低減できる。
る。
5が形成された面(第1面)とは反対側の面に接着剤11を設け、支持基板1の第1面1
aに接着させる。
有する半導体チップ2−2を半導体チップ2−1上に積層する。貫通電極3の形成は、例
えばBSV(Back Side VIA)方式のウエハプロセスによって行なわれる。
なお、BSV方式とは、基板表面に半導体素子と配線を有するLSI及び表電極を形成し
、基板裏面から配線に向かってホールを形成し、ホールに金属を埋め込むことでTSVを
形成する方法である。
れた金属バンプ5と、支持基板1に対して略垂直なZ軸に上下に重なるように積層される
。同様にして貫通電極3を有する半導体チップ2−3を半導体チップ2−2上に積層する
(図4(a))。半導体チップ2−3には例えば半導体チップ2−2と反対側の面に再配
線(図示しない)と電極パッド2−3aを有する。なお、半導体チップ2の積層において
、半導体チップ2−1にあらかじめ金属バンプ5を形成せず、半導体チップ2−2及び2
−3の支持基板1側の面にあらかじめ金属バンプ5を形成し、上述のように積層させる方
法を用いても良い。
ップ2−3上に積層する。この時、例えば金属バンプ5が半導体チップ2−3の貫通電極
3上に位置するように搭載される。なお、半導体チップ2−3の配線基板6と対向する面
には再配線が形成されていても良い。その場合、再配線上に金属バンプ5が搭載される。
このようにしてチップ積層体が完成する。
属バンプ5の溶融温度未満でおこない、それにより半導体チップ間を機械的に接続しない
ようにしている。これにより半導体チップを積層するときに、金属バンプ5の溶融や凝固
を繰り返すことにより金属バンプ5が脆くなり、半導体チップ2の接続部が破断する虞を
低減できる。
ため、製造工程内で半導体チップ2の上下に重なる金属バンプ5同士の位置ズレが生じる
虞がある。したがって、位置ズレを防ぐために、全ての半導体チップを積層しチップ積層
体を形成後、樹脂封止を行う前にチップ積層体の還元リフローを行うことが望ましい。ま
たは、図2に示したようにあらかじめ半導体チップ2の表面に接着剤(接着性を有する樹
脂)12を形成しておき、接着剤12を用いて半導体チップの間を固定させる方法を用い
てもよい。
はんだバンプ8を形成し、上述のように製造されたチップ積層体を第1面6aにフリップ
チップ実装する。この際、半導体チップ2−3に形成された電極パッド2−3aと配線基
板6上のはんだバンプ8が配線基板6と重なるようにする。また、フリップチップ実装す
るときの温度は、配線基板6に形成されたはんだバンプ8の溶融温度未満でおこなっても
良い。
おき、図2に示すようにチップ積層体と配線基板6とを固定させる方法を用いてもよい。
金属バンプ5及び配線基板6のはんだバンプ8を溶融させる。これにより半導体チップ2
の間及びチップ積層体と配線基板6を電気的に接続させる。
含めた配線基板6上をトランスファーモールドによって樹脂モールド7で一括封止する。
体装置の断片化(シンギュレーション)を行う(図示しない)。
フィル剤等で一度チップ間に樹脂を充填することなく、トランスファーモールドにより一
括で全体を樹脂封止することが可能になる。そのため工程数が削減できる。
に晒すことによって一度に金属バンプと貫通電極を接続させるため、金属バンプの溶融及
び凝固を繰り返すことにより金属バンプが脆くなり、半導体チップの接続部が破断する虞
を低減できる。
次に、第2の実施形態について、図8及び図9を参照しながら説明する。
。なお、それ以外は第1の実施形態と同様である。
、本実施形態の半導体装置は第1の実施形態と比較して支持基板を用いない。つまり、配
線基板上のチップ積層体の最上段は半導体チップ2−1となる。なお、その他の構成は第
1の実施形態と同様であるためその説明は省略する。
があらかじめ形成された半導体チップ2−1上に、貫通電極3及び金属バンプ5があらか
じめ形成された半導体チップ2−2を積層する。この時、半導体チップ2−1に対して略
垂直なZ軸方向において、半導体チップ2−1の金属バンプ5と半導体チップ2−2の貫
通電極3との位置が重なるように積層させる。その後の工程は第1の実施形態と同様なた
め説明を省略する。なお、図9(b)に示すように、半導体チップ2及び4間、及びチッ
プ積層体と配線基板6との間に接着剤12、13を用いても良い。
らには第1の実施形態と比較して支持基板を用いずにチップ積層体を形成することが可能
なため、工程数及び費用が削減される。
異なる。なお、それ以外は第2の実施形態と同様である。
ンプが形成された半導体チップ2−1を接着させる。テープ材料100はたとえば、片面
に接着性を有するものであればその形状や材質は問わない。その後、第2の実施形態と同
様にチップ積層体を形成する。チップ積層体の金属バンプを還元雰囲気等によって電気的
に接続させた後に、テープ材料100をチップ積層体から剥離させる。テープ材料100
の剥離は、例えばピックアップツールA及び吸着ツールB等を用いる。
剥離方法を示している。ピックアップツールAにより、チップ積層体を突き上げると同時
に吸着ツールBによりチップ積層体の半導体チップ4を吸着させることで、テープ材料1
00をチップ積層体から剥離させることが可能になる。なお、この時吸着させる半導体チ
ップは半導体チップ2でも良い。その後の製造方法は第2の実施形態に示したとおりであ
る。
様の効果を有し、さらには第1の実施形態と比較してテープ材料を後に剥離させるため、
半導体装置の面積を削減することが可能になる。
のであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その
他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の
省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や
要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる
1a、6a 第1面
1b、6b 第2面
2 半導体チップ
3 貫通電極
4 半導体チップ(ロジックLSI)
5 金属バンプ
6 配線基板
7 樹脂モールド
8 はんだバンプ
9 外部接続端子
10 内部接続端子
11、12、13 接着剤
61 絶縁層
62 配線層
100 テープ材料
Claims (9)
- 第1バンプ電極を有する第1半導体チップの第1面上に第2バンプ電極及び第1貫通電極を有する第2半導体チップを、前記第1バンプ電極と前記第1貫通電極とが重なるように積層させ、
前記第2半導体チップ上に第2貫通電極を有する第3半導体チップを、前記第2バンプ電極と前記第2貫通電極とが重なるように積層させ、前記第3半導体チップ上に第4半導体チップを積層させてチップ積層体を形成し、
前記チップ積層体の前記第1及び第2バンプ電極をリフローによって前記第1及び第2貫通電極に機械的に接続し、
第2面を有する第1基板上に前記第1面が前記第2面側に向くように、第1樹脂と第3バンプ電極とを介して前記第1基板と前記リフロー後のチップ積層体とをフリップチップ実装により接続して、前記チップ積層体の積層方向と交差する方向において前記第1樹脂が前記第4半導体チップと前記第3バンプ電極との間に配置され、
前記第2面と前記第4半導体チップとの間及び前記第1、第2及び第3半導体チップ間を前記第1樹脂とは異なる第2樹脂で封止する、
半導体装置の製造方法。 - 第1半導体チップの第1面上に、第1バンプ電極及び第1貫通電極を有する第2半導体チップを前記第1バンプ電極が前記第1面に接するように積層させ、
前記第2半導体チップ上に、第2バンプ電極及び第2貫通電極を有する第3半導体チップを前記第2バンプ電極と前記第1貫通電極とが重なるように積層させ、前記第3半導体チップ上に第4半導体チップを積層させてチップ積層体を形成し、
前記チップ積層体の前記第1及び第2バンプ電極をリフローによって前記第1及び第2貫通電極に機械的に接続し、
第2面を有する第1基板上に前記第1面が前記第2面側に向くように、第1樹脂と第3バンプ電極とを介して前記第1基板と前記リフロー後のチップ積層体とをフリップチップ実装により接続して、前記チップ積層体の積層方向と交差する方向において前記第1樹脂が前記第4半導体チップと前記第3バンプ電極との間に配置され、
前記第2面と前記第4半導体チップとの間及び前記第1、第2及び第3半導体チップ間を前記第1樹脂とは異なる第2樹脂で樹脂封止する、
半導体装置の製造方法。 - 前記第1半導体チップの前記第1面と反対面に第3樹脂を介して第2基板を設けることを特徴とする請求項1または2に記載の半導体装置の製造方法。
- テープ材料に前記第1半導体チップの前記第1面と反対面を接着させることを特徴とする請求項1または2に記載の半導体装置の製造方法。
- 前記リフローは、還元雰囲気中で行うことを特徴とする請求項1乃至4のいずれか1項に記載の半導体装置の製造方法。
- 前記第2樹脂はトランスファーモールドによって行うことを特徴とする請求項1乃至5のいずれか1項に記載の半導体装置の製造方法。
- 前記第1及び第2バンプ電極はAu、Ni、Cu、Sn、Bi、Zn、In、及びその合金のいずれかを含む金属バンプ、またはAu、Ni、Cu、Al、Pd、及びその合金のいずれかを含む電極パッドであることを特徴とする請求項1乃至6のいずれか1項に記載の半導体装置の製造方法。
- 前記チップ積層体を形成後、
ピックアップツール及び吸着ツールを用いて前記テープ材料を剥離することを特徴とする請求項4に記載の半導体装置の製造方法。 - 前記第1、第2及び第3半導体チップ間に更に接着樹脂を有することを特徴とする請求項1乃至8のいずれか1項に記載の半導体装置の製造方法。
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