JP6495692B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP6495692B2 JP6495692B2 JP2015048491A JP2015048491A JP6495692B2 JP 6495692 B2 JP6495692 B2 JP 6495692B2 JP 2015048491 A JP2015048491 A JP 2015048491A JP 2015048491 A JP2015048491 A JP 2015048491A JP 6495692 B2 JP6495692 B2 JP 6495692B2
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Classifications
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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Description
第1実施形態の半導体装置では、チップ積層体の支持体としてシリコン基板を用いることで、半導体チップの反りを抑制する。
図1を用いて、第1実施形態に係る半導体装置1の構造について説明する。
図2乃至図10を用いて、第1実施形態に係る半導体装置1の製造方法について説明する。
上記第1実施形態によれば、チップ積層体20の支持体としてシリコン基板30を用いている。このようなシリコン基板30は、シリコン基板を用いて形成された半導体チップ11a〜11h及びIFチップ18を有するチップ積層体20と同じ熱膨張係数である。また、シリコンは、剛性が高く、切断及び研削が容易である。このため、支持体としてシリコン基板30を用いることで、半導体チップ11a〜11hの反りを抑制することができ、半導体装置1の信頼性を向上させることができる。さらに、シリコン基板30は研削及びダイシングし易いため、パッケージの小型化及び薄化を実現し易い。
第1実施形態では、チップ積層体20の支持体の基板30の厚みT2が一定であった。これに対し、第2実施形態は、基板30の厚みT2が中央部と端部で異なっている。第2実施形態では、図11及び図12を用いて、第1実施形態と異なる点について説明する。
第3実施形態の半導体装置1は、基板30のカット部31の変形例である。第3実施形態では、図13乃至図16を用いて、第1実施形態と異なる点について説明する。
第4実施形態の半導体装置1は、カット部31内の樹脂に関する変形例である。第4実施形態では、図17及び図18を用いて、第1実施形態と異なる点について説明する。
第5実施形態では、図19乃至図21を用いて、各実施形態における基板30の平面図について説明する。
第6実施形態の半導体装置1は、基板30の幅W2に関する変形例である。第6実施形態では、図22及び図23を用いて、第1実施形態と異なる点について説明する。
第7実施形態では、図24乃至図28を用いて、第1の実施形態と異なる半導体装置1の製造方法について説明する。ここでは、第1実施形態と異なる点について説明する。
第8実施形態の半導体装置1は、研削前における基板30の形状に関する変形例である。第8実施形態では、図29を用いて、第1実施形態と異なる点について説明する。
第9実施形態の半導体装置1は、各半導体チップ11a〜11hとしてDRAMを用いた場合である。第9実施形態では、図30を用いて、第1実施形態と異なる点について説明する。
第10実施形態は、チップ積層体20の支持体となる基板70として、半導体チップを用いた例である。ここでは、第1実施形態と異なる点について説明する。
図31を用いて、第10実施形態に係る半導体装置1の構造について説明する。
図32乃至図37を用いて、第10実施形態に係る半導体装置1の製造方法について説明する。
Claims (4)
- 複数の半導体チップを含み、前記複数の半導体チップの少なくとも一部は前記半導体チップを貫通する電極を有し、前記複数の半導体チップは積層されかつ前記電極を介して互いに接続され、第1幅を有する積層体と、
前記積層体の第1面上に設けられ、前記第1幅より大きい第2幅を有し、1つの前記半導体チップの厚さ以上の厚さを有し、前記積層体の前記第1面と対向する第3面、及び前記第3面と反対側に位置する第4面を有する第1基板と、前記第1基板の周囲に間隙を有するように設けられ、前記第1基板と直接接触せず、前記第1基板と同一の厚みを持つ第2基板とを有するシリコン基板と、
前記積層体の第2面上に設けられ、前記第2幅と等しい第3幅を有する配線層と、
前記積層体の周囲及び前記間隙内に設けられた樹脂と
を具備する半導体装置。 - 前記間隙内の前記樹脂は、前記シリコン基板の前記第4面から露出している、請求項1記載の半導体装置。
- 前記配線層と前記積層体の前記第2面との間に設けられ、前記積層体に電気的に接続され、前記第1幅より小さい第4幅を有する第1チップをさらに具備する請求項1または2記載の半導体装置。
- シリコン基板にカット部を形成する第1工程と、
前記第1工程の後、前記シリコン基板上に、半導体チップを貫通する電極を有する複数の半導体チップを積層し、前記複数の半導体チップが前記電極を介して互いに接続された積層体を形成する第2工程と、
前記第2工程の後、前記積層体に配線層を接続する第3工程と、
前記第3工程の後、前記シリコン基板上及び前記積層体の周囲に樹脂を形成する第4工程と、
前記第4工程の後、前記シリコン基板を研削し、前記シリコン基板の厚みを薄くすることにより、前記カット部を研削し、前記シリコン基板の前記カット部よりも外側の部分を分離する第5工程と
を具備し、
前記カット部は、前記積層体の形成された領域よりも外側に位置し、
前記積層体は第1幅を有し、前記シリコン基板は、前記第1幅より大きい第2幅を有すると共に、1つの前記半導体チップの厚さ以上の厚さを有し、前記配線層は前記第2幅と等しい第3幅を有する、半導体装置の製造方法。
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