TWI612589B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TWI612589B
TWI612589B TW104127000A TW104127000A TWI612589B TW I612589 B TWI612589 B TW I612589B TW 104127000 A TW104127000 A TW 104127000A TW 104127000 A TW104127000 A TW 104127000A TW I612589 B TWI612589 B TW I612589B
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Taiwan
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laminate
width
silicon substrate
semiconductor device
semiconductor
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TW104127000A
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English (en)
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TW201633412A (zh
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栗田洋一郎
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東芝記憶體股份有限公司
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Publication of TW201633412A publication Critical patent/TW201633412A/zh
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Abstract

實施形態的半導體裝置係具有：層疊體(20)，其係包含複數的半導體晶片(11a~11h)，複數的半導體晶片的至少一部分係具有貫通半導體晶片的電極(12)，複數的半導體晶片係被層疊且經由電極來互相連接，具有第1寬度(W1)；矽基板(30)，其係設於層疊體的第1面上，具有比第1寬度大的第2寬度(W2)；配線層(50)，其係設於層疊體的第2面上；及樹脂(42、45)，其係設於層疊體的周圍。

Description

半導體裝置及其製造方法
本申請案是以2015年3月11日申請之日本專利申請案號2015-048491作為優先權的基礎，求取求其利益，引用其內容全體。
本實施形態是關於具有層疊複數的半導體晶片的晶片層疊體之半導體裝置及其製造方法。
為了實現半導體裝置的小型化、高密度化，而提案一種在配線基板上層疊複數的半導體晶片予以封裝化者。
但，若使半導體晶片薄化，則半導體晶片的剛性會降低，容易產生半導體晶片的彎曲。其結果，發生半導體晶片間的連接不良，半導體裝置的可靠度降低。此半導體晶片的彎曲是在層疊半導體晶片時更增加。而且，半導體晶片的彎曲是在藉由垂直貫通半導體晶片的內部的貫通電極(TSV：Through Silicon Via)來連接半導體晶片間的構造中明顯產生。
實施形態是在於提供一種可抑制晶片的彎曲之半導體裝置及其製造方法。
實施形態係提供一種半導體裝置，其係具備：層疊體，其係包含複數的半導體晶片，前述複數的半導體晶片的至少一部分係具有貫通前述半導體晶片的電極，前述複數的半導體晶片係被層疊且經由前述電極來互相連接，具有第1寬度；矽基板，其係設於前述層疊體的第1面上，具有比前述第1寬度大的第2寬度；配線層，其係設於前述層疊體的第2面上；及樹脂，其係設於前述層疊體的周圍。
又，實施形態係提供一種半導體裝置，其係具備：層疊體，其係包含複數的半導體晶片，前述複數的半導體晶片係具有貫通前述半導體晶片的電極，前述複數的半導體晶片係被層疊且經由前述電極來互相連接，具有第1寬度；矽基板，其係設於前述層疊體的第1面上，具有前述第1寬度，構成半導體晶片；配線層，其係設於前述層疊體的第2面上；及樹脂，其係設於前述層疊體的周圍，前述矽基板係具有大於等於前述層疊體的1個的半導體晶片的厚度之厚度。
又，實施形態係提供一種半導體裝置的製造方法，其係具備：在矽基板上層疊具有貫通半導體晶片的電極之複數的半導體晶片，形成前述複數的半導體晶片經由前述電極來互相連接的層疊體之工程；將配線層連接至前述層疊體之工程；在前述矽基板上及前述層疊體的周圍形成樹脂之工程；及切削前述矽基板，將前述矽基板的厚度弄薄之工程。
1‧‧‧半導體裝置
10‧‧‧記憶晶片層疊體
11a~11h‧‧‧半導體晶片
12‧‧‧貫通電極
13‧‧‧凸塊電極
14‧‧‧黏著劑
15‧‧‧配線
16‧‧‧絕緣膜
17‧‧‧電極焊墊
18‧‧‧介面晶片(IF晶片)
20‧‧‧晶片層疊體
30‧‧‧基板
31‧‧‧切斷部
41‧‧‧黏著劑
42‧‧‧樹脂
43、44‧‧‧內部連接端子
45‧‧‧樹脂
46‧‧‧外部連接端子
50‧‧‧配線層
60‧‧‧晶片載體
61‧‧‧階差部
62‧‧‧開口部
70‧‧‧基板
圖1是第1實施形態的半導體裝置的剖面圖。
圖2是第1實施形態的半導體裝置的製造方法的流程圖。
圖3是表示第1實施形態的半導體裝置的製造工程的圖。
圖4是接續於圖3，表示第1實施形態的半導體裝置的製造工程的圖。
圖5是沿著圖4的V-V線的基板及載體的剖面圖。
圖6是接續於圖5，表示第1實施形態的半導體裝置的製造工程的剖面圖。
圖7是接續於圖6，表示第1實施形態的半導體裝置的製造工程的剖面圖。
圖8是接續於圖7，表示第1實施形態的半導體裝置 的製造工程的剖面圖。
圖9是接續於圖8，表示第1實施形態的半導體裝置的製造工程的剖面圖。
圖10是接續於圖9，表示第1實施形態的半導體裝置的製造工程的剖面圖。
圖11是第2實施形態的半導體裝置的剖面圖。
圖12是第2實施形態的半導體裝置的剖面圖。
圖13是第3實施形態的半導體裝置的剖面圖。
圖14是第3實施形態的半導體裝置的剖面圖。
圖15是第3實施形態的半導體裝置的剖面圖。
圖16是第3實施形態的半導體裝置的剖面圖。
圖17是表示第4實施形態的半導體裝置的製造工程的剖面圖。
圖18是表示第4實施形態的半導體裝置的剖面圖。
圖19是表示第5實施形態的半導體裝置的基板的平面圖。
圖20是表示第5實施形態的半導體裝置的基板的平面圖。
圖21是表示第5實施形態的半導體裝置的基板的平面圖。
圖22是表示第6實施形態的半導體裝置的基板的剖面圖。
圖23是表示圖22的半導體裝置的基板的平面圖。
圖24是第7實施形態的半導體裝置的製造方法的流 程圖。
圖25是表示第7實施形態的半導體裝置的製造工程的圖。
圖26是表示第7實施形態的半導體裝置的製造工程的圖。
圖27是表示第7實施形態的半導體裝置的製造工程的剖面圖。
圖28是接續於圖27，表示第7實施形態的半導體裝置的製造工程的剖面圖。
圖29是表示第8實施形態的半導體裝置的製造工程的剖面圖。
圖30是表示第9實施形態的半導體裝置的剖面圖。
圖31是表示第10實施形態的半導體裝置的剖面圖。
圖32是表示第10實施形態的半導體裝置的製造工程的剖面圖。
圖33是接續於圖32，表示第10實施形態的半導體裝置的製造工程的剖面圖。
圖34是接續於圖33，表示第10實施形態的半導體裝置的製造工程的剖面圖。
圖35是接續於圖34，表示第10實施形態的半導體裝置的製造工程的剖面圖。
圖36是接續於圖35，表示第10實施形態的半導體裝置的製造工程的剖面圖。
圖37是接續於圖36，表示第10實施形態的半導體 裝置的製造工程的剖面圖。
圖38是表示第10實施形態的半導體裝置的變形例的剖面圖。
圖39是表示第10實施形態的半導體裝置的變形例的剖面圖。
以下，參照圖面說明有關實施形態。另外，在以下的說明中，有關具有同一機能及構成的要素是附上共通的參照符號。
[1]第1實施形態
第1實施形態的半導體裝置是藉由使用矽基板作為晶片層疊體的支撐體，抑制半導體晶片的彎曲。
[1-1]構造
利用圖1來說明有關第1實施形態的半導體裝置1的構造。
如圖1所示般，第1實施形態的半導體裝置1是具備晶片層疊體20、基板30、配線層50、樹脂42及45。晶片層疊體20是包含記憶晶片層疊體10及介面晶片(IF晶片)18。
記憶晶片層疊體10是層疊複數的半導體晶片11a~11h而形成。各半導體晶片11b~11h是具有垂直貫通半 導體晶片11b~11h的內部之例如由矽(Si)所構成的貫通電極(TSV)12。在本圖中，位於記憶晶片層疊體10的基板30側的最下段之半導體晶片11a是不具貫通電極12，但亦可具有貫通電極12。複數的半導體晶片11a~11h是藉由貫通電極12及凸塊電極13來彼此連接。在未形成有複數的半導體晶片11a~11h間的貫通電極12及凸塊電極13之領域是設有黏著劑14，藉由此黏著劑14來黏著固定複數的半導體晶片11a~11h。各半導體晶片11a~11h是例如具有NAND型快閃記憶體的記憶晶片。
IF晶片18是具備用以在構成記憶晶片層疊體10的複數的半導體晶片11a~11h與外部裝置(未圖示)之間進行資料通訊的介面電路(IF電路)。IF晶片18是經由配線15等來與複數的半導體晶片11a~11h連接。IF晶片18是被配置於晶片層疊體20的配線層50側的最上面。但，IF晶片18是不限於圖1的位置，例如亦可配置在記憶晶片層疊體10的半導體晶片11a~11h間等，或IF晶片18本身不設，將IF電路搭載於半導體晶片11a~11h內。IF晶片18的寬度W4是形成比半導體晶片11a~11h(記憶晶片層疊體10)的寬度W1小。
基板30是具有作為晶片層疊體20的支撐體的機能。基板30是在晶片層疊體20的第1面上經由黏著劑41而設。基板30的寬度W2是比半導體晶片11a~11h(記憶晶片層疊體10)的寬度W1大，與配線層的寬度W3相等。基板30是最好具有大於等於1個的半導體晶片11a ~11h的厚度T1之厚度T2。基板30的厚度T2是亦可比配線層50的厚度更薄。基板30的厚度T2是例如100μm~200μm程度。另外，當複數的半導體晶片11a~11h的厚度T1不同時，基板30的厚度T2是最好為大於等於最厚的半導體晶片的厚度T1。
基板30的材料是最好符合(a)具有與構成晶片層疊體20的材料(主要是矽)的熱膨脹係數接近的熱膨脹係數、(b)剛性高、(c)容易切斷及研磨之材料。藉由符合(a)，即使經過半導體裝置1的製造工程的熱處理，還是可抑制晶片層疊體20的彎曲。藉由符合(b)，可抑制晶片層疊體20的彎曲。藉由符合(c)，容易進行封裝時的切割工程的切斷或基板的薄化工程的研磨。作為符合如此之(a)~(c)的要求的材料，最好是矽。因此，基板30最好是使用矽基板。
基板30是具有切斷部31。切斷部31是位於比晶片層疊體20的配置的領域更外側。切斷部31是從基板30之與晶片層疊體20對向的面30A貫通至與此面相反側的面30B。
配線層50是設在晶片層疊體20的第2面上。配線層50是經由內部連接端子43及44來與晶片層疊體20的電極焊墊17連接。在配線層50之與晶片層疊體20相反側的面是設有外部連接端子46。外部連接端子46是經由配線層50內的配線網(未圖示)來與內部連接端子43及44電性連接。像本圖那樣將半導體裝置1作為BGA (Ball Grid Array)封裝使用時，外部連接端子46是以具有焊錫球、焊錫電鍍、Au電鍍等的突起端子所構成。但，本實施形態的半導體裝置1是在作為外部連接端子46而設置金屬接端面的LGA(Land Grid Array)型或CSP(Chip Size Package)型等的其他的半導體封裝也可適用。
配線層50是例如在絕緣樹脂基板或絕緣樹脂層的表面及內部設置配線網(未圖示)者。配線層50具體而言是可利用使用玻璃-環氧樹脂或BT樹脂(Bismaleimide Triazine Resin)等的絕緣樹脂之印刷配線板(多層印刷基板等)。如此構成配線層50的主要材料是樹脂，因此與基板30的材料(矽)不同。另外，配線層50是也包含中介層(interposer)、配線基板、封裝基板、或直接形成晶片層疊體20上的再配線層。
樹脂42是設在複數的半導體晶片11a~11h間及記憶晶片層疊體10的側面。樹脂42是埋入基板30的切斷部31內。因此，樹脂42是從切斷部31之基板30的面30B露出。樹脂45是覆蓋樹脂42，設在基板30與配線層50之間。
樹脂42及45是例如熱硬化性樹脂。熱硬化性樹脂是例如可使用在環氧系樹脂、丙烯系樹脂、胺系樹脂、矽氧系樹脂、聚醯亞胺系樹脂等中混合矽石等的充填材(填充物)者。樹脂42與樹脂45是例如可使用成分不同的材料。樹脂42是例如環氧系樹脂，最好是填充物粒子小的 材料、液狀的浸透容易的材料。樹脂45是例如環氧系樹脂，最好是填充物粒子大，且熱膨脹係數接近晶片層疊體20的材料之材料。如此，樹脂42與樹脂45是即使為同環氧系樹脂，也最好成分不同。但，樹脂42與樹脂45是亦可為同成分的同材料。
[1-2]製造方法
利用圖2~圖10來說明有關第1實施形態的半導體裝置1的製造方法。
首先，如圖3所示般，例如對於Si基板30進行半切斷，形成切斷部31(圖2的ST1)。另外，切斷部31是具有不貫通基板30程度的預定深度(參照圖5)。切斷部31的深度是例如為基板30的厚度的一半程度。然後，基板30是按每個晶片被切斷(圖2的ST2)。
其次，如圖4及圖5所示般，在晶片載體60上搭載有基板30(圖2的ST3)。此時，基板30是按每個晶片配置於晶片載體60的階差部61。基板30的厚度是最好為大於等於後述的晶片層疊體20的厚度，例如775μm程度。另外，在晶片載體60的階差部61的中央是設有開口部62。
其次，如圖6所示般，在基板30上，經由熱硬化性的黏著劑41來形成晶片層疊體20(圖2的ST4)。以下，參照圖1來說明有關晶片層疊體20的形成。
首先，在基板30上的預定的位置黏著成為記憶晶片 層疊體10的第1段的半導體晶片11a。在此，所謂預定的位置是例如收於基板30的切斷部31的內側之類的位置。然後，在半導體晶片11a上依序層疊預定的段數的半導體晶片11b~11h，形成記憶晶片層疊體10。此時，半導體晶片11a~11h的相互間是以由矽所構成的貫通電極12與凸塊電極13能夠連接的方式進行對位而連接。而且，在未形成有貫通電極12的領域中，於半導體晶片11a~11h的一面是複數的黏著劑14會以點在的方式形成。藉由此黏著劑14，在層疊半導體晶片11a~11h時，對向的半導體晶片11a~11h會被黏著而固定。
其次，在位於記憶晶片層疊體10的最上段的半導體晶片11h上形成有絕緣膜16，在此絕緣膜16內形成有連接至貫通電極12的配線15。而且，搭載有被連接至此配線15的IF晶片18。IF晶片18是對於記憶晶片層疊體10覆晶連接(FC連接)。如此，形成晶片層疊體20(圖2的ST4)。
其次，如圖6所示般，晶片層疊體20的側面及構成晶片層疊體20的半導體晶片11a~11h之間會以鑄模樹脂42所密封(圖2的ST5)。此時，樹脂42是充填基板30的切斷部31內。並且，切斷部31會成為制止部(stopper)，使樹脂42不會擴展至比切斷部31更外側。另外，藉由樹脂42的密封是亦可在形成晶片層疊體20的工程途中適當進行。
其次，如圖7所示般，晶片層疊體20會被連接至配 線層50(圖2的ST6)。具體而言，以晶片層疊體20的IF晶片18能夠與配線層50對向的方式配置。而且，進行晶片層疊體20與配線層50之對應的內部連接端子43及44的對位，藉由預先塗佈的暫時固定材(未圖示)來進行暫時黏著。然後，藉由在蟻酸環境等的還原環境中加熱(回流)，晶片層疊體20與配線層50會被電性連接。
在此，之所以利用還原環境，是為了使電性連接確實地進行，而將形成於內部連接端子43的表面之氧化膜等還原、除去。並且，內部連接端子43是例如以焊錫材料或Au作為主成分。內部連接端子43是進行記憶晶片層疊體10的最上段的半導體晶片11h與配線層50之間的電性連接。
另外，上述是顯示利用還原環境的回流之連接方法，但除此以外亦可使用利用焊劑之內部連接端子43的還原與利用焊錫回流之一般性的覆晶連接方法。
其次，如圖8所示般，晶片層疊體20與配線層50之間會以樹脂45所充填(圖2的ST7)，同時基板30會以樹脂45所覆蓋。另外，此工程是亦可分開實施以樹脂來充填晶片層疊體20與配線層50之間的工程、及以樹脂來被覆基板30的工程。此情況，亦可使用不同的樹脂(未圖示)。
其次，如圖9所示般，樹脂45及基板30會被同時被研磨(圖2的ST8)。此時，亦可切斷部31內的樹脂42也被研磨，從基板30露出樹脂42。然後，在配線層50 的外側的面上形成外部連接端子46。
其次，如圖10所示般，藉由切割來切斷基板30、配線層50及樹脂45，進行小片的封裝化(圖2的ST9)。如此完成圖1所示的層疊型半導體裝置1。
[1-3]效果
若根據上述第1實施形態，則使用矽基板30作為晶片層疊體20的支撐體。如此的矽基板30是與具有使用矽基板所形成的半導體晶片11a~11h及IF晶片18之晶片層疊體20相同的熱膨脹係數。並且，矽是剛性高，切斷及研磨容易。因此，藉由使用矽基板30作為支撐體，可抑制半導體晶片11a~11h的彎曲，可使半導體裝置1的可靠度提升。而且，因為矽基板30容易研磨及切割，所以容易實現封裝的小型化及薄化。
[2]第2實施形態
第1實施形態是晶片層疊體20的支撐體的基板30的厚度T2為一定。相對於此，第2實施形態是基板30的厚度T2在中央部及端部不同。第2實施形態是利用圖11及圖12來說明有關與第1實施形態相異的點。
如圖11及圖12所示般，第2實施形態的半導體裝置1是藉由基板30及晶片層疊體20彎曲，基板30的中央部的厚度T2a與基板30的端部的厚度T2b會不同。但，在此所謂的基板30及晶片層疊體20彎曲是以往的問題充 分可減低的程度的稍微的彎曲。
圖11的情況，晶片層疊體20是具有突出至基板30側的彎曲。因此，基板30的面30A會形成凹陷至內側的凹形狀。亦即，基板30的中央部的厚度T2a是形成比基板30的端部的厚度T2b薄。
圖12的情況，晶片層疊體20是具有突出於配線層50側的彎曲。因此，基板30的面30A會形成突出至外側的凸形狀。亦即，基板30的中央部的厚度T2a是比基板30的端部的厚度T2b厚。
在此，於圖11及圖12的半導體裝置1中，基板30之形成有晶片層疊體20的領域，亦即基板30的中央部的厚度T2a是最好為大於等於1個半導體晶片11a~11h的厚度T1。
若根據上述第2實施形態，則即使基板30及晶片層疊體20稍微彎曲時，亦與第1實施形態同樣，相較於以往，可抑制半導體晶片11a~11h的彎曲。
另外，當基板30及晶片層疊體20不彎曲，而基板30的厚度T2有偏差時，也最好形成晶片層疊體20的領域之基板30的厚度T2為大於等於1個半導體晶片11a~11h的厚度T1。
[3]第3實施形態
第3實施形態的半導體裝置1是基板30的切斷部31的變形例。第3實施形態是利用圖13~圖16來說明有關 與第1實施形態不同的點。
如圖13所示般，切斷部31亦可為凹部形狀。亦即，切斷部31是從與晶片層疊體20對向的面30A凹陷的凹部。因此，切斷部31內的樹脂42是未從基板30的外側面30B露出。如此之圖13的半導體裝置1的情況，藉由樹脂42進入凹部，基板30之對於樹脂42的緊貼性會提升，具有對於封裝的變形應力的可靠度提高的效果。
如圖14所示般，亦可在切斷部31的內部進行切割。亦即，切斷部31內的樹脂42會從基板30的側面露出。換言之，基板30的周圍會形成以樹脂42所覆蓋的狀態。如此之圖14的半導體裝置1的情況，基板30的端部不會露出於封裝端部，藉由樹脂42所保護，具有對於封裝的耐衝撃的可靠度提高的效果。
如圖15所示般，亦可在凹部形狀的切斷部31的內部進行切割。亦即，切斷部31內的樹脂42會從基板30的內側部分的側面露出。換言之，基板30的內側部分的側面的周圍會形成以樹脂42所覆蓋的狀態。並且，基板30是形成朝晶片層疊體20突出的凸形狀。如此之圖15的半導體裝置1的情況，藉由基板30的端部形成薄，樹脂42與基板30的熱膨脹係數的差所產生的應力會藉由基板30變形而被緩和，具有熱的可靠度提高的效果。
如圖16所示般，亦可在比切斷部31還內側進行切割，切斷部31變無。如此之圖16的半導體裝置1的情況，藉由比較厚的基板30存在至封裝端部，封裝全體的 剛性會提升，具有封裝的運用的可靠度提高的效果。
若根據以上那樣的第3實施形態的半導體裝置1，則與第1實施形態同樣，可抑制半導體晶片11a~11h的彎曲。
[4]第4實施形態
第4實施形態的半導體裝置1是有關切斷部31內的樹脂之變形例。第4實施形態是利用圖17及圖18來說明有關與第1實施形態不同的點。
如圖17所示般，以樹脂42來密封晶片層疊體20的周圍時，樹脂42亦可不進入切斷部31內。此情況，最終構造的半導體裝置1是如圖18所示般，亦可以樹脂45來埋入切斷部31。
若根據以上那樣的第4實施形態的半導體裝置1，則與第1實施形態同樣，可抑制半導體晶片11a~11h的彎曲。
又，第4實施形態的半導體裝置1是藉由切斷部31內以樹脂45所埋入，與切斷部31內以樹脂42所埋入時作比較，相對熱膨脹係數大的樹脂42的硬化時的收縮應力不會施加於基板30的薄部分，具有可靠度提高的效果。
[5]第5實施形態
第5實施形態是利用圖19~圖21來說明有關各實施 形態的基板30的平面圖。
如圖19所示般，在基板30的內側設有切斷部31，基板30的側面的周圍是未以樹脂42及45所包圍。如此的平面圖的半導體裝置1是例如具有圖1那樣的剖面構造。圖19的半導體裝置1是藉由樹脂42或樹脂45進入切斷部31，基板30之對於樹脂42或45的緊貼性會提升，具有對於封裝的變形應力之可靠度高的效果。
如圖20所示般，在基板30的周圍形成有樹脂42或45，基板30的側面全部會以樹脂42或45所覆蓋。如此的平面圖的半導體裝置1是例如具有圖14那樣的剖面構造。圖20的半導體裝置1是基板30的端部不會露出於封裝端部，藉由樹脂42或樹脂45來保護，具有對於封裝的耐衝撃的可靠度提高的效果。
如圖21所示般，基板30的側面的一部分會以樹脂42或45所覆蓋。如此的平面圖的半導體裝置1是例如具有圖14或圖16那樣的剖面構造。圖21的半導體裝置1是有關基板30的端部不會露出於封裝端部，藉由樹脂42或樹脂45所保護的部分具有對於封裝的耐衝撃的可靠度提高的效果。
若根據以上那樣的第5實施形態的半導體裝置1，則與第1實施形態同樣，可抑制半導體晶片11a~11h的彎曲。
另外，基板30的切斷部31是在基板30的一側面，不限於以1個的切斷部所形成，亦可設有複數個的切斷 部。
[6]第6實施形態
第6實施形態的半導體裝置1是有關基板30的寬度W2的變形例。第6實施形態是利用圖22及圖23來說明有關與第1實施形態不同的點。
如圖22所示般，基板30的寬度W2是亦可比配線層50的寬度W3小。此情況，如圖23所示般，基板30的側面的周圍是以樹脂45所覆蓋。
若根據以上那樣的第6實施形態的半導體裝置1，則與第1實施形態同樣，可抑制半導體晶片11a~11h的彎曲。
另外，基板30的寬度W2是亦可與晶片層疊體20的寬度W1相同。
[7]第7實施形態
第7實施形態是利用圖24~圖28來說明有關與第1實施形態不同的半導體裝置1的製造方法。在此是說明有關與第1實施形態不同的點。
首先，如圖25~圖27所示般，例如對於矽基板30進行半切斷，形成切斷部31(圖24的ST1)。基板30是亦可為圖25的矽晶圓(圓形)或圖26的矽的長基板(長方形)。
其次，如圖28所示般，在基板30上經由熱硬化性的 黏著劑41來形成晶片層疊體20(圖24的ST2’)。
其次，在晶片層疊體20的側面上、構成晶片層疊體20的半導體晶片11a~11h之間的空間及切斷部31內充填有層間密封樹脂42(圖24的ST3’)。
其次，基板30是按每個晶片被切斷(圖24的ST4’)。
然後，與第1實施形態同樣，進行圖24的步驟ST6~ST9。
第1實施形態是在半切斷之後進行基板30的每個晶片的切斷。相對於此，第7實施形態是以樹脂42來密封晶片層疊體20的側面之後進行基板30的每個晶片的切斷。並且，第7實施形態的半導體裝置1的製造工程是未使用晶片載體60。如此的第7實施形態的半導體裝置1亦與第1實施形態同樣，可抑制半導體晶片11a~11h的彎曲。
[8]第8實施形態
第8實施形態的半導體裝置1是有關研磨前之基板30的形狀的變形例。第8實施形態是利用圖29來說明有關與第1實施形態不同的點。
如圖29所示般，基板30是亦可具有對應於載體60的開口部62的突出部32。突出部32是設在與基板30之形成有切斷部31的面相反側的面。
另外，基板30的突出部32是在圖9的研磨工程被削 除。因此，第8實施形態的最終的半導體裝置10是形成與圖1同樣的構造。但，在圖9的研磨工程後，基板30的突出部32亦可殘留。
若根據以上那樣的第8實施形態的半導體裝置1，則與第1實施形態同樣，可抑制半導體晶片11a~11h的彎曲。又，若根據第8實施形態，則搬送至晶片載體60時，基板30的突出部32會嵌入載體60的開口部62。因此，可安定地進行之後的製程。
[9]第9實施形態
第9實施形態的半導體裝置1是使用DRAM作為各半導體晶片11a~11h的情況。第9實施形態是利用圖30來說明有關與第1實施形態不同的點。
如圖30所示般，各半導體晶片11a~11h是亦可為例如具有DRAM的記憶晶片。此情況，IF晶片18是使用寬度比圖1的構造寬的晶片，被連接至內部連接端子43及44。
若根據以上那樣的第9實施形態的半導體裝置1，則與第1實施形態同樣，可抑制半導體晶片11a~11h的彎曲。
[10]第10實施形態
第10實施形態是使用半導體晶片作為成為晶片層疊體20的支撐體的基板70之例。在此是說明有關與第1實 施形態不同的點。
[10-1]構造
利用圖31來說明有關第10實施形態的半導體裝置1的構造。
如圖31所示般，第10實施形態的半導體裝置1是在成為晶片層疊體20的支撐體的基板70搭載有半導體積體電路。亦即，基板70是與構成晶片層疊體20的半導體晶片11a~11h同構成。因此，基板70亦可謂晶片層疊體20的第一段的半導體晶片的基板。
基板70的厚度T2是最好為大於等於1個半導體晶片11a~11h的厚度T1之厚度。基板70的厚度T2是例如為1個半導體晶片11a~11h的厚度T1的3~5倍程度。例如，基板70的厚度T2是150μm程度，各半導體晶片11a~11h的厚度T1是30~50μm程度。
基板70的寬度W2是與半導體晶片11a~11h(記憶晶片層疊體10)的寬度W1相等。但，基板70的寬度W2是亦可比半導體晶片11a~11h(記憶晶片層疊體10)的寬度W1大。又，基板70與半導體晶片11a~11h(記憶晶片層疊體10)是亦可為同一尺寸。
基板70是不具有設在半導體晶片11a~11h內的貫通電極12。但，亦可為在基板70內形成貫通電極12。
樹脂45是設在複數的半導體晶片11a~11h間、記憶晶片層疊體10及基板70的側面。
[10-2]製造方法
利用圖32~圖37來說明有關第10實施形態的半導體裝置1的製造方法。
首先，如圖32所示般，在晶片載體60上搭載基板70。基板70是搭載有半導體積體電路的半導體晶片的基板。基板70的厚度是最好為大於等於晶片層疊體20的厚度，例如775μm程度。
其次，如圖33所示般，在基板70上形成晶片層疊體20。其次，如圖34所示般，晶片層疊體20會經由內部連接端子43來連接至配線層50。其次，如圖35所示般，基板70、晶片層疊體20及配線層50會以樹脂45來密封。此時，樹脂45亦可充填於晶片層疊體20的複數的半導體晶片11a~11h間。
其次，如圖36所示般，樹脂45及基板70會同時被研磨，基板70被薄化。其次，如圖37所示般，藉由切割，基板70、配線層50及樹脂45會被切斷，進行小片的封裝化。如此，完成圖10所示的層疊型半導體裝置1。
若根據以上那樣的第10實施形態的半導體裝置1，則與第1實施形態同樣，可抑制半導體晶片11a~11h的彎曲。
另外，第10實施形態的半導體裝置1是如圖38及圖39所示般，與上述第2實施形態的半導體裝置1同樣， 基板70的中央部的厚度T2a與基板70的端部的厚度T2b亦可為不同。
以上說明了本發明的幾個實施形態，但該等的實施形態是舉例提示者，非意圖限定發明的範圍。該等新穎的實施形態是可在其他各種的形態下被實施，可在不脫離發明的要旨的範圍內進行各種的省略、置換、變更。該等實施形態或其變形是為發明的範圍或要旨所包含，且為申請專利範圍記載的發明及其均等的範圍所包含。
1‧‧‧半導體裝置
10‧‧‧記憶晶片層疊體
11a~11h‧‧‧半導體晶片
12‧‧‧貫通電極
13‧‧‧凸塊電極
14‧‧‧黏著劑
15‧‧‧配線
16‧‧‧絕緣膜
17‧‧‧電極焊墊
18‧‧‧介面晶片(IF晶片)
20‧‧‧晶片層疊體
30‧‧‧基板
30A、30B‧‧‧面
31‧‧‧切斷部
41‧‧‧黏著劑
42‧‧‧樹脂
43、44‧‧‧內部連接端子
45‧‧‧樹脂
46‧‧‧外部連接端子
50‧‧‧配線層
W1~W4‧‧‧寬度
T1、T2‧‧‧厚度

Claims (22)

  1. 一種半導體裝置，其特徵係具備：層疊體，其係包含複數的半導體晶片，前述複數的半導體晶片的至少一部分係具有貫通前述半導體晶片的電極，前述複數的半導體晶片係被層疊且經由前述電極來互相連接，具有第1寬度；矽基板，其係設於前述層疊體的第1面上，具有比前述第1寬度大的第2寬度；配線層，其係設於前述層疊體的第2面上；及樹脂，其係設於前述層疊體的周圍，前述矽基板係具有大於等於1個的半導體晶片的厚度之厚度。
  2. 如申請專利範圍第1項之半導體裝置，其中，前述矽基板係具有切斷部，前述切斷部係位於比前述層疊體的配置的領域更外側，前述樹脂係設於前述切斷部內。
  3. 如申請專利範圍第2項之半導體裝置，其中，前述切斷部係從前述矽基板的第3面貫通至第4面，前述第3面係與前述層疊體的前述第1面對向，前述第4面係位於與前述第3面相反的側。
  4. 如申請專利範圍第3項之半導體裝置，其中，前述切斷部內的前述樹脂係從前述矽基板的前述第4面露出。
  5. 如申請專利範圍第2項之半導體裝置，其中，前述 切斷部係從前述矽基板之與前述層疊體的前述第1面對向的面凹陷的凹部。
  6. 如申請專利範圍第1項之半導體裝置，其中，前述矽基板的中央部的厚度係與前述矽基板的端部的厚度不同。
  7. 如申請專利範圍第1項之半導體裝置，其中，前述矽基板的前述第2寬度係與前述配線層的第3寬度相等。
  8. 如申請專利範圍第1項之半導體裝置，其中，前述矽基板的前述第2寬度係比前述配線層的第3寬度小。
  9. 如申請專利範圍第1項之半導體裝置，其中，前述矽基板的側面的至少一部分係以前述樹脂所覆蓋。
  10. 如申請專利範圍第1項之半導體裝置，其中，前述矽基板的側面的全部係從前述樹脂露出。
  11. 如申請專利範圍第1項之半導體裝置，其中，具有第1晶片，該第1晶片係設於前述配線層與前述層疊體的前述第2面之間，被電性連接至前述層疊體，具有比前述第1寬度小的第4寬度。
  12. 一種半導體裝置，其特徵係具備：層疊體，其係包含複數的半導體晶片，前述複數的半導體晶片係具有貫通前述半導體晶片的電極，前述複數的半導體晶片係被層疊且經由前述電極來互相連接，具有第1寬度；矽基板，其係設於前述層疊體的第1面上，具有前述第1寬度，構成半導體晶片； 配線層，其係設於前述層疊體的第2面上；及樹脂，其係設於前述層疊體的周圍，前述矽基板係具有大於等於前述層疊體的1個的半導體晶片的厚度之厚度，具有第1晶片，該第1晶片係設於前述配線層與前述層疊體的前述第2面之間，被電性連接至前述層疊體，具有比前述第1寬度小的第2寬度。
  13. 如申請專利範圍第12項之半導體裝置，其中，前述矽基板的中央部的厚度係與前述矽基板的端部的厚度不同。
  14. 如申請專利範圍第12項之半導體裝置，其中，前述矽基板的中央部的厚度係比前述矽基板的端部的厚度薄。
  15. 如申請專利範圍第12項之半導體裝置，其中，前述矽基板的中央部的厚度係比前述矽基板的端部的厚度厚。
  16. 一種半導體裝置的製造方法，其特徵係具備：在矽基板上層疊具有貫通半導體晶片的電極之複數的半導體晶片，形成前述複數的半導體晶片經由前述電極來互相連接的層疊體之工程；將配線層連接至前述層疊體之工程；在前述矽基板上及前述層疊體的周圍形成樹脂之工程；及切削前述矽基板，將前述矽基板的厚度弄薄之工程。
  17. 如申請專利範圍第16項之半導體裝置的製造方法，其中，前述層疊體係具有第1寬度，前述矽基板係具有比前述第1寬度大的第2寬度。
  18. 如申請專利範圍第16項之半導體裝置的製造方法，其中，更具備：在形成前述層疊體之前，在前述矽基板形成切斷部之工程，前述切斷部係位於比前述層疊體的形成的領域更外側，前述樹脂係形成於前述切斷部內。
  19. 一種半導體裝置，其特徵係具備：層疊體，其係包含複數的半導體晶片，前述複數的半導體晶片的至少一部分係具有貫通前述半導體晶片的電極，前述複數的半導體晶片係被層疊且經由前述電極來互相連接，具有第1寬度；矽基板，其係設於前述層疊體的第1面上，具有比前述第1寬度大的第2寬度；配線層，其係設於前述層疊體的第2面上；及樹脂，其係設於前述層疊體的周圍，前述矽基板的前述第2寬度係比前述配線層的第3寬度小。
  20. 一種半導體裝置，其特徵係具備：層疊體，其係包含複數的半導體晶片，前述複數的半導體晶片的至少一部分係具有貫通前述半導體晶片的電 極，前述複數的半導體晶片係被層疊且經由前述電極來互相連接，具有第1寬度；矽基板，其係設於前述層疊體的第1面上，具有比前述第1寬度大的第2寬度；配線層，其係設於前述層疊體的第2面上；及樹脂，其係設於前述層疊體的周圍，前述矽基板的側面的至少一部分係以前述樹脂所覆蓋。
  21. 一種半導體裝置，其特徵係具備：層疊體，其係包含複數的半導體晶片，前述複數的半導體晶片的至少一部分係具有貫通前述半導體晶片的電極，前述複數的半導體晶片係被層疊且經由前述電極來互相連接，具有第1寬度；矽基板，其係設於前述層疊體的第1面上，具有比前述第1寬度大的第2寬度；配線層，其係設於前述層疊體的第2面上；及樹脂，其係設於前述層疊體的周圍，具有第1晶片，該第1晶片係設於前述配線層與前述層疊體的前述第2面之間，被電性連接至前述層疊體，具有比前述第1寬度小的第4寬度。
  22. 一種半導體裝置，其特徵係具備：層疊體，其係包含複數的半導體晶片，前述複數的半導體晶片的至少一部分係具有貫通前述半導體晶片的電極，前述複數的半導體晶片係被層疊且經由前述電極來互 相連接，具有第1寬度；矽基板，其係設於前述層疊體的第1面上，具有比前述第1寬度大的第2寬度；配線層，其係設於前述層疊體的第2面上；及樹脂，其係設於前述層疊體的周圍，前述矽基板的前述第2寬度係與前述配線層的第3寬度相等。
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