CN112490223B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN112490223B
CN112490223B CN202010120717.5A CN202010120717A CN112490223B CN 112490223 B CN112490223 B CN 112490223B CN 202010120717 A CN202010120717 A CN 202010120717A CN 112490223 B CN112490223 B CN 112490223B
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semiconductor chip
semiconductor
adhesive
semiconductor device
film
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CN112490223A (zh
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荒井俊光
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Kioxia Corp
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Kioxia Corp
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Abstract

实施方式提供一种能够提高可靠性的半导体装置。实施方式的半导体装置在布线衬底(1)上积层多个背面贴附了膜状粘接剂(2、4)的半导体芯片(3)，利用导电性导线(5)将布线衬底(1)与多个半导体芯片(3)连接，且具备贴附了FOW(4a)的半导体芯片(3c)、及经由FOW(4a)与半导体芯片(3c)固着的半导体芯片(3b)。半导体芯片(3b)的正面包含由FOW(4a)覆盖的第1部分、及未由FOW(4a)覆盖的第2部分。半导体装置进而具备树脂(6a)，该树脂(6a)覆盖第2部分、及位于半导体芯片(3b)的正面上的FOW(4a)的侧端面。

Description

半导体装置
[相关申请]
本申请享有以日本专利申请2019-166233号(申请日：2019年9月12日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
本实施方式涉及一种半导体装置。
背景技术
已知有一种将多个半导体芯片搭载在1个半导体封装体内而成的MCP(Multi ChipPackage，多芯片封装体)。
发明内容
本发明要解决的问题是，本实施方式将提供一种能够提高可靠性的半导体装置。
本实施方式的半导体装置在布线衬底上积层多个背面贴附了膜状粘接剂的半导体芯片，利用导电性导线将所述布线衬底与多个所述半导体芯片连接，且具备：第1半导体芯片，是在背面贴附了可供埋入所述导电性导线的所述膜状粘接剂即第1粘接剂的所述半导体芯片；及第2半导体芯片，是经由所述第1粘接剂与所述第1半导体芯片固着的所述半导体芯片。
所述第2半导体芯片的正面包含由所述第1粘接剂覆盖的第1部分、及未由所述第1粘接剂覆盖的第2部分，且所述半导体装置进而具备覆膜部，该覆膜部覆盖所述第2部分、及位于所述第2半导体芯片的正面上的所述第1粘接剂的侧端面。
附图说明
图1是表示本实施方式的半导体装置的构造的剖视图。
图2是示意性地表示从上表面观察到的本实施方式的半导体装置的构造的俯视图。
图3是说明由应力集中所致的半导体芯片的翘曲的剖视图。
图4是表示本实施方式的半导体装置的制造步骤的一例的流程图。
图5A是表示半导体装置的制造步骤中的截面构造的图。
图5B是表示半导体装置的制造步骤中的截面构造的图。
图5C是表示半导体装置的制造步骤中的截面构造的图。
图5D是表示半导体装置的制造步骤中的截面构造的图。
图5E是表示半导体装置的制造步骤中的截面构造的图。
图5F是表示半导体装置的制造步骤中的截面构造的图。
图5G是表示半导体装置的制造步骤中的截面构造的图。
图5H是表示半导体装置的制造步骤中的截面构造的图。
图5I是表示半导体装置的制造步骤中的截面构造的图。
图5J是表示半导体装置的制造步骤中的截面构造的图。
具体实施方式
以下，参照附图来说明实施方式。
图1是表示本实施方式的半导体装置的构造的剖视图。在以下说明中，使用作为正交座标系统的一例的xyz座标系统。即，将与构成半导体装置100的布线衬底1的表面平行的平面设为xy平面，将与xy平面正交的方向设为z轴。另外，x轴与y轴是设为xy平面内的正交的两方向。此外，以下，为了方便说明，使用将z轴正方向侧(衬底1的第1表面1a侧)设为上侧，将z轴负方向侧(衬底1的第2表面1b侧)设为下侧的上下关系进行说明，但并不表示普遍性的上下关系。
图1中表示将半导体装置100沿着xz平面切断后的截面(以下表示为xz截面)的构造。此外，以下使用xz截面的构造进行说明，但yz截面等xz截面以外的截面中也可存在相同的构造。
图1所示的半导体装置100具备布线衬底1。布线衬底1是例如在表面或内部设置着布线层(未图示)的绝缘树脂布线衬底或陶瓷布线衬底等。具体来说，例如利用使用了玻璃环氧树脂的印刷布线衬底等。或者，也可使用硅中介层或引线框架等。
布线衬底1具备第1表面1a及第2表面1b。在第2表面1b，形成着BGA(Ball GridArray，球栅阵列)封装体用的外部端子(由焊料球等形成的突起状端子)或LGA(Land gridarray，焊盘网格阵列)封装体用的外部端子(通过金属镀覆等形成的金属焊盘)。此外，这些外部端子省略了图示。
在布线衬底的第1表面1a，设置着多个半导体芯片3a～3f。以下，在无需区分半导体芯片3a～3f的情况下，简单地表示为半导体芯片3。半导体芯片3a～3f中，在z方向上配置在最下侧的半导体芯片为半导体芯片3a。在半导体芯片3a的上方，将半导体芯片3b、3c、3d、3e、3f依序朝z轴正方向积层配置。
半导体芯片3b相对于半导体芯片3a朝x轴正方向错开特定距离(例如300μm左右)地配置。另外，半导体芯片3c相对于半导体芯片3b朝x轴负方向错开特定距离(例如300μm左右)地配置。进而，半导体芯片3d相对于半导体芯片3c朝x轴正方向错开特定距离(例如300μm左右)地配置。另外，半导体芯片3e相对于半导体芯片3d朝x轴负方向错开特定距离(例如300μm左右)地配置。进而，半导体芯片3f相对于半导体芯片3e朝x轴正方向错开特定距离(例如300μm左右)地配置。即，各半导体芯片3的上表面的一部分以未由其它半导体芯片3覆盖的方式配置。
此外，半导体芯片3可列举例如像NAND(Not AND，与非)闪存这样的半导体芯片，但不限定于此，可使用任意的半导体芯片。另外，在图1中，记载了将6片半导体芯片3积层而成的构造，但也可以是3片以上的任意片数。
半导体芯片3在各背面整体贴附了膜状粘接剂2、4。膜状粘接剂2、4是使用了热硬化树脂(例如环氧系树脂、聚酰亚胺系树脂、丙烯酸系树脂、或将这些混合而成的树脂)的粘接剂，厚度根据用途而异。一般来说，布线衬底1与半导体芯片3粘接或半导体芯片3彼此粘接的用途中所使用的膜状粘接剂2具有5μm～20μm左右的厚度。供埋入用于将半导体芯片3与布线衬底1之间电连接的导电性导线5、或用于将半导体芯片3与其它半导体芯片3电连接的导电性导线5，且将经积层的半导体芯片3彼此粘接的用途中所使用的膜状粘接剂4具有40μm～60μm左右的厚度。以下说明中，将未埋入导电性导线5而使用的膜状粘接剂2表示为DAF(Die Attach Film，裸片贴合膜)2。另外，将能够埋入导电性导线5的膜状粘接剂4表示为FOW(Film On Wire，膜覆线)4。此外，在图1中，导电性导线5图示为导电性导线5a～5f，但本说明书中，在无需区分导电性导线5a～5f的情况下，简单地表示为导电性导线5。此外，导电性导线5为导电性部件的一例。也可使用非导线状的导电性部件，将半导体芯片3与布线衬底1间或半导体芯片3与其它半导体芯片3之间电连接。
半导体芯片3经由DAF2或FOW4与布线衬底1或其它半导体芯片3固着。具体来说，半导体芯片3a经由DAF2a固着于布线衬底1。另外，半导体芯片3b经由DAF2b与半导体芯片3a固着。另外，半导体芯片3c经由FOW4a与半导体芯片3b固着。另外，半导体芯片3d经由DAF2c与半导体芯片3c固着。另外，半导体芯片3e经由FOW4b与半导体芯片3d固着。进而，半导体芯片3f经由DAF2d与半导体芯片3e固着。
半导体芯片3a与布线衬底1通过导电性导线5a电连接。另外，半导体芯片3b与布线衬底1通过导电性导线5b电连接。另外，半导体芯片3c与布线衬底1通过导电性导线5c电连接。另外，半导体芯片3d与布线衬底1通过导电性导线5d电连接。另外，半导体芯片3e与布线衬底1通过导电性导线5e电连接。进而，半导体芯片3f与布线衬底1通过导电性导线5f电连接。
此外，半导体芯片3有时也经由其它半导体芯片3与布线衬底1电连接。例如，一端连接于半导体芯片3b的导电性导线5b的另一端有时连接于布线衬底1，也有时连接于半导体芯片3a。此处，关于导电性导线5b的配置，使用图2更具体地进行说明。
图2是示意性地表示从上表面观察到的本实施方式的半导体装置的构造的俯视图。图2是表示将半导体芯片3a～3c积层之后，且将导电性导线5c与半导体芯片3c结合之前的俯视图。在图2中，以虚线的矩形区域示出半导体芯片3b，以粗线的矩形区域示出半导体芯片3c。此外，从上表面观察的情况下，半导体芯片3a为与半导体芯片3c相同的形状，且配置在相同位置。此外，在本案说明书中，所谓“相同”不仅包含严格相同，也包含例如制造步骤中的偏差等。在布线衬底1、半导体芯片3a及半导体芯片3b上，沿着各区域中左端侧的一边，形成着包含用来连接导电性导线5的多个电极的电极区域WA。即，在布线衬底1形成着电极区域WA1，在半导体芯片3a形成着电极区域WA3a。另外，在半导体芯片3b，形成着电极区域WA3b。
电极区域WA3a形成在比半导体芯片3b的左端更靠左侧的区域，成为在电极区域WA3a的上部未覆盖半导体芯片3b的构造。另外，在半导体芯片3a的上部，从上表面观察时在相同位置配置着半导体芯片3c。因此，成为在电极区域WA3a的上部覆盖着半导体芯片3c的构造。由于具有这种构造，一端连接于半导体芯片3a的电极区域WA3a的导电性导线5a通过贴附在半导体芯片3c的背面的FOW4a的下表面与半导体芯片3a的上表面之间的空间，与布线衬底1的电极区域WA1结合。
另一方面，电极区域WA3b与贴附在半导体芯片3c的背面的FOW4a的下表面相接(密接)地形成。因此，一端连接于半导体芯片3b的电极区域WA3b的导电性导线5b从贴附在半导体芯片3c的背面的FOW4a中通过，与半导体芯片3a的电极区域WA3a或布线衬底1的电极区域WA1结合。
像这样，半导体芯片3上的电极区域WA与贴附在其它半导体芯片3的背面的膜状粘接剂密接地形成的情况下，一端连接于该电极区域WA的导电性导线5必须从膜状粘接剂之中通过。即，以下表面与形成于半导体芯片3的电极区域WA密接的方式配置的膜状粘接剂由于必须将导电性导线5埋入(从膜状粘接剂之中穿过)，所以必须使用作为第1粘接剂的FOW4而非DAF2。
在具有图1的构造的半导体装置100中，半导体芯片3b上的电极区域WA与贴附在半导体芯片3c的背面的膜状粘接剂4a密接地形成，另外，半导体芯片3d上的电极区域WA与贴附在半导体芯片3e的背面的膜状粘接剂4b密接地形成。因此，一端连接于半导体芯片3b的导电性导线5b与一端连接于半导体芯片3d的导电性导线5d必须从与各半导体芯片3b、3d的正面密接的膜状粘接剂中穿过。因此，贴附在半导体芯片3c与半导体芯片3e的背面的膜状粘接剂使用了FOW4，贴附在其它半导体芯片3a、3b、3d、3f的背面的膜状粘接剂使用了DAF2。
此外，贴附在半导体芯片3a、3b、3d、3f的背面的膜状粘接剂也能使用FOW4。但是，鉴于对半导体装置100的薄型化的要求不断加强的现状，优选使用膜厚比FOW4薄的DAF2。另外，也有因使用膜厚较厚的FOW4作为膜状粘接剂，而导致FOW4正下方的半导体芯片3产生翘曲的问题，所以优选在无需埋入导电性导线5的部位使用DAF2。
图3是说明由应力集中所致的半导体芯片的翘曲的剖视图。图3表示将半导体芯片3a～3c积层后的芯片右端附近的概略剖视图。此外，在图3中，表示未形成树脂6a的状态。
一般来说，膜状粘接剂的膨胀量根据温度而变化。即，膨胀量随着温度上升而也将变大，随着温度下降而变小。另外，膜状粘接剂的体积越大，则因加热、冷却引起的体积变化越大。另外，与构成半导体芯片3的硅的热膨胀系数相比，膜状粘接剂的热膨胀系数为1个数量级以上的较大的值。因此，在100度以上的高温环境下，膜状粘接剂的膨胀量与硅的膨胀量产生差。
在半导体装置100的制造步骤中，使半导体芯片3彼此固着时，为了使膜状粘接剂热硬化而对半导体装置100整体施加100度以上的热处理。与热膨胀系数相应地，膜状粘接剂在热处理中膨胀，随着温度下降而收缩。与DAF2相比膜厚较厚且体积较大的FOW4因由膨胀、收缩引起的体积变化较大，所以在FOW4a的端部正下方的半导体芯片3b的正面产生局部应力。因此，半导体芯片3b中从FOW4的右端突出的部分如图3所示产生翘曲。在半导体芯片3b中，形成于产生了翘曲的部分的电路部分可能会发生动作不良，而导致半导体装置的可靠性降低。
为了防止如上所述的半导体芯片3b的翘曲，如图1所示，本实施方式的半导体装置1以从作为第1半导体芯片的半导体芯片3c及作为第1粘接剂的FOW4a的右侧端面，连续地覆盖到作为第2半导体芯片的半导体芯片3b的正面且较半导体芯片3c的右端更向右侧突出的部分(半导体芯片3b中的第2部分)的方式，设置着作为覆膜部的树脂6a。另外，与半导体芯片3b同样地，半导体芯片3d也以从半导体芯片3e及FOW4b的右侧面，连续地覆盖到半导体芯片3d的正面且较半导体芯片3e的右端更向右侧突出的部分的方式，设置着树脂6b，以防止翘曲。
树脂6a、6b是具有与FOW4同等的热膨胀系数的热硬化性树脂。此外，在本案说明书中“同等”不仅包含严格相同，也包含例如制造步骤中的偏差等，还包含为了获得本发明的效果所需的范围。此处，使用图2进一步说明由树脂6覆盖的平面区域。在图2中，以单点划线的矩形区域表示半导体芯片3b中的电路区域CA3b(形成着半导体元件或布线等的区域)。考虑到从半导体晶圆切下半导体芯片的切割中的切下位置的偏移，通常在半导体芯片3b的周缘部，设置着未形成电路的切割线。例如，从半导体芯片3b的周缘起25μm左右的区域中设置着切割线。即，在图2中，从单点划线所示的电路区域CA3b的外周到虚线所示的半导体芯片3b的外周之间成为切割线。
树脂6a形成为覆盖半导体芯片3b的正面且从FOW4a的端部即半导体芯片3c的端部突出的部分中的、至少设置在该部分的电路区域CA3b整体。此外，上文中已对形成在半导体芯片3b上的树脂6а进行了叙述，形成在半导体芯片3d上的树脂6b也形成在相同区域。即，树脂6b形成为覆盖半导体芯片3d的正面且从FOW4b的端部即半导体芯片3e的端部突出的部分中的、至少设置在该部分的电路区域整体。
而且，在半导体装置100，在布线衬底1的第1表面1a上形成着密封树脂7，以便覆盖半导体芯片3、及导电性导线5的整体并将它们密封。
接下来，使用图4、图5A～图5J对所述半导体装置100的制造方法进行说明。图4是表示本实施方式的半导体装置的制造步骤的一例的流程图。另外，图5A～图5J是表示半导体装置的制造步骤中的截面构造的图。
首先，使半导体芯片3a、3b依序固着在布线衬底1的第1表面1a上，进行结合(参照S1、图5A)。具体来说，首先，将背面贴附了DAF2a的半导体芯片3a配置在布线衬底1的上表面1a。然后，在半导体芯片3a上的特定位置，配置背面贴附了DAF2b的半导体芯片3b。对整体实施热处理后使DAF2a、3b硬化，使布线衬底1、半导体芯片3a、3b固着。最后，将导电性导线5a与半导体芯片3a及布线衬底1结合并电连接。另外，使用导电性导线5b将半导体芯片3b与布线衬底1、或半导体芯片3b与半导体芯片3a结合并电连接。
随后，在半导体芯片3b上配置背面贴附了FOW4a的半导体芯片3c(参照S2、图5B)。此时，FOW4a为半硬化状态。因此，FOW4a为粘度较低的状态，所以连接于半导体芯片3b的导电性导线5b的一部分埋入到FOW4a中。
然后，对半导体芯片3b的正面中的从FOW4a的端部凸出并露出的部分，使用分配器8等从上方灌注树脂6a(参照S3、图5C)。此外，树脂6a较理想为具有与FOW4a同等的热膨胀系数的树脂。接下来，使所灌注的树脂6a泄漏并扩散到半导体芯片3b的正面及半导体芯片3c与FOW4a的侧面。接着，实施加热处理，使FOW4a与树脂6a热硬化(参照S4、图5D)。通过加热处理，FOW4a与树脂6a的分界部分成为连续状态。此外，加热后的树脂6a形成为至少连续地覆盖半导体芯片3b的正面中形成于未与FOW4a密接的部分的电路区域CA3b、及半导体芯片3c与FOW4a的侧面中位于半导体芯片3b的正面上的部分。
像这样，利用树脂6a覆盖半导体芯片3b正面的露出部分的电路区域，进而，连续地形成树脂6a与FOW4a，由此即使在之后的步骤中施加的加热处理、或完成后的半导体装置100在高温下动作的情况下，也能够防止从FOW4a对半导体芯片3b的正面局部地施加应力。因此，能够抑制形成于半导体芯片3b的电路的动作不良，提高半导体装置的可靠性。
随后，使半导体芯片3d固着在半导体芯片3c上，进行结合(参照S5、图5E)。具体来说，首先，将背面贴附了DAF2c的半导体芯片3d配置在半导体芯片3c上的特定位置。对整体实施热处理而使DAF2c硬化，使半导体芯片3c与3d固着。然后，使用导电性导线5c将半导体芯片3c与布线衬底1结合并电连接。另外，使用导电性导线5d将半导体芯片3d与布线衬底1、或半导体芯片3d与半导体芯片3c结合并电连接。
接下来，在半导体芯片3d上配置背面贴附了FOW4b的半导体芯片3e(参照S6、图5F)。此时，FOW4b为半硬化状态。因此，FOW4b为粘度较低的状态，所以连接于半导体芯片3d的导电性导线5d的一部分埋入到FOW4b中。
然后，对半导体芯片3d的正面中从FOW4b的端部凸出并露出的部分，使用分配器8等从上方灌注树脂6b(参照S7、图5G)。此外，树脂6b较理想为具有与FOW4b同等的热膨胀系数的树脂。接下来，使所灌注的树脂6b泄漏并扩散到半导体芯片3d的正面、及半导体芯片3e与FOW4b的侧面。接着，实施加热处理，使FOW4b与树脂6b热硬化(参照S8、图5H)。通过加热处理，FOW4b与树脂6b的分界部分成为连续状态。此外，加热后的树脂6b形成为至少连续地覆盖半导体芯片3d的正面中形成于未与FOW4b密接的部分的电路区域、及半导体芯片3e与FOW4b的侧面中位于半导体芯片3d的正面上的部分。
像这样，利用树脂6b覆盖半导体芯片3d正面的露出部分的电路区域，进而，连续地形成树脂6b与FOW4b，由此，即使在之后的步骤中施加的加热处理、或完成后的半导体装置100在低温环境下或高温环境下动作的情况下，也能够防止对半导体芯片3d的正面从FOW4b局部地施加应力。因此，能够抑制形成在半导体芯片3d的电路的动作不良，提高半导体装置的可靠性。
随后，使半导体芯片3f固着在半导体芯片3e上，进行结合(参照S9、图5I)。具体来说，首先，将背面贴附了DAF2d的半导体芯片3f配置在半导体芯片3e上的特定位置。对整体实施热处理而使DAF2d硬化，使半导体芯片3e与3f固着。然后，使用导电性导线5e将半导体芯片3e与布线衬底1结合并电连接。另外，使用导电性导线5f将半导体芯片3f与布线衬底1、或半导体芯片3f与半导体芯片3e结合并电连接。
所有半导体芯片3均被固着，且经由导电性导线5与布线衬底1电连接后，最后利用密封树脂7将经积层的半导体芯片3、及已结合的导电性导线5塑封(molding)(参照S10、图5J)。在布线衬底1的第2表面1b的特定位置，形成BGA封装体用的外部端子(由焊料球等形成的突起状端子)或LGA封装体用的外部端子(通过金属镀覆等形成的金属焊盘)，半导体装置100完成。
如上所述，根据本实施方式，关于多个半导体芯片3经由像FOW4这样的厚膜的膜状粘接剂积层而成的半导体装置，具有从位于上下方的半导体芯片3所凸出的部分，且在经由FOW4与正上方的半导体芯片3粘接的半导体芯片3中，使用具有与FOW4同等的热膨胀系数的树脂6，利用树脂6覆盖该半导体芯片3所凸出的部分的正面。此时，由于以FOW4与树脂6的分界部分成为连续状态的方式形成树脂6，所以能够防止从FOW4对半导体芯片3正面局部地施加应力。因此，能够抑制形成在半导体芯片3的电路的动作不良，提高半导体装置的可靠性。
此外，在半导体芯片3所凸出的部分形成树脂6的方法不限定于所述灌注，也可以使用其它方法形成。另外，所积层的半导体芯片3的数量、或相对于上下方的半导体芯片3的水平方向的偏移量或方向并不限定于所述一例。
对本发明的实施方式进行了说明，但本实施方式表示为一例，并不意在限定发明的范围。该新颖的实施方式能以其它多种方式实施，能在不脱离发明的主旨的范围内，进行各种省略、置换、变更。这些实施方式或其变化包含在发明的范围或主旨中，并且包含在权利要求书所记载的发明及其均等的范围内。
[符号的说明]
1 布线衬底
2、2a～2d 膜状粘接剂(DAF)
3、3a～3f 半导体芯片
4、4a、4b 膜状粘接剂(FOW)
5、5a～5f 导电性导线
6、6a、6b 树脂
7 密封树脂
8 分配器
100 半导体装置
CA3b 电路区域
WA、WA1、WA3a、WA3b 电极区域

Claims (5)

1.一种半导体装置，在布线衬底上积层多个背面贴附了膜状粘接剂的半导体芯片，利用导电性部件将所述布线衬底与多个所述半导体芯片连接，且具备：第1半导体芯片，是在背面贴附了能够供埋入所述导电性部件的所述膜状粘接剂即第1粘接剂的所述半导体芯片；
第2半导体芯片，是经由所述第1粘接剂与所述第1半导体芯片固着的所述半导体芯片；及
第3半导体芯片，是经由贴附在所述第2半导体芯片的背面的所述膜状粘接剂与所述第2半导体芯片固着的半导体芯片；
所述第2半导体芯片的正面包含由所述第1粘接剂覆盖的第1部分、及未由所述第1粘接剂覆盖的第2部分，且
所述半导体装置进而具备覆膜部，该覆膜部仅位于所述第2部分的上方，覆盖所述第2部分、及位于所述第2半导体芯片的正面上的所述第1粘接剂的侧端面，
所述第3半导体芯片的正面固着在所述第2半导体芯片的与所述第1部分对向的背面。
2.根据权利要求1所述的半导体装置，其中所述覆膜部由热硬化性树脂形成。
3.根据权利要求2所述的半导体装置，其中形成所述覆膜部的所述热硬化性树脂具有与所述第1粘接剂同等的热膨胀系数。
4.根据权利要求3所述的半导体装置，其中位于所述第2半导体芯片的正面上的所述第1粘接剂的侧端面与所述覆膜部的分界面连续地形成。
5.根据权利要求1至4中任一项所述的半导体装置，其进而具备密封树脂，该密封树脂将积层在所述布线衬底上的全部所述半导体芯片与所述导电性部件密封。
CN202010120717.5A 2019-09-12 2020-02-26 半导体装置 Active CN112490223B (zh)

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