TW202125766A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TW202125766A
TW202125766A TW109106679A TW109106679A TW202125766A TW 202125766 A TW202125766 A TW 202125766A TW 109106679 A TW109106679 A TW 109106679A TW 109106679 A TW109106679 A TW 109106679A TW 202125766 A TW202125766 A TW 202125766A
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semiconductor
semiconductor wafer
adhesive
semiconductor device
wafer
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TW109106679A
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English (en)
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荒井俊光
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日商鎧俠股份有限公司
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Publication of TW202125766A publication Critical patent/TW202125766A/zh

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Abstract

本發明之實施形態提供一種能夠提高可靠性之半導體裝置。 本發明之實施形態之半導體裝置係於配線基板1上積層複數個背面貼附有膜狀接著劑2、4之半導體晶片3，利用導電性導線5將配線基板1與複數個半導體晶片3連接，且具備貼附有FOW4a之半導體晶片3c、及經由FOW4a與半導體晶片3c固著之半導體晶片3b。半導體晶片3b之正面包含由FOW4a覆蓋之第1部分、及未由FOW4a覆蓋之第2部分。半導體裝置進而具備樹脂6a，該樹脂6a覆蓋第2部分、及位於半導體晶片3b之正面上之FOW4a之側端面。

Description

半導體裝置
本實施形態係關於一種半導體裝置。
已知有一種將複數個半導體晶片搭載於1個半導體封裝體內而成之MCP(Multi Chip Package，多晶片封裝體)。
本發明所欲解決之問題在於，本實施形態將提供一種能夠提高可靠性之半導體裝置。
本實施形態之半導體裝置係於配線基板上積層複數個背面貼附有膜狀接著劑之半導體晶片，利用導電性導線將上述配線基板與複數個上述半導體晶片連接，且具備：第1半導體晶片，其係於背面貼附有可供埋入上述導電性導線之上述膜狀接著劑即第1接著劑之上述半導體晶片；及第2半導體晶片，其係經由上述第1接著劑與上述第1半導體晶片固著之上述半導體晶片。
上述第2半導體晶片之正面包含由上述第1接著劑覆蓋之第1部分、及未由上述第1接著劑覆蓋之第2部分，且上述半導體裝置進而具備覆膜部，該覆膜部覆蓋上述第2部分、及位於上述第2半導體晶片之正面上之上述第1接著劑之側端面。
以下，參照附圖來說明實施形態。
圖1係表示本實施形態之半導體裝置之構造之剖視圖。於以下說明中，使用作為正交座標系統之一例之xyz座標系統。即，將與構成半導體裝置100之配線基板1之表面平行之平面設為xy平面，將與xy平面正交之方向設為z軸。又，x軸與y軸係設為xy平面內之正交之兩方向。再者，以下，為了方便說明，使用將z軸正方向側(基板1之第1表面1a側)設為上側，將z軸負方向側(基板1之第2表面1b側)設為下側之上下關係進行說明，但並不表示普遍之上下關係。
圖1中表示將半導體裝置100沿著xz平面切斷後之截面(以下表示為xz截面)之構造。再者，以下使用xz截面之構造進行說明，但yz截面等xz截面以外之截面中亦可存在相同之構造。
圖1所示之半導體裝置100具備配線基板1。配線基板1係例如於表面或內部設置有配線層(未圖示)之絕緣樹脂配線基板或陶瓷配線基板等。具體而言，例如利用使用了玻璃環氧樹脂之印刷配線基板等。或，亦可使用矽中介層或引線框架等。
配線基板1具備第1表面1a及第2表面1b。於第2表面1b，形成有BGA(Ball Grid Array，球柵陣列)封裝體用之外部端子(由焊料球等形成之突起狀端子)或LGA(Land grid array，焊盤柵格陣列)封裝體用之外部端子(藉由金屬鍍覆等形成之金屬焊盤)。再者，該等外部端子省略了圖示。
於配線基板之第1表面1a，設置有複數個半導體晶片3a～3f。以下，於無需區分半導體晶片3a～3f之情形時，簡單地表示為半導體晶片3。半導體晶片3a～3f中，於z方向上配置於最下側之半導體晶片為半導體晶片3a。於半導體晶片3a之上方，將半導體晶片3b、3c、3d、3e、3f依序朝z軸正方向積層配置。
半導體晶片3b相對於半導體晶片3a朝x軸正方向錯開特定距離(例如300 μm左右)地配置。又，半導體晶片3c相對於半導體晶片3b朝x軸負方向錯開特定距離(例如300 μm左右)地配置。進而，半導體晶片3d相對於半導體晶片3c朝x軸正方向錯開特定距離(例如300 μm左右)地配置。又，半導體晶片3e相對於半導體晶片3d朝x軸負方向錯開特定距離(例如300 μm左右)地配置。進而，半導體晶片3f相對於半導體晶片3e朝x軸正方向錯開特定距離(例如300 μm左右)地配置。即，各半導體晶片3之上表面之一部分以未由其他半導體晶片3覆蓋之方式配置。
再者，半導體晶片3可列舉例如NAND(Not AND，反及)快閃記憶體般之半導體晶片，但不限定於此，可使用任意之半導體晶片。又，於圖1中，記載了將6片半導體晶片3積層而成之構造，但亦可為3片以上之任意片數。
半導體晶片3於各背面整體貼附有膜狀接著劑2、4。膜狀接著劑2、4係使用了熱硬化樹脂(例如環氧系樹脂、聚醯亞胺系樹脂、丙烯酸系樹脂、或將該等混合而成之樹脂)之接著劑，厚度根據用途而異。一般而言，配線基板1與半導體晶片3接著或半導體晶片3彼此接著之用途中所使用之膜狀接著劑2具有5 μm～20 μm左右之厚度。供埋入用於將半導體晶片3與配線基板1之間電性連接之導電性導線5、或用於將半導體晶片3與其他半導體晶片3電性連接之導電性導線5，且將經積層之半導體晶片3彼此接著之用途中所使用之膜狀接著劑4具有40 μm～60 μm左右之厚度。以下說明中，將未埋入導電性導線5而使用之膜狀接著劑2表示為DAF(Die Attach Film，晶粒貼合膜)2。又，將能夠埋入導電性導線5之膜狀接著劑4表示為FOW(Film On Wire，膜覆線)4。再者，於圖1中，導電性導線5圖示為導電性導線5a～5f，但本說明書中，於無需區分導電性導線5a～5f之情形時，簡單地表示為導電性導線5。再者，導電性導線5為導電性構件之一例。亦可使用非導線狀之導電性構件，將半導體晶片3與配線基板1間或半導體晶片3與其他半導體晶片3之間電性連接。
半導體晶片3經由DAF2或FOW4與配線基板1或其他半導體晶片3固著。具體而言，半導體晶片3a經由DAF2a固著於配線基板1。又，半導體晶片3b經由DAF2b與半導體晶片3a固著。又，半導體晶片3c經由FOW4a與半導體晶片3b固著。又，半導體晶片3d經由DAF2c與半導體晶片3c固著。又，半導體晶片3e經由FOW4b與半導體晶片3d固著。進而，半導體晶片3f經由DAF2d與半導體晶片3e固著。
半導體晶片3a與配線基板1藉由導電性導線5a電性連接。又，半導體晶片3b與配線基板1藉由導電性導線5b電性連接。又，半導體晶片3c與配線基板1藉由導電性導線5c電性連接。又，半導體晶片3d與配線基板1藉由導電性導線5d電性連接。又，半導體晶片3e與配線基板1藉由導電性導線5e電性連接。進而，半導體晶片3f與配線基板1藉由導電性導線5f電性連接。
再者，半導體晶片3有時亦經由其他半導體晶片3與配線基板1電性連接。例如，一端與半導體晶片3b連接之導電性導線5b之另一端有時連接於配線基板1，亦有時連接於半導體晶片3a。此處，關於導電性導線5b之配置，使用圖2更具體地進行說明。
圖2係模式性地表示從上表面觀察到之本實施形態之半導體裝置之構造的俯視圖。圖2係表示將半導體晶片3a～3c積層之後，且將導電性導線5c與半導體晶片3c接合之前之俯視圖。於圖2中，以虛線之矩形區域示出半導體晶片3b，以粗線之矩形區域示出半導體晶片3c。再者，從上表面觀察之情形時，半導體晶片3a為與半導體晶片3c相同之形狀，且配置於相同位置。再者，於本案說明書中，所謂「相同」不僅包含嚴格相同，亦包含例如製造步驟中之偏差等。於配線基板1、半導體晶片3a及半導體晶片3b，沿著各區域中左端側之一邊，形成有包含用來連接導電性導線5之複數個電極之電極區域WA。即，於配線基板1形成有電極區域WA1，於半導體晶片3a形成有電極區域WA3a。又，於半導體晶片3b，形成有電極區域WA3b。
電極區域WA3a形成於較半導體晶片3b之左端更靠左側之區域，成為於電極區域WA3a之上部未覆蓋半導體晶片3b之構造。又，於半導體晶片3a之上部，從上表面觀察時於相同位置配置有半導體晶片3c。因此，成為於電極區域WA3a之上部覆蓋有半導體晶片3c之構造。由於具有此種構造，一端與半導體晶片3a之電極區域WA3a連接之導電性導線5a通過貼附於半導體晶片3c之背面之FOW4a之下表面與半導體晶片3a之上表面之間之空間，與配線基板1之電極區域WA1接合。
另一方面，電極區域WA3b與貼附於半導體晶片3c之背面之FOW4a之下表面相接(密接)地形成。因此，一端與半導體晶片3b之電極區域WA3b連接之導電性導線5b從貼附於半導體晶片3c之背面之FOW4a中通過，與半導體晶片3a之電極區域WA3a或配線基板1之電極區域WA1接合。
如此，半導體晶片3上之電極區域WA與貼附於其他半導體晶片3之背面之膜狀接著劑密接地形成之情形時，一端連接於該電極區域WA之導電性導線5必須從膜狀接著劑之中通過。即，以下表面與形成於半導體晶片3之電極區域WA密接之方式配置之膜狀接著劑由於必須將導電性導線5埋入(從膜狀接著劑之中通過)，故必須使用作為第1接著劑之FOW4而非DAF2。
於具有圖1之構造之半導體裝置100中，半導體晶片3b上之電極區域WA與貼附於半導體晶片3c之背面之膜狀接著劑4a密接地形成，又，半導體晶片3d上之電極區域WA與貼附於半導體晶片3e之背面之膜狀接著劑4b密接地形成。因此，一端連接於半導體晶片3b之導電性導線5b與一端連接於半導體晶片3d之導電性導線5d必須從與各半導體晶片3b、3d之正面密接之膜狀接著劑中通過。因此，貼附於半導體晶片3c與半導體晶片3e之背面之膜狀接著劑使用了FOW4，貼附於其他半導體晶片3a、3b、3d、3f之背面之膜狀接著劑使用了DAF2。
再者，貼附於半導體晶片3a、3b、3d、3f之背面之膜狀接著劑亦能使用FOW4。但是，鑒於對半導體裝置100之薄型化之要求不斷加強之現狀，較佳為使用膜厚較FOW4薄之DAF2。又，亦有因使用膜厚較厚之FOW4作為膜狀接著劑，而導致FOW4正下方之半導體晶片3產生翹曲之問題，故較佳為於無需埋入導電性導線5之部位使用DAF2。
圖3係說明由應力集中所致之半導體晶片之翹曲之剖視圖。圖3表示將半導體晶片3a～3c積層後之晶片右端附近之概略剖視圖。再者，於圖3中，表示未形成有樹脂6a之狀態。
一般而言，膜狀接著劑之膨脹量根據溫度而變化。即，膨脹量亦隨著溫度上升而變大，隨著溫度下降而變小。又，膜狀接著劑之體積越大，則因加熱、冷卻引起之體積變化越大。又，與構成半導體晶片3之矽之熱膨脹係數相比，膜狀接著劑之熱膨脹係數為1個數量級以上之較大之值。因此，於100度以上之高溫環境下，膜狀接著劑之膨脹量與矽之膨脹量產生差。
於半導體裝置100之製造步驟中，使半導體晶片3彼此固著時，為了使膜狀接著劑熱硬化而對半導體裝置100整體施加100度以上之熱處理。與熱膨脹係數相應地，膜狀接著劑於熱處理中膨脹，隨著溫度下降而收縮。與DAF2相比膜厚較厚且體積較大之FOW4因由膨脹、收縮引起之體積變化較大，故於FOW4a之端部正下方之半導體晶片3b之正面產生局部應力。因此，半導體晶片3b中從FOW4之右端突出之部分如圖3所示產生翹曲。於半導體晶片3b中，形成於產生了翹曲之部分之電路部分可能會發生動作不良，而導致半導體裝置之可靠性降低。
為了防止如上所述之半導體晶片3b之翹曲，如圖1所示，本實施形態之半導體裝置1以從作為第1半導體晶片之半導體晶片3c及作為第1接著劑之FOW4a之右側端面，連續地覆蓋至作為第2半導體晶片之半導體晶片3b之正面且較半導體晶片3c之右端更向右側突出之部分(半導體晶片3b中之第2部分)之方式，設置有作為覆膜部之樹脂6a。又，與半導體晶片3b同樣地，半導體晶片3d亦以從半導體晶片3e及FOW4b之右側面，連續地覆蓋至半導體晶片3d之正面且較半導體晶片3e之右端更向右側突出之部分之方式，設置有樹脂6b，以防止翹曲。
樹脂6a、6b係具有與FOW4同等之熱膨脹係數之熱硬化性樹脂。再者，於本案說明書中「同等」不僅包含嚴格相同，亦包含例如製造步驟中之偏差等，還包含為了獲得本發明之效果所需之範圍。此處，使用圖2進一步說明由樹脂6覆蓋之平面區域。於圖2中，以單點劃線之矩形區域表示半導體晶片3b中之電路區域CA3b(形成有半導體元件或配線等之區域)。考慮到從半導體晶圓切下半導體晶片之切割中之切下位置之偏移，通常於半導體晶片3b之周緣部，設置有未形成電路之切割線。例如，從半導體晶片3b之周緣起25 μm左右之區域中設置有切割線。即，於圖2中，從單點劃線所示之電路區域CA3b之外周至虛線所示之半導體晶片3b之外周之間成為切割線。
樹脂6a形成為覆蓋半導體晶片3b之正面且從FOW4a之端部即半導體晶片3c之端部突出之部分中之、至少設置於該部分之電路區域CA3b整體。再者，上文中已對形成於半導體晶片3b上之樹脂6а進行了敍述，形成於半導體晶片3d上之樹脂6b亦形成於相同區域。即，樹脂6b形成為覆蓋半導體晶片3d之正面且從FOW4b之端部即半導體晶片3e之端部突出之部分中之、至少設置於該部分之電路區域整體。
而且，於半導體裝置100，於配線基板1之第1表面1a上形成有密封樹脂7，以便覆蓋半導體晶片3、及導電性導線5之整體並將其等密封。
其次，使用圖4、圖5A～圖5J對上述半導體裝置100之製造方法進行說明。圖4係表示本實施形態之半導體裝置之製造步驟之一例的流程圖。又，圖5A～圖5J係表示半導體裝置之製造步驟中之截面構造之圖。
首先，使半導體晶片3a、3b依序固著於配線基板1之第1表面1a上，進行接合(參照S1、圖5A)。具體而言，首先，將背面貼附有DAF2a之半導體晶片3a配置於配線基板1之上表面1a。繼而，於半導體晶片3a上之特定位置，配置背面貼附有DAF2b之半導體晶片3b。對整體實施熱處理後使DAF2a、3b硬化，使配線基板1、半導體晶片3a、3b固著。最後，將導電性導線5a與半導體晶片3a及配線基板1接合並電性連接。又，使用導電性導線5b將半導體晶片3b與配線基板1、或半導體晶片3b與半導體晶片3a接合並電性連接。
隨後，於半導體晶片3b上配置背面貼附有FOW4a之半導體晶片3c(參照S2、圖5B)。此時，FOW4a為半硬化狀態。因此，FOW4a為黏度較低之狀態，故連接於半導體晶片3b之導電性導線5b之一部分埋入至FOW4a中。
繼而，對半導體晶片3b之正面中之從FOW4a之端部凸出並露出之部分，使用分配器8等從上方注封樹脂6a(參照S3、圖5C)。再者，樹脂6a較理想為具有與FOW4a同等之熱膨脹係數之樹脂。其次，使所注封之樹脂6a洩漏並擴散至半導體晶片3b之正面及半導體晶片3c與FOW4a之側面。隨後，實施加熱處理，使FOW4a與樹脂6a熱硬化(參照S4、圖5D)。藉由加熱處理，FOW4a與樹脂6a之分界部分成為連續狀態。再者，加熱後之樹脂6a形成為至少連續地覆蓋半導體晶片3b之正面中形成於未與FOW4a密接之部分之電路區域CA3b、及半導體晶片3c與FOW4a之側面中位於半導體晶片3b之正面上之部分。
如此，利用樹脂6a覆蓋半導體晶片3b正面之露出部分之電路區域，進而，連續地形成樹脂6a與FOW4a，藉此即便於之後之步驟中施加之加熱處理、或完成後之半導體裝置100於高溫下動作之情形時，亦能夠防止從FOW4a對半導體晶片3b之正面局部地施加應力。因此，能夠抑制形成於半導體晶片3b之電路之動作不良，提高半導體裝置之可靠性。
隨後，使半導體晶片3d固著於半導體晶片3c上，進行接合(參照S5、圖5E)。具體而言，首先，將背面貼附有DAF2c之半導體晶片3d配置於半導體晶片3c上之特定位置。對整體實施熱處理而使DAF2c硬化，使半導體晶片3c與3d固著。繼而，使用導電性導線5c將半導體晶片3c與配線基板1接合並電性連接。又，使用導電性導線5d將半導體晶片3d與配線基板1、或半導體晶片3d與半導體晶片3c接合並電性連接。
其次，於半導體晶片3d上配置背面貼附有FOW4b之半導體晶片3e(參照S6、圖5F)。此時，FOW4b為半硬化狀態。因此，FOW4b為黏度較低之狀態，故連接於半導體晶片3d之導電性導線5d之一部分埋入至FOW4b中。
繼而，對半導體晶片3d之正面中從FOW4b之端部凸出並露出之部分，使用分配器8等從上方注封樹脂6b(參照S7、圖5G)。再者，樹脂6b較理想為具有與FOW4b同等之熱膨脹係數之樹脂。其次，使所注封之樹脂6b洩漏並擴散至半導體晶片3d之正面、及半導體晶片3e與FOW4b之側面。隨後，實施加熱處理，使FOW4b與樹脂6b熱硬化(參照S8、圖5H)。藉由加熱處理，FOW4b與樹脂6b之分界部分成為連續狀態。再者，加熱後之樹脂6b形成為至少連續地覆蓋半導體晶片3d之正面中形成於未與FOW4b密接之部分之電路區域、及半導體晶片3e與FOW4b之側面中位於半導體晶片3d之正面上之部分。
如此，利用樹脂6b覆蓋半導體晶片3d正面之露出部分之電路區域，進而，連續地形成樹脂6b與FOW4b，藉此，即便於之後之步驟中施加之加熱處理、或完成後之半導體裝置100於低溫環境下或高溫環境下動作之情形時，亦能夠防止對半導體晶片3d之正面從FOW4b局部地施加應力。因此，能夠抑制形成於半導體晶片3d之電路之動作不良，提高半導體裝置之可靠性。
隨後，使半導體晶片3f固著於半導體晶片3e上，進行接合(參照S9、圖5I)。具體而言，首先，將背面貼附有DAF2d之半導體晶片3f配置於半導體晶片3e上之特定位置。對整體實施熱處理而使DAF2d硬化，使半導體晶片3e與3f固著。繼而，使用導電性導線5e將半導體晶片3e與配線基板1接合並電性連接。又，使用導電性導線5f將半導體晶片3f與配線基板1、或半導體晶片3f與半導體晶片3e接合並電性連接。
所有半導體晶片3均被固著，且經由導電性導線5與配線基板1電性連接後，最後利用密封樹脂7將經積層之半導體晶片3、及已接合之導電性導線5塑封(molding)(參照S10、圖5J)。於配線基板1之第2表面1b之特定位置，形成BGA封裝體用之外部端子(由焊料球等形成之突起狀端子)或LGA封裝體用之外部端子(藉由金屬鍍覆等形成之金屬焊盤)，半導體裝置100完成。
如上所述，根據本實施形態，關於複數個半導體晶片3經由如FOW4般之厚膜之膜狀接著劑積層而成之半導體裝置，具有從位於上下方之半導體晶片3所凸出之部分，且於經由FOW4與正上方之半導體晶片3接著之半導體晶片3中，使用具有與FOW4同等之熱膨脹係數之樹脂6，利用樹脂6覆蓋該半導體晶片3所凸出之部分之正面。此時，由於以FOW4與樹脂6之分界部分成為連續狀態之方式形成樹脂6，故能夠防止從FOW4對半導體晶片3正面局部地施加應力。因此，能夠抑制形成於半導體晶片3之電路之動作不良，提高半導體裝置之可靠性。
再者，於半導體晶片3所凸出之部分形成樹脂6之方法不限定於上述注封，亦可使用其他方法形成。又，所積層之半導體晶片3之數量、或相對於上下方之半導體晶片3之水平方向之偏移量或方向並不限定於上述一例。
對本發明之實施形態進行了說明，但本實施形態表示為一例，並不意於限定發明之範圍。該新穎之實施形態能以其他多種形態實施，能於不脫離發明之主旨之範圍內，進行各種省略、置換、變更。該等實施形態或其變化包含於發明之範圍或主旨中，並且包含於申請專利範圍所記載之發明及其均等之範圍內。
[相關申請] 本申請享有以日本專利申請2019-166233號(申請日：2019年9月12日)為基礎申請之優先權。本申請藉由參照該基礎申請而包含基礎申請之全部內容。
1:配線基板 1a:第1表面 1b:第2表面 2:膜狀接著劑(DAF) 2a:膜狀接著劑(DAF) 2b:膜狀接著劑(DAF) 2c:膜狀接著劑(DAF) 2d:膜狀接著劑(DAF) 3:半導體晶片 3a～3f:半導體晶片 4:膜狀接著劑(FOW) 4a:膜狀接著劑(FOW) 4b:膜狀接著劑(FOW) 5:導電性導線 5a～5f:導電性導線 6:樹脂 6a:樹脂 6b:樹脂 7:密封樹脂 8:分配器 100:半導體裝置 CA3b:電路區域 WA:電極區域 WA1:電極區域 WA3a:電極區域 WA3b:電極區域
圖1係表示本實施形態之半導體裝置之構造之剖視圖。 圖2係模式性地表示從上表面觀察到之本實施形態之半導體裝置之構造的俯視圖。 圖3係說明由應力集中所致之半導體晶片之翹曲之剖視圖。 圖4係表示本實施形態之半導體裝置之製造步驟之一例的流程圖。 圖5A係表示半導體裝置之製造步驟中之截面構造之圖。 圖5B係表示半導體裝置之製造步驟中之截面構造之圖。 圖5C係表示半導體裝置之製造步驟中之截面構造之圖。 圖5D係表示半導體裝置之製造步驟中之截面構造之圖。 圖5E係表示半導體裝置之製造步驟中之截面構造之圖。 圖5F係表示半導體裝置之製造步驟中之截面構造之圖。 圖5G係表示半導體裝置之製造步驟中之截面構造之圖。 圖5H係表示半導體裝置之製造步驟中之截面構造之圖。 圖5I係表示半導體裝置之製造步驟中之截面構造之圖。 圖5J係表示半導體裝置之製造步驟中之截面構造之圖。
1:配線基板
1a:第1表面
1b:第2表面
2a:膜狀接著劑(DAF)
2b:膜狀接著劑(DAF)
2c:膜狀接著劑(DAF)
2d:膜狀接著劑(DAF)
3a~3f:半導體晶片
4a:膜狀接著劑(FOW)
4b:膜狀接著劑(FOW)
5a~5f:導電性導線
6a:樹脂
6b:樹脂
7:密封樹脂
100:半導體裝置

Claims (6)

  1. 一種半導體裝置，其係於配線基板上積層複數個背面貼附有膜狀接著劑之半導體晶片，利用導電性構件將上述配線基板與複數個上述半導體晶片連接，且具備： 第1半導體晶片，其係於背面貼附有可供埋入上述導電性構件之上述膜狀接著劑即第1接著劑之上述半導體晶片；及 第2半導體晶片，其係經由上述第1接著劑與上述第1半導體晶片固著之上述半導體晶片； 上述第2半導體晶片之正面包含由上述第1接著劑覆蓋之第1部分、及未由上述第1接著劑覆蓋之第2部分，且 上述半導體裝置進而具備覆膜部，該覆膜部覆蓋上述第2部分、及位於上述第2半導體晶片之正面上之上述第1接著劑之側端面。
  2. 如請求項1之半導體裝置，其中上述覆膜部由熱硬化性樹脂形成。
  3. 如請求項2之半導體裝置，其中形成上述覆膜部之上述熱硬化性樹脂具有與上述第1接著劑同等之熱膨脹係數。
  4. 如請求項3之半導體裝置，其中位於上述第2半導體晶片之正面上之上述第1接著劑之側端面與上述覆膜部之分界面連續地形成。
  5. 如請求項1至4中任一項之半導體裝置，其進而具備第3半導體晶片，該第3半導體晶片係經由貼附於上述第2半導體晶片之背面之上述膜狀接著劑與上述第2半導體晶片固著之半導體晶片，上述第3半導體晶片之正面固著於上述第2半導體晶片之與上述第1部分對向之背面。
  6. 如請求項1至4中任一項之半導體裝置，其進而具備密封樹脂，該密封樹脂將積層於上述配線基板上之全部上述半導體晶片與上述導電性構件密封。
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