TWI750439B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI750439B
TWI750439B TW107147240A TW107147240A TWI750439B TW I750439 B TWI750439 B TW I750439B TW 107147240 A TW107147240 A TW 107147240A TW 107147240 A TW107147240 A TW 107147240A TW I750439 B TWI750439 B TW I750439B
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semiconductor device
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TW202008528A (zh
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佐野雄一
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日商東芝記憶體股份有限公司
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Abstract

實施形態提供一種具有抑制間隔晶片與塑模樹脂之間之剝離且能以低成本製造之封裝構造之半導體裝置及其製造方法。 實施形態之半導體裝置包括：基板；第1半導體晶片，其設置於基板上；第1接著材料，其設置於第1半導體晶片上；間隔晶片，其設置於第1接著材料上；第2接著材料，其設置於間隔晶片上；第2半導體晶片，其設置於第2接著材料上；以及樹脂材料，其被覆第1及第2半導體晶片、以及間隔晶片；且間隔晶片具有第1區域及第2區域，第1區域相較第2區域而言更粗糙化。

Description

半導體裝置及其製造方法
本實施形態係關於一種半導體裝置及其製造方法。
有於NAND(Not And，與非)型快閃記憶體等半導體裝置之封裝內，使用FOD(Film On Device，裝置上膜)技術積層記憶體晶片或控制器晶片等複數個半導體晶片之情形。於FOD技術中，當使上層之半導體晶片(上層晶片)小型化時，為了可將下層晶片埋入至接著膜內，有時使用間隔晶片。
然而，間隔晶片係使用無圖案之鏡面晶片，其表面為鏡面狀態。因此，與將半導體晶片密封之塑模樹脂之密接力較弱。因此，有於高溫多濕之環境下，於間隔晶片與塑模樹脂之界面發生剝離之虞。該情況使半導體裝置之可靠性降低。
又，想到於間隔晶片塗佈聚醯亞胺來提高與塑模樹脂之密接力。然而，聚醯亞胺之使用會使製造成本增大。
實施形態提供一種具有抑制間隔晶片與塑模樹脂之間之剝離且能以低成本製造之封裝構造之半導體裝置及其製造方法。
實施形態之半導體裝置包括：基板；第1半導體晶片，其設置於基板上；第1接著材料，其設置於第1半導體晶片上；間隔晶片，其設置於第1接著材料上；第2接著材料，其設置於間隔晶片上；第2半導體晶片，其設置於第2接著材料上；以及樹脂材料，其被覆第1及第2半導體晶片、以及間隔晶片；且間隔晶片具有第1區域及第2區域，第1區域相較第2區域而言更粗糙化。
以下，參照圖式對本發明之實施形態進行說明。本實施形態並非限定本發明者。於以下之實施形態中，基板之上下方向表示以設置有半導體晶片之面為上之情形時之相對方向，有時與按照重力加速度之上下方向不同。圖式係模式性或概念性者，各部分之比率等未必與實物相同。於說明書與圖式中，對與關於既有之圖式已於上文敍述過之要素相同之要素附上相同符號並適當省略詳細之說明。
(第1實施形態) 圖1係表示第1實施形態之半導體裝置1之構成之一例的剖視圖。圖2係表示第1實施形態之半導體裝置1之構成之一例的俯視圖。圖1係沿著圖2之A-A線之剖視圖。
本實施形態之半導體裝置1係面安裝型之半導體封裝，例如可為BGA(Ball Grid Array package，球柵陣列封裝)、MAP(Mold Array Package，塑模陣列封裝)或LGA(Land Grid Array Package，平面柵格陣列封裝)等。半導體裝置1亦可為例如NAND型快閃記憶體等半導體記憶裝置。
半導體裝置1包括基板10、接著材料20、控制器晶片30、接著材料40、間隔晶片50、接著材料60、記憶體晶片70、塑模樹脂80及金屬凸塊90。
基板10例如為將單層或複數層絕緣層(未圖示)與複數層配線層(未圖示)積層並一體化所得之多層配線基板。絕緣層例如使用玻璃環氧樹脂、玻璃-BT樹脂(雙馬來醯亞胺三嗪樹脂)等樹脂材料。配線層設置於基板10內或基板10之正面及背面，且電性連接於焊墊12、14。配線層例如使用銅等低電阻之導電性材料。基板10之平面形狀並無特別限定，可為大致長方形或者大致正方形。
於基板10之正面及背面，設置有阻焊劑(未圖示)。於背面之金屬凸塊90之形成區域未設置有阻焊劑，金屬凸塊90與自阻焊劑露出之配線層電性連接。藉此，金屬凸塊90作為外部連接端子與其他半導體裝置連接。金屬凸塊90例如使用焊料等導電性材料。
作為第1半導體晶片之控制器晶片30係利用接著材料(DAF(Die Attachment Film，晶片貼膜))20接著並固定於基板10之正面上。控制器晶片30係控制記憶體晶片70之半導體晶片，於半導體基板之正面設置有構成控制電路之半導體元件(例如電晶體等)。又，控制器晶片30具有連接於內部控制電路之焊墊32，且利用金屬導線35與基板10之焊墊12電性連接。控制器晶片30選擇進行資料之寫入或讀出之記憶體晶片70，或對所選擇之記憶體晶片70進行資料之寫入或讀出。再者，複數個控制器晶片30亦可配置於基板10上。
接著材料20設置於基板10與控制器晶片30之間，且將控制器晶片30接著於基板10。接著材料20例如使用包含熱固性樹脂之接著膜(DAF)。
間隔晶片50設置於接著材料40上，利用接著材料40以不與基板10及控制器晶片30接觸之方式，配置於基板10及控制器晶片30之上方。間隔晶片50係使用控制器晶片30或記憶體晶片70中所使用之半導體基板。例如，間隔晶片50係使用由矽晶圓形成之單晶矽。
間隔晶片50之正面中之供塑模樹脂80直接接觸之第1區域R1照射雷射光後粗糙化。因此，間隔晶片50之正面之第1區域R1經表面粗糙化加工成與其以外之第2區域R2相比較為粗糙(凹凸多或凹凸大)。又，當於大氣中利用雷射光對第1區域R1進行表面粗糙化加工時，間隔晶片50之第1區域R1氧化及/或碳化。因此，於間隔晶片50之正面之第1區域R1，例如形成有矽氧化物及/或矽碳化物。如此，間隔晶片50之正面之第1區域R1與第2區域R2相比更粗糙化，並且設置有矽氧化物及/或矽碳化物。以下，將如此經粗糙化之矽氧化物及/或矽碳化物層亦稱為加工層55。第1區域R1之加工層55之矽氧化物及/或矽碳化物之量或者加工層55之厚度較設置於第2區域R2之矽氧化物及/或矽碳化物之量多或者厚度厚。藉此，於第1區域R1中，間隔晶片50與塑模樹脂80之密接性變高，於間隔晶片50與塑模樹脂80之界面不易產生剝離。
於第2區域R2上，利用接著材料60接著有記憶體晶片70。如下所述，接著材料60例如包含熱固性樹脂，且可良好地密接於鏡面狀態之矽結晶。因此，間隔晶片50之第2區域R2未必需要利用雷射光進行表面粗糙化加工。
於間隔晶片50之正面之第1區域R1未經粗糙化而不具有加工層55之情形時，間隔晶片50之正面為鏡面狀態，且與塑模樹脂80之密接性較差。因此，於間隔晶片50之第1區域R1與塑模樹脂80之界面容易產生剝離。
與此相對，於本實施形態之間隔晶片50之第1區域R1中，在間隔晶片50之正面設置有加工層55。加工層55經表面粗糙化加工，由凹凸較多之(較大之)矽氧化物及/或矽碳化物形成。因此，於與塑模樹脂80之界面不易產生剝離，可提高半導體裝置1之可靠性。
作為第1接著材料之接著材料40設置於控制器晶片30與間隔晶片50之間及基板10與間隔晶片50之間，將間隔晶片50接著並固定於基板10及控制器晶片30上。並且，接著材料40被覆控制器晶片30及金屬導線35等並對其等予以保護。如此，第1實施形態之半導體裝置1具有FOD(Film On Device)構造。接著材料40例如使用包含熱固性樹脂之接著膜(DAF)。接著材料40例如使用環氧樹脂、苯酚樹脂、丙烯酸系樹脂及二氧化矽填料。接著材料40之厚度為5 μm～150 μm。
作為第2接著材料之接著材料60設置於間隔晶片50與記憶體晶片70之間，將記憶體晶片70接著於間隔晶片50。接著材料60例如使用包含熱固性樹脂之接著膜(DAF)。
作為第2半導體晶片之記憶體晶片70設置於接著材料60上，且利用接著材料60接著於間隔晶片50上。記憶體晶片70例如為具有NAND型快閃記憶體之半導體晶片，於半導體基板之正面上設置有平面型或立體型之記憶胞陣列。又，記憶體晶片70具有連接於內部電路之焊墊74，焊墊74利用金屬導線75與基板10之焊墊14電性連接。藉此，記憶體晶片可經由金屬導線75、35及基板10之內部配線與控制器晶片30電性連接，接受控制器晶片30之控制而動作。
於本實施形態中，複數個記憶體晶片70積層於間隔晶片50上。於此情形時，複數個記憶體晶片70分別利用接著材料60接著於位於其正下方之間隔晶片50或記憶體晶片70。
塑模樹脂80設置於基板10上，且被覆控制器晶片30、間隔晶片50、記憶體晶片70及金屬導線35、75。塑模樹脂80自半導體裝置1之外部保護控制器晶片30、間隔晶片50、記憶體晶片70及金屬導線35、75。
塑模樹脂80與間隔晶片50之第1區域R1直接接觸。第1區域R1經粗糙化，並且被氧化及/或碳化。因此，塑模樹脂80於第1區域R1中與間隔晶片50良好地密接，不易自間隔晶片50剝離。再者，間隔晶片50之側面未利用雷射光進行表面粗糙化加工，但藉由切割而切斷，故而於某種程度上變粗。因此，認為間隔晶片50之側面與塑模樹脂80之密接性並不會成為問題。
如上所述，根據本實施形態，塑模樹脂80直接接觸之間隔晶片50之第1區域R1藉由雷射加工而粗糙化，且氧化或碳化。藉此，可提高間隔晶片50與塑模樹脂80之密接性，且抑制塑模樹脂80自間隔晶片50剝離。
其次，說明本實施形態之半導體裝置1之製造方法。
圖3(A)～圖4(B)係表示第1實施形態之半導體裝置1之製造方法之一例的剖視圖。首先，如圖3(A)所示，於基板10上搭載控制器晶片30。控制器晶片30利用接著材料20接著於基板10上。接著材料20預先貼附於控制器晶片30之背面，藉由將控制器晶片30晶片接合於基板10上而將控制器晶片30接著於基板10上。為了將控制器晶片30接著於基板10上，接著材料20於晶片接合時被加熱。
其次，如圖3(B)所示，利用金屬導線35將控制器晶片30之焊墊32與基板10之焊墊12之間接合。其次，將間隔晶片50設置於控制器晶片30之上方。此時，於間隔晶片50之背面預先貼附有接著材料40，於將間隔晶片50晶片接合於基板10上時，接著材料40將間隔晶片50接著於基板10上。為了將間隔晶片50接著於基板10上，接著材料40於晶片接合時被加熱。此時，間隔晶片50之正面成為光滑之鏡面狀態。
其次，如圖4(A)所示，對間隔晶片50之第1區域R1照射雷射光，使該間隔晶片50之第1區域R1粗糙化。於本實施形態中，第1區域R1係沿著未搭載記憶體晶片70之間隔晶片50之外邊之區域。雷射裝置99對第1區域R1照射雷射光，於第1區域R1之間隔晶片50之正面形成凹凸，形成包含氧化物及/或碳化物之加工層55。於間隔晶片50為矽基板之情形時，加工層55包含矽氧化物及/或矽碳化物。於第2區域R2，未形成加工層55，第2區域R2之間隔晶片50保持鏡面狀態。
其次，如圖4(B)所示，於間隔晶片50上搭載記憶體晶片70。記憶體晶片70係利用接著材料60而接著於間隔晶片50上。進而，其他記憶體晶片70係利用接著材料60而接著於位於其正下方之記憶體晶片70上。如此，複數個記憶體晶片70積層於間隔晶片50上。接著材料60預先貼附於各記憶體晶片70之背面，藉由將記憶體晶片70晶片接合於間隔晶片50或其他記憶體晶片70上而將記憶體晶片70接著於間隔晶片50或其他記憶體晶片70上。為了將記憶體晶片70接著於基板10上，接著材料60於晶片接合時被加熱。
其次，利用金屬導線75將記憶體晶片70之焊墊74與基板10之焊墊14之間接合。
其次，利用塑模樹脂80被覆控制器晶片30、記憶體晶片70、間隔晶片50及金屬導線35、75。藉此，獲得圖1所示之構造。此時，至少塑模樹脂80與間隔晶片50之接觸區域為第1區域R1。
根據本實施形態，塑模樹脂80直接接觸之間隔晶片50之第1區域R1藉由雷射加工而粗糙化，且氧化或碳化。藉此，可提高間隔晶片50與塑模樹脂80之密接性，且抑制塑模樹脂80自間隔晶片50剝離。因此，半導體裝置1之可靠性提高。
(第2實施形態) 圖5係表示第2實施形態之半導體裝置2之構成之一例的剖視圖。根據第2實施形態，間隔晶片50具有搭載記憶體晶片70之第1面F1、及與第1面F1為相反側之第2面F2。加工層55設置於整個第1面F1，第1區域R1成為整個第1面(上表面)F1。無加工層55之第2區域R2成為與第1面F1為相反側之第2面(背面)F2。因此，加工層55不僅設置於塑模樹脂80與間隔晶片50之間之界面，亦設置於接著材料60與間隔晶片50之間之界面。即，加工層55亦設置於記憶體晶片70之下。第2實施形態之其他構成可與第1實施形態之對應之構成相同。
又，於半導體裝置2之製造方法中，只要於圖4(A)所示之步驟中，雷射裝置99對間隔晶片50之第1面F1之整個面照射雷射光便可。藉此，於間隔晶片50之第1面F1之整個面形成加工層55。半導體裝置2之製造方法之其他步驟可與第1實施形態之半導體裝置1之對應之步驟相同。藉此，第2實施形態可獲得與第1實施形態相同之效果。
(第3實施形態) 圖6係表示第3實施形態之半導體裝置3之構成之一例的剖視圖。圖7係表示第3實施形態之半導體裝置3之構成之一例的俯視圖。根據第3實施形態，記憶體晶片70_1、70_2於相對於間隔晶片50之第1面F1大致平行之方向上並列地配置。位於鄰接之記憶體晶片70_1、70_2間之間隔晶片50之正面區域成為第1區域R1。於第3實施形態中，如圖7所示，第1區域R1位於間隔晶片50之中間區域，且與塑模樹脂80直接接觸。於間隔晶片50之第1區域R1，設置有加工層55。第3實施形態之其他構成可與第1實施形態之對應之構成相同。
又，於半導體裝置3之製造方法中，雷射裝置99只要對位於間隔晶片50之中間之第1區域R1照射雷射光便可。半導體裝置3之製造方法之其他步驟可與第1實施形態之半導體裝置1之對應之步驟相同。藉此，第3實施形態可獲得與第1實施形態相同之效果。
於圖6中，記憶體晶片70_1、70_2分別以單層記憶體晶片之形式設置於間隔晶片50上。然而，記憶體晶片70_1、70_2亦可為分別積層有複數個記憶體晶片之積層體。第3實施形態之其他構成可與第1實施形態之對應之構成相同。藉此，第3實施形態可獲得與第1實施形態相同之效果。
又，於第3實施形態中，加工層55亦可與第2實施形態同樣地，設置於整個第1面F1。藉此，第3實施形態可獲得與第2實施形態相同之效果。
對本發明之若干實施形態進行了說明，但該等實施形態係作為示例而提出者，並不意圖限定發明之範圍。該等實施形態能以其他多種形態實施，可於不脫離發明主旨之範圍內進行各種省略、置換、變更。該等實施形態或其變化包含於發明之範圍或主旨中，並且包含於申請專利範圍中所記載之發明及其均等之範圍內。
[相關申請] 本申請享有以日本專利申請2018-148775號(申請日：2018年8月7日)為基礎申請之優先權。本申請藉由參照該基礎申請而包含基礎申請之全部內容。
1‧‧‧半導體裝置 2‧‧‧半導體裝置 3‧‧‧半導體裝置 10‧‧‧基板 12‧‧‧焊墊 14‧‧‧焊墊 20‧‧‧接著材料 30‧‧‧控制器晶片 32‧‧‧焊墊 35‧‧‧金屬導線 40‧‧‧接著材料 50‧‧‧間隔晶片 55‧‧‧加工層 60‧‧‧接著材料 70‧‧‧記憶體晶片 70_1‧‧‧記憶體晶片 70_2‧‧‧記憶體晶片 74‧‧‧焊墊 75‧‧‧金屬導線 80‧‧‧塑模樹脂 90‧‧‧金屬凸塊 99‧‧‧雷射裝置 F1‧‧‧第1面(上表面) F2‧‧‧第2面(背面) R1‧‧‧第1區域 R2‧‧‧第2區域
圖1係表示第1實施形態之半導體裝置之構成之一例的剖視圖。 圖2係表示第1實施形態之半導體裝置之構成之一例的俯視圖。 圖3(A)～圖4(B)係表示第1實施形態之半導體裝置之製造方法之一例的剖視圖。 圖5係表示第2實施形態之半導體裝置之構成之一例的剖視圖。 圖6係表示第3實施形態之半導體裝置之構成之一例的剖視圖。 圖7係表示第3實施形態之半導體裝置之構成之一例的俯視圖。
1‧‧‧半導體裝置
10‧‧‧基板
12‧‧‧焊墊
14‧‧‧焊墊
20‧‧‧接著材料
30‧‧‧控制器晶片
32‧‧‧焊墊
35‧‧‧金屬導線
40‧‧‧接著材料
50‧‧‧間隔晶片
55‧‧‧加工層
60‧‧‧接著材料
70‧‧‧記憶體晶片
74‧‧‧焊墊
75‧‧‧金屬導線
80‧‧‧塑模樹脂
90‧‧‧金屬凸塊
R1‧‧‧第1區域
R2‧‧‧第2區域

Claims (13)

  1. 一種半導體裝置，其包括：基板；第1半導體晶片，其設置於上述基板上；第1接著材料，其設置於上述第1半導體晶片上；矽之間隔晶片，其設置於上述第1接著材料上；第2接著材料，其設置於上述間隔晶片上；第2半導體晶片，其設置於上述第2接著材料上；及樹脂材料，其被覆上述第1半導體晶片及上述第2半導體晶片、以及上述間隔晶片；且上述間隔晶片具有第1區域及第2區域，上述第1區域與上述第2區域相比更粗糙化；上述間隔晶片之材料之氧化物或碳化物以每單位面積之比計，於上述第1區域中較上述第2區域中存在得多。
  2. 如請求項1之半導體裝置，其中上述間隔晶片未形成圖案。
  3. 如請求項1之半導體裝置，其中上述間隔晶片具有供搭載上述第2半導體晶片之第1面、及與上述第1面為相反側之第2面，上述第1區域包含上述第1面， 上述第2區域包含上述第2面。
  4. 如請求項1之半導體裝置，其中上述第1區域係上述樹脂材料與上述間隔晶片接觸之部分。
  5. 如請求項3之半導體裝置，其中上述第1區域包含上述間隔晶片之側面。
  6. 如請求項1之半導體裝置，其中上述第2半導體晶片係記憶體晶片，上述第1半導體晶片係控制上述記憶體晶片之控制器晶片。
  7. 如請求項1之半導體裝置，其中上述第1接著材料自上方觀察時，覆蓋上述第1半導體晶片之上表面的全部。
  8. 如請求項7之半導體裝置，其中上述間隔晶片自上方觀察時，覆蓋上述第1半導體晶片之上表面的全部。
  9. 一種半導體裝置之製造方法，其包括如下步驟：於基板上搭載第1半導體晶片；於上述第1半導體晶片上設置第1接著材料；於上述第1接著材料之上設置矽之間隔晶片；對上述間隔晶片照射雷射，使該間隔晶片之第1區域粗糙化，且以未粗糙化之部分作為第2區域； 於上述間隔晶片上搭載第2半導體晶片；及利用樹脂材料被覆上述第1半導體晶片及上述第2半導體晶片、以及上述間隔晶片；且至少上述樹脂材料與上述間隔晶片之接觸區域為上述第1區域；上述間隔晶片之材料之氧化物或碳化物以每單位面積之比計，於上述第1區域中較上述第2區域中存在得多。
  10. 如請求項9之半導體裝置之製造方法，其中上述間隔晶片未形成圖案。
  11. 如請求項9之半導體裝置之製造方法，其中於上述第1區域，藉由雷射照射而形成上述間隔晶片之材料之氧化物或碳化物。
  12. 如請求項9至11中任一項之半導體裝置之製造方法，其中上述間隔晶片藉由刀片切割而切斷。
  13. 如請求項9至11中任一項之半導體裝置之製造方法，其中上述第1接著材料自上方觀察時，覆蓋上述第1半導體晶片之上表面的全部；上述間隔晶片自上方觀察時，覆蓋上述第1半導體晶片之上表面的全部。
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