TW202203417A - 半導體裝置及半導體裝置的製造方法 - Google Patents

半導體裝置及半導體裝置的製造方法 Download PDF

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TW202203417A
TW202203417A TW109146143A TW109146143A TW202203417A TW 202203417 A TW202203417 A TW 202203417A TW 109146143 A TW109146143 A TW 109146143A TW 109146143 A TW109146143 A TW 109146143A TW 202203417 A TW202203417 A TW 202203417A
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semiconductor wafer
resin layer
semiconductor
wiring board
semiconductor device
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TW109146143A
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TWI777337B (zh
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丹羽恵一
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日商鎧俠股份有限公司
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Abstract

本實施形態的半導體裝置，係具備：配線基板；第1半導體晶片；樹脂層；和第2半導體晶片。第1半導體晶片，係具有第1表面和該第1表面之相反側的第2表面，並且在第1表面側經由連接凸塊連接到配線基板。樹脂層，係覆蓋第1半導體晶片與配線基板之間的連接凸塊，且設置成為在第1半導體晶片的周圍其上表面與第1半導體晶片的第2表面大致平行。第2半導體晶片，係具有第3表面和該第3表面之相反側的第4表面，並且在第3表面側上經由黏著層黏著在第1半導體晶片的第2表面及樹脂層之上表面。當從前述第2半導體晶片的第4表面之上方觀察時，樹脂層之上表面從第2半導體晶片的外邊緣的至少一部分向外側突出。

Description

半導體裝置及半導體裝置的製造方法
本實施形態關於半導體裝置及半導體裝置的製造方法。 關連申請的引用 本申請主張基於2020年07月6日申請在先的日本專利申請第2020-116296號的優先權的利益，享受該利益，並且此處藉由引用而包含該內容全體。
在半導體裝置的封裝結構中，已知有將多個記憶體晶片層疊在與基板覆晶(Flip Chip)連接的控制器晶片的上方的結構。例如已知有在控制器晶片的周圍設置間隔晶片(spacer chip)，利用控制器晶片及間隔晶片來支撐記憶體晶片的間隔結構。
但是，由於使用間隔晶片導致組裝成本變高，並且步驟數增加。此外，難以對齊控制器晶片與間隔晶片之間的高度，如果產生台階，最下層的記憶體晶片的潤濕性有可能變差。此外，隧道部的鑄模填充性有可能變差。
提供一種能夠不使用間隔晶片，而更適當地支撐半導體晶片的的半導體裝置及半導體裝置的製造方法。
本實施形態的半導體裝置，係具備：配線基板；第1半導體晶片；樹脂層；及第2半導體晶片。第1半導體晶片，係具有第1表面和該第1表面之相反側的第2表面，且在第1表面上具有連接凸塊的第1半導體晶片，並且在第1表面側經由連接凸塊連接到配線基板。樹脂層，係覆蓋第1半導體晶片與配線基板之間的連接凸塊，且設置成為在第1半導體晶片的周圍其上表面與第1半導體晶片的第2表面大致平行。第2半導體晶片，係具有第3表面和該第3表面之相反側的第4表面，且在第3表面具有黏著層的第2半導體晶片，並且在第3表面側上經由黏著層黏著在第1半導體晶片的第2表面及樹脂層的上表面。當從前述第2半導體晶片的第4表面的上方觀察時，樹脂層的上表面從第2半導體晶片的外邊緣的至少一部分向外側突出。
依據上述構成，可以提供不使用間隔晶片，而更適當地支撐半導體晶片的半導體裝置及半導體裝置的製造方法。
以下，參照圖面說明本發明的實施形態。本實施形態並非用來限定本發明。以下的實施形態中，配線基板的上下方向係表示以搭載半導體晶片的一面為上方之情況下的相對方向，有可能存在與依循重力加速度的上下方向不同的情況。圖面為示意性或概念性示出者，各部分的比率等，未必一定與實際者相同。說明書與圖面中，針對和已出現的圖面中記載者為同樣的要素標記標記為相同的符號並適當地省略詳細的說明。此外，在以下的記載中，言及半導體晶片或樹脂層的中心位置的情況下，中心位置可以是當假設該半導體晶片或樹脂層由均勻的材料製成，而從上方觀察時的輪廓獲得的重心位置。
(第1實施形態) 圖1係表示第1實施形態的半導體裝置1的結構例的截面圖。半導體裝置1具備配線基板10、半導體晶片20、30～33、黏著層40～43、金屬材料70、樹脂層80、接合導線90、和密封樹脂91。半導體裝置1例如為NAND型快閃記憶體的封裝。
配線基板10可以是包含配線層11和絕緣層15的印刷基板或中介層。配線層11使用例如銅、鎳或彼等的合金等之低電阻金屬。絕緣層15使用例如玻璃環氧樹脂等之絕緣性材料。圖中，僅在絕緣層15的表面和背面設置有配線層11。但是，配線基板10亦可以是具有將多個配線層11和多個絕緣層15層疊而構成的多層配線結構。配線基板10例如如中介層這樣地具有貫穿其表面和背面的貫穿電極12亦可。
在配線基板10的表面設置有設置於配線層11上的阻焊層14。阻焊層14係為了保護配線層11免受金屬材料70之影響並抑制短線不良的絕緣層。在阻焊層14設置有開口部OP，配線層11的一部分及絕緣層15從開口部OP露出。
在配線基板10的背面亦設置有設置於配線層11上的阻焊層14。在從阻焊層14露出的配線層11上設置金屬凸塊13。金屬凸塊13係為了將未圖示的其他元件和配線基板10進行電性連接而設置。
半導體晶片20設置在配線基板10的表面側。半導體晶片20例如為控制記憶體晶片的控制器晶片。在半導體晶片20的面向配線基板10的一面上設置有未圖示的半導體元件。半導體元件例如可以是構成控制器的CMOS (Complementary Metal Oxide Semiconductor)回路。在半導體晶片20的背面設置有與半導體元件電性連接的電極柱21。電極柱21可以使用例如銅、鎳或彼等的合金等之低電阻金屬材料。
作為連接凸塊的電極柱21被插入配線基板10的開口部OP中。在電極柱21的周圍配置有金屬材料70。電極柱21經由金屬材料70與從開口部OP露出的配線層11電性連接。金屬材料70使用例如焊錫、銀、銅等之低電阻金屬材料。金屬材料70例如在開口部OP內覆蓋配線基板10的配線層11的一部分，並且亦覆蓋半導體晶片20的電極柱21的側面的一部分。藉此，金屬材料70將半導體晶片20的電極柱21與配線基板10的配線層11予以電性連接。
更詳細言之，半導體晶片20具有表面20a和該表面20a之相反側的表面20b，且在表面20a具有電極柱21。此外，半導體晶片20經由表面20a側中的電極柱21而與配線基板10連接。
在半導體晶片20的周圍以及半導體晶片20與配線基板10之間設置有樹脂層(填料)80。樹脂層80例如是使NCP(Non Conductive Past)硬化而成者，覆蓋並保護半導體晶片20的周圍。
更詳細言之，樹脂層80覆蓋半導體晶片20與配線基板10之間的電極柱21。此外，樹脂層80在半導體晶片20的周圍以上表面S與半導體晶片20的表面20b呈大致平行的方式設置。如圖1所示，樹脂層80具有大致梯形之截面形狀。亦即，在樹脂層80的外周端部設置有梯度。因此，樹脂層80的下部之面積大於上表面S之面積。樹脂層80的上方係圖1的紙面上方。樹脂層80的下方係圖1的紙面下方。
在半導體晶片20之上透過黏著層40黏著有半導體晶片30。半導體晶片30例如是包含NAND型快閃記憶體的記憶體晶片。半導體晶片30在其表面具有半導體元件(未圖示)。半導體元件例如可以是記憶單元陣列及其周邊電路(CMOS電路)。記憶單元陣列可以是將多個記憶單元三維配置的立體型記憶單元陣列。此外，在半導體晶片30上透過黏著層41黏著有半導體晶片31。在半導體晶片31上透過黏著層42黏著有半導體晶片32。在半導體晶片32上透過黏著層43黏著有半導體晶片33。和半導體晶片30同樣，半導體晶片31～33例如是包含NAND型快閃記憶體的記憶體晶片。半導體晶片30～33可以是相同的記憶體晶片。圖中，除了作為控制器晶片之半導體晶片20以外，層疊有4個作為記憶體晶片之半導體晶片30～33。但是，半導體晶片的層疊數可以是3個以下或5個以上。
更詳細言之，半導體晶片30，表面30a和該表面30a之相反側的表面30b，在表面30a具有黏著層40。此外，半導體晶片30係在表面30a側透過黏著層40黏著於半導體晶片20的表面20b及樹脂層80之上表面S。
此外，樹脂層80以支撐半導體晶片30的方式被設置。因此，在半導體晶片30與配線基板10之間不存在間隔件。樹脂層80不僅設置在半導體晶片20的周邊，而是設置在更寬廣的面積。在圖1所示例中，樹脂層80的外周端部位於半導體晶片30的外側與配線層11(焊墊10p)之間。藉此，當接合導線90連接於半導體晶片30的焊墊(參照圖2所示焊墊30p)時，能夠適當地支撐半導體晶片30。藉由樹脂層80支撐半導體晶片30，因此支撐半導體晶片30用的間隔件成為不必要。此外，在圖1所示例中，半導體晶片30的下方全部被樹脂層80填充。但是，不限定於此，只要在能夠支撐半導體晶片30的範圍內則可以縮窄樹脂層80的幅度。在該情況下，在半導體晶片30與配線基板10之間，在樹脂層80以外填充密封樹脂91。
接合導線90連接到配線基板10、半導體晶片30～33之任意之焊墊。為了便於以接合導線90連接，因此半導體晶片30～33層疊為偏移焊墊之量。此外，由於半導體晶片20實施基於電極柱21的覆晶連接，因此不實施導線接合。但是，除了電極柱21的連接以外，半導體晶片20亦可以實施導線接合。
此外，密封樹脂91對半導體晶片20、30～33、間隔晶片50、樹脂層80、接合導線90等實施密封。藉此，半導體裝置1構成為在配線基板10上層疊有多個半導體晶片20、30～33的1個半導體封裝。
圖2係表示圖1的配線基板10、半導體晶片20、30及樹脂層80的位置關係之一例的平面圖。圖2係從半導體晶片30的第2表面之上方觀察到的圖。此外，從圖2之A-A線觀察到的截面圖係對應於圖1。
20o表示半導體晶片20的外邊緣。30o表示半導體晶片30的外邊緣。10p表示設置在配線基板10的焊墊。30p表示設置在半導體晶片30的表面30b的焊墊。30s1表示半導體晶片30的邊之中作為設置焊墊30p的邊。圖2所示例中，邊30s1表示半導體晶片30的長邊。30s2表示半導體晶片30的邊之中未設置有焊墊30p的邊。圖2所示例中，邊30s1係表示半導體晶片30的短邊。
L1表示邊30s1與焊墊10p之間之距離。L2表示邊30s2與上表面S之外邊緣之間之距離。
樹脂層80之上表面S比半導體晶片20的外邊緣20o寬廣。藉此，樹脂層80適當地包圍並保護半導體晶片20。
從半導體晶片30的表面30b之上方觀察時，樹脂層80之上表面S從半導體晶片30的外邊緣30o之至少一部分更向外側突出。亦即，樹脂層80不僅設置在半導體晶片20的周邊，而是設置在更寬廣的面積。此外，樹脂層80之一部分設置成為超出外邊緣30o。
此外，從半導體晶片30的表面30b之上方觀察時，樹脂層80之上表面S從設置在半導體晶片30的表面30b的焊墊30p側之外邊緣30o更向外側突出。圖2所示例中，焊墊30p沿著半導體晶片30的邊30s1而配置。亦即，樹脂層80之上表面S比起邊30s1更向外側突出。
此外，樹脂層80之上表面S可以是位於焊墊30p側之外邊緣30o以外之外邊緣30o之內側。圖2所示例中，樹脂層80的下部及上表面S位在邊30s2之內側並未從邊30s2突出。亦即，取決於方向，樹脂層80被收納於外邊緣30o之內側亦可。此係因為由於封裝尺寸之規格，封裝尺寸或樹脂層80的寬度會受到製品等之限制。
此外，樹脂層80設置在直至焊墊10p之前部為止的範圍，該焊墊10p可以經由接合導線90連接到被該樹脂層80之上表面S支撐的半導體晶片30的表面30b上所設置的焊墊30p，而且，該焊墊10p設置在配線基板10上並且可與接合導線90連接。圖2所示例中，從外邊緣30o(邊30s1)之外側突出的樹脂層80的下部的位置不超過L1。因此，樹脂層80不接觸焊墊10p。假設，樹脂層80接觸焊墊10p時，則難以將接合導線90連接到焊墊10p。此外，圖2所示例中，即使樹脂層80的上表面S在邊30s2之內側時，因為L2較短，因此半導體晶片Ｓ1的大部分可以被上表面S支撐。因此，導線接合時樹脂層80可以支撐半導體晶片30。假設，L2變長時，導線接合時半導體晶片30會變形，有可能無法連接到接合導線90。L2例如焊墊30p是大約50μm平方的情況下，L2大約200μm以下為較佳。因此，藉由上述之位置關係，樹脂層80在導線接合時可以支撐半導體晶片30，並且，配置成為不接觸焊墊10p。此外，L2之上限距離例如受到焊墊30p之配置等而有可能變化。例如焊墊30p僅設置在邊30s1的中央部附近之情況下，L2之上限距離變長。因此，該情況下的樹脂層80即使L2變長亦可以支撐半導體晶片30。
此外，圖2所示例中，在圖2之紙面下方，設置有與半導體晶片32、33連接用的焊墊10p。在圖2之紙面下方樹脂層80之上表面S亦比外邊緣30o更向外側突出。
接著，對本實施形態的半導體裝置1的製造方法進行說明。
圖3～圖12係表示第1實施形態的半導體裝置1的製造方法之一例的圖。
首先，在半導體晶圓W形成半導體元件。圖3係表示形成有半導體元件的半導體晶圓W之斜視圖。在半導體晶圓W上形成半導體元件，聚醯亞胺PI覆蓋半導體元件。半導體晶圓W，後述之切割步驟中被分割的多個半導體晶片20(或30～33)。
接著，如圖4所示，在聚醯亞胺PI上黏貼保護帶TP1。接著，如圖5所示，在保護帶TP1朝下的狀態下，利用研磨機G研磨半導體晶圓W之背面。
將保護帶TP1剝離之後，如圖6所示，將半導體晶圓W之背面黏貼到在晶圓環WR內拉伸的可撓性之樹脂帶TP2上。接著，如圖7所示，使用雷射振盪器LG沿著半導體晶圓W的表面或背面之切割線照射雷射光。藉此，在切割線形成溝(凹槽)。
接著，如圖8所示，使用切割刀片DB沿著切割線之溝切斷半導體晶圓W。藉此，將半導體晶圓W切割為半導體晶片20(或30～33)。從樹脂帶TP2拾取被分割的半導體晶片20(或30～33)以便安裝到配線基板10。
另一方面，在配線基板10中形成有絕緣層15、配線層11、貫穿電極12、和阻焊層14。接著，使用形成在阻焊層14上的遮罩構件，在阻焊層14形成開口部OP。此時，開口部OP形成為使配線層11及其周邊之絕緣層15露出。
接著，如圖9所示，在配線基板10上塗布樹脂層80的材料80a。如使用圖2之說明般，以使樹脂層80能夠支撐半導體晶片20的方式塗布足夠之量之材料80a。
接著，如圖10所示，拾取如圖8所示步驟中形成的半導體晶片20，利用安裝治具MT使半導體晶片20的表面20a面對配線基板10。安裝治具MT，係具有吸附孔(未圖示)，並透過同樣開設有吸附孔的薄膜F將半導體晶片20進行吸附。當藉由安裝治具MT擠壓材料80a時，薄膜F用來抑制材料80a向上爬並與安裝治具MT接觸。假設材料80a進入安裝治具MT之吸附孔時，安裝治具MT變為無法使用。亦即，薄膜F保護安裝治具MT。此外，安裝治具MT中的與表面20b對向之表面之尺寸充分大於半導體晶片20的尺寸為較佳。
接著，如圖11所示，藉由安裝治具MT擠壓半導體晶片20及材料80a。藉由擠壓使材料80a向圖11的紙面左右方向擴展。因此，材料80a可以填充到安裝治具MT之端部。安裝治具MT中的面對表面20b之表面大致平坦，因此上表面S亦大致平坦。此外例如藉由熱壓接進行覆晶連接。藉此，半導體晶片20連接到配線基板10。
雖未圖示，接著，進行樹脂層80的硬化處理及電漿處理。藉由電漿處理提升半導體晶片20的表面20b與黏著層40之密接性。此外，樹脂層80會因硬化而收縮。因此，上表面S與表面20b可能不總是精確地平行。但是，上表面S與表面20b之差足夠小，並且藉由黏著層40抑制對半導體晶片20的影響。
亦即，使半導體晶片20的表面20a與配線基板10相對以便在樹脂層80內使電極柱21連接到配線基板10，並且使樹脂層80的上表面S與半導體晶片20的表面20b呈大致平行的方式實施樹脂層80的硬化。此外，在半導體晶片20的外周端部與樹脂層80之境界部B處，樹脂層80之上表面S與半導體晶片20的表面20b呈大致平行。此係因為材料80a被具有大致平坦的下表面的安裝治具MT擠壓、填充而在半導體晶片20的外周端部處與薄膜F接觸。
接著，如圖12所示，拾取如圖8所示步驟中形成的半導體晶片30，將半導體晶片30黏附到半導體晶片20及樹脂層80。亦即，使半導體晶片30的表面30a透過黏著層40黏附到半導體晶片20的表面20b及樹脂層80之上表面S。
之後，進行半導體晶片31～33之黏著、接合導線90的連接以及藉由密封樹脂91對半導體晶片20、30～33之密封。
如以上這樣地，依據第1實施形態，在半導體晶片20的周圍樹脂層80以其上表面S與半導體晶片20的表面20b呈大致平行的方式設置。此外，從半導體晶片30的表面30b之上方觀察時，樹脂層80之上表面S從半導體晶片30的外邊緣30o之至少一部分向外側突出。例如設置具有上表面S的樹脂層80，且該上表面S的面積能夠與半導體晶片20的面積相比。藉此，樹脂層80能夠適當地支撐半導體晶片20。因此，能夠不使用間隔晶片，而更適當地支撐半導體晶片30。不存在間隔晶片，因此可以抑制例如步驟數之增加。
此外，已知有不使用間隔晶片，利用厚的DAF(晶片黏結薄膜(Die Attach Film))來覆蓋控制器晶片並配置記憶體晶片的結構。但是，在該結構中，以DAF嵌入控制器晶片時記憶體晶片有可能變形為圓頂狀。此外，需要對齊記憶體晶片的中心與控制器晶片的中心。假設記憶體晶片相對控制器晶片位移時，控制器晶片的嵌入變為困難，有可能難以支撐記憶體晶片。結果，有可能記憶體晶片變為容易傾斜。因此，有可能無法適當地支撐記憶體晶片。
相對於此，在第1實施形態中，由於不需要嵌入半導體晶片20，僅需要將半導體晶片30黏附到半導體晶片20及樹脂層80即可。因此，半導體晶片30的安裝之難易度變低。此外，半導體晶片30不一定要直接配置在半導體晶片20的上方。因此，半導體晶片30的搭載位置之自由度可以提升。此外，DAF(黏著層40)可以變薄，因此可以削減材料費。
(第2實施形態) 圖13A及圖13B係說明第3實施形態的半導體裝置1的圖。第2實施形態與第1實施形態不同之點在於，半導體晶片30的位置存在偏移(位移)。圖13A及圖13B分別表示半導體晶片30及樹脂層80的位置關係之一例的平面圖。此外，上表面S被省略。此外，圖13A及圖13B所示樹脂層80比起半導體晶片30的外邊緣30o全體更向外側突出。
圖13A所示例中，半導體晶片30的中心位置係與半導體晶片20的中心位置及樹脂層80的中心位置大致一致。另一方面，圖13B所示半導體晶片30比起圖13A所示半導體晶片30更向紙面下方位移而配置。因此，半導體晶片30的中心位置偏離半導體晶片20的中心位置及樹脂層80的中心位置。亦即，從半導體晶片30的表面30b之上方觀察時，半導體晶片30相對於半導體晶片20或樹脂層80位移而配置。更詳細言之，半導體晶片30，係以設置在該半導體晶片30的焊墊30p與設置在配線基板10且電性連接到焊墊30p的焊墊10p分開的方式，相對於半導體晶片20或樹脂層80偏移而配置。藉此例如可以增大焊墊10p與焊墊30p之間之距離。藉由增大焊墊10p、30p間之距離，可以提升導線接合性。
如這樣地，在樹脂層80可以支撐半導體晶片30的範圍內能夠變更半導體晶片30的安裝位置。因此，可以提升封裝設計之自由度。
此外，在如上述說明的利用厚的DAF來覆蓋控制器晶片而配置記憶體晶片的結構中，記憶體晶片的安裝位置係由控制器晶片的位置來決定。因此，難以變更焊墊10p、30p之位置關係。
相對於此，第2實施形態中，藉由偏移半導體晶片30的配置，可以變更焊墊10p、30p間之距離。此外，封裝設計中，焊墊10p之位置之設計自由度可以提升。
第2實施形態的半導體裝置1的其他構成係和第1實施形態的半導體裝置1對應的構成同樣，因此省略其詳細說明。第2實施形態的半導體裝置1可以獲得和第1實施形態同樣的效果。
(第3實施形態) 圖14A及圖14B係說明第3實施形態的半導體裝置1的圖。第3實施形態與第1實施形態不同之點在於，在配線基板10上塗布量已被調整過的樹脂層80的材料80a。圖14A係表示塗布量較少時的樹脂層80的材料80a之一例的圖。圖14A中，上段表示截面圖，下段表示平面圖。圖14B係表示塗布量較多時的樹脂層80的材料80a之一例的圖。圖14B中，上段表示截面圖，下段表示平面圖。
圖14A及圖14B之平面圖係示出圖9中的材料80a的塗布步驟。圖14A及圖14B所示例中，在開口部OP附近將材料80a塗布成為X字狀。
在圖9所示步驟中，在配線基板10上塗布量已被調整過的樹脂層80的材料使得樹脂層80的上表面S成為預定面積。圖14A所示例中，材料80a的塗布量較少，因此硬化的樹脂層80的面積變小。另一方面，圖14B所示例中，材料80a的塗布量較多，因此硬化的樹脂層80的面積變大。此外，需要使用與預定的面積對應的大小之安裝治具MT擠壓樹脂層80。
如這樣地，藉由調整材料80a的塗布量，可以調整樹脂層80的面積(容積)及樹脂層之上表面S之面積。
第3實施形態的半導體裝置1的其他構成係和第1實施形態的半導體裝置1對應的構成同樣，因此省略其詳細說明。第3實施形態的半導體裝置1可以獲得和第1實施形態同樣的效果。此外，可以在第3實施形態的半導體裝置1組合第2實施形態。
(第4實施形態) 圖15A～圖15D係說明第4實施形態的半導體裝置1的圖。第4實施形態與第1實施形態不同之點在於，樹脂層80相對於半導體晶片20、30的大小或位置根據樹脂層80的材料80a的塗布位置而變化。圖15A係表示樹脂層80的材料80a的塗布位置之一例的平面圖。圖15B係表示圖15A的塗布位置中的半導體晶片30及樹脂層80的位置關係的平面圖。
在圖9所示步驟中，以樹脂層80形成於配線基板10上之預定位置的方式，或以樹脂層80形成為預定形狀的方式，在配線基板10上塗布樹脂層80的材料。圖15A所示例中，在開口部OP附近將樹脂層80的材料80a塗布成為十字狀。此外，材料80a在紙面左右方向塗布為較長。藉此，如圖15B所示，在紙面左右方向形成長的樹脂層80。
圖15C係表示樹脂層80的材料80a的塗布位置之一例的平面圖。圖15D係表示圖15C的塗布位置中的半導體晶片30與樹脂層80的位置關係的平面圖。
在圖15C所示例中，樹脂層80的材料80a在開口部OP附近被塗布成為X字狀。此外，在與開口部OP分開的紙面左方及紙面下方之2點處，樹脂層80的材料80a被塗布成為丸狀。藉此，如圖15D所示，形成覆蓋半導體晶片20，而且在紙面左下方較長的樹脂層80。
如這樣地，藉由調整材料80a的塗布位置及塗布形狀，可以調整樹脂層80的位置及形狀。
第4實施形態的半導體裝置1的其他構成係和第1實施形態的半導體裝置1對應的構成同樣，因此省略其詳細說明。第4實施形態的半導體裝置1可以獲得和第1實施形態同樣的效果。此外，在第4實施形態的半導體裝置1可以組合第2實施形態及第3實施形態。
(第5實施形態) 圖16A～圖16D係說明第4實施形態的半導體裝置1的圖。第5實施形態與第1實施形態不同之點在於半導體晶片30與樹脂層80之位置關係。圖16A～圖16D分別半導體晶片30與樹脂層80的位置關係之一例的平面圖。此外，樹脂層80的大小及形狀之調整方法可以分別與第3實施形態及第4實施形態同樣。
在圖16A所示例中，樹脂層80係從半導體晶片30的短邊突出，但不從半導體晶片30的長邊突出。圖16B所示例中，樹脂層80從半導體晶片30的短邊及紙面上側之長邊突出，但不從半導體晶片30的紙面下側之長邊突出。圖16C所示例中，樹脂層80從半導體晶片30的長邊突出。從半導體晶片30之上方觀察時，樹脂層80的外周端部與半導體晶片30的短邊大致一致。圖16D所示例中，樹脂層80從半導體晶片30的紙面下側之長邊及紙面右側之短邊突出，但不從半導體晶片30的紙面上側之長邊及紙面左側之短邊突出。
此外，更詳細言之，從半導體晶片30的表面30b之上方觀察時，樹脂層80相對於半導體晶片20或半導體晶片30偏移而配置。圖16B及圖16D所示例中，例如樹脂層80的中心位置從半導體晶片20的中心位置及半導體晶片30的中心位置偏移。
如這樣地，僅樹脂層80的特定之邊大於或小於半導體晶片30亦可。亦即，在樹脂層80能夠支撐半導體晶片30的範圍內，可以變更樹脂層80的位置或形狀等。因此，可以提升封裝設計之自由度。
第5實施形態的半導體裝置1的其他構成係和第1實施形態的半導體裝置1對應的構成同樣，因此省略其詳細說明。第5實施形態的半導體裝置1可以獲得和第1實施形態同樣的效果。此外，在第5實施形態的半導體裝置1組合第2實施形態～第4實施形態亦可。
對本發明之幾個實施形態進行說明，但是這些實施形態僅作為提示之例，並不意圖限定發明之範圍。這些實施形態可以用其他各種形態來實施，在不脫離發明之要旨的範圍內可以進行各種省略、替換、變更。這些實施形態或其變形，係和包含於發明之範圍或要旨同樣地，亦包含於申請專利範圍所記載的發明和其均等之範圍內。
1:半導體裝置 10:配線基板 10p:焊墊 11:配線層 12:貫穿電極 13:金屬凸塊 14:阻焊層 15:絕緣層 20,30~33:半導體晶片 20a:20b:表面 21:電極柱(連接凸塊) 30a,30b:表面 40~43:黏著層 70:金屬材料 80:樹脂層 90:接合導線 91:密封樹脂
[圖1]係表示第1實施形態的半導體裝置的結構例的截面圖。 [圖2]係表示圖1的配線基板、半導體晶片與樹脂層的位置關係之一例的平面圖。 [圖3]係表示第1實施形態的半導體裝置的製造方法之一例的圖。 [圖4]係表示接續圖3的半導體裝置的製造方法之一例的圖。 [圖5]係表示接續圖4的半導體裝置的製造方法之一例的圖。 [圖6]係表示接續圖5的半導體裝置的製造方法之一例的圖。 [圖7]係表示接續圖6的半導體裝置的製造方法之一例的圖。 [圖8]係表示接續圖7的半導體裝置的製造方法之一例的圖。 [圖9]係表示接續圖8的半導體裝置的製造方法之一例的圖。 [圖10]係表示接續圖9的半導體裝置的製造方法之一例的圖。 [圖11]係表示接續圖10的半導體裝置的製造方法之一例的圖。 [圖12]係表示接續圖11的半導體裝置的製造方法之一例的圖。 [圖13A]係表示半導體晶片與樹脂層的位置關係之一例的平面圖。 [圖13B]係表示半導體晶片與樹脂層的位置關係之一例的平面圖。 [圖14A]係表示塗布量較少時的樹脂層的材料之一例的圖。 [圖14B]係表示塗布量較多時的樹脂層的材料之一例的圖。 [圖15A]係表示樹脂層的材料的塗布位置之一例的平面圖。 [圖15B]係表示圖15A的塗布位置中的半導體晶片與樹脂層的位置關係的平面圖。 [圖15C]係表示樹脂層的材料的塗布位置之一例的平面圖。 [圖15D]係表示圖15C的塗布位置中的半導體晶片與樹脂層的位置關係的平面圖。 [圖16A]係表示半導體晶片與樹脂層的位置關係之一例的平面圖。 [圖16B]係表示半導體晶片與樹脂層的位置關係之一例的平面圖。 [圖16C]係表示半導體晶片與樹脂層的位置關係之一例的平面圖。 [圖16D]係表示半導體晶片與樹脂層的位置關係之一例的平面圖。
1:半導體裝置
10:配線基板
10p:焊墊
11:配線層
12:貫穿電極
13:金屬凸塊
14:阻焊層
15:絕緣層
20,30~33:半導體晶片
20a,20b:表面
21:電極柱(連接凸塊)
30a,30b:表面
40~43:黏著層
70:金屬材料
80:樹脂層
90:接合導線
91:密封樹脂
OP:開口部
S:上表面

Claims (12)

  1. 一種半導體裝置，具備： 配線基板； 第1半導體晶片，係具有第1表面和該第1表面之相反側的第2表面且在前述第1表面上具有連接凸塊的第1半導體晶片，並且在前述第1表面側透過前述連接凸塊連接到前述配線基板的第1半導體晶片； 樹脂層，係在前述第1半導體晶片與前述配線基板之間覆蓋前述連接凸塊，且在前述在第1半導體晶片的周圍以使前述樹脂層的上表面成為與前述第1半導體晶片的前述第2表面呈大致平行的方式而設置；及 第2半導體晶片，係具有第3表面和該第3表面之相反側的第4表面且在前述第3表面上具有黏著層的第2半導體晶片，且在前述第3表面側上透過前述黏著層黏附到前述第1半導體晶片的前述第2表面和前述樹脂層之上表面的第2半導體晶片； 前述第2半導體晶片的前述第4表面之上方觀察時，前述樹脂層之上表面係從前述第2半導體晶片的外邊緣的至少一部分向外側突出。
  2. 如請求項1之半導體裝置，其中 在前述第2半導體晶片與前述配線基板之間未設置間隔件。
  3. 如請求項1之半導體裝置，其中 從前述第2半導體晶片的前述第4表面之上方觀察時，前述樹脂層之上表面係從前述第2半導體晶片的前述第4表面上所設置的第1焊墊側之前述外邊緣向外側突出。
  4. 如請求項1至3之任一項之半導體裝置，其中 從前述第2半導體晶片的前述第4表面之上方觀察時，前述第2半導體晶片的中心位置相對於前述第1半導體晶片的中心位置或前述樹脂層的中心位置呈偏移而配置。
  5. 如請求項4之半導體裝置，其中 前述第2半導體晶片的中心位置，係以設置在該第2半導體晶片的第1焊墊與被設置在前述配線基板且被電性連接到前述第1焊墊的第2焊墊呈分開的方式，相對於前述第1半導體晶片的中心位置或前述樹脂層的中心位置偏移而配置。
  6. 如請求項1至3之任一項之半導體裝置，其中 從前述第2半導體晶片的前述第4表面之上方觀察時，前述樹脂層的中心位置相對於前述第1半導體晶片的中心位置或前述第2半導體晶片的中心位置偏移而配置。
  7. 如請求項1至3之任一項之半導體裝置，其中 在前述第2半導體晶片的外周端部與前述樹脂層之境界部處，前述樹脂層之上表面係與前述第1半導體晶片的前述第2表面呈大致平行。
  8. 如請求項1至3之任一項之半導體裝置，其中 前述樹脂層係設置在第2焊墊之前部為止的範圍內，該第2焊墊係可以經由導線接合到被該樹脂層之上表面支撐的前述第2半導體晶片的前述第4表面上所設置的第1焊墊、並且設置在前述配線基板且連接到前述導線者。
  9. 一種半導體裝置的製造方法，具備： 將樹脂層的材料塗布在配線基板上的步驟， 使具有第1表面和該第1表面之相反側的第2表面且在前述第1表面上具有連接凸塊的第1半導體晶片的前述第1表面面對前述配線基板以使前述連接凸塊在前述樹脂層內連接到前述配線基板，並且以使前述樹脂層之上表面成為與前述第1半導體晶片的前述第2表面呈大致平行的方式對前述樹脂層實施硬化的步驟，及 使具有第3表面和該第3表面之相反側的第4表面且在前述第3表面上具有黏著層的第2半導體晶片的前述第3表面，透過前述黏著層黏附到前述第1半導體晶片的前述第2表面及前述樹脂層之上表面的步驟， 還具備：從前述第2半導體晶片的前述第4表面之上方觀察時，使前述樹脂層之上表面從前述第2半導體晶片的外邊緣的至少一部分向外側突出的步驟。
  10. 如請求項9之半導體裝置的製造方法，其中 還具備：以使前述樹脂層形成在前述配線基板上之預定位置的方式，或以使前述樹脂層形成為預定形狀的方式，將前述樹脂層的材料塗布在前述配線基板上的步驟。
  11. 如請求項9之半導體裝置的製造方法，其中 還具備：將以使前述樹脂層之上表面成為預定面積的方式而被調整了量的前述樹脂層的材料塗布在前述配線基板上的步驟。
  12. 如請求項9至11之任一項之半導體裝置的製造方法，其中 還具備：在前述第2半導體晶片與前述配線基板之間不設置間隔件。
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US7956449B2 (en) * 2008-06-25 2011-06-07 Stats Chippac Ltd. Stacked integrated circuit package system
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US20190067248A1 (en) 2017-08-24 2019-02-28 Micron Technology, Inc. Semiconductor device having laterally offset stacked semiconductor dies
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