CN113257772A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN113257772A
CN113257772A CN202010875391.7A CN202010875391A CN113257772A CN 113257772 A CN113257772 A CN 113257772A CN 202010875391 A CN202010875391 A CN 202010875391A CN 113257772 A CN113257772 A CN 113257772A
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Prior art keywords
electrode
wiring layer
opening
semiconductor device
semiconductor chip
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CN202010875391.7A
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English (en)
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丹羽惠一
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Kioxia Corp
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Kioxia Corp
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Publication of CN113257772A publication Critical patent/CN113257772A/zh
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Abstract

本发明提供能够抑制在倒装芯片连接的连接区域产生孔洞的情况的半导体装置及其制造方法。本实施方式的半导体装置具备布线基板，该布线基板包含布线层和设于该布线层上的绝缘层，在设于所述绝缘层的开口部中使所述布线层的一部分露出。导电材料被埋入开口部，覆盖该开口部内的布线层。半导体芯片具有插入到开口部内并连接于导电材料的电极。在从半导体芯片的搭载方向观察时，电极与布线层分离，在电极与布线层之间夹设有导电材料。

Description

半导体装置及其制造方法
相关申请的引用
本申请以2020年02月07日提出申请的在先的日本专利申请第2020－19933号的优先权利益为基础，并且谋求其利益，此处通过引用而包含其内容整体。
技术领域
本实施方式涉及半导体装置及其制造方法。
背景技术
作为将半导体芯片向布线基板进行倒装芯片连接的方法，存在批量回流(massreflow)方式或者热压接方式。其中，在基于热压接方式的倒装芯片连接中，在将半导体芯片搭载于布线基板上时，利用热量使焊料熔融，使半导体芯片的凸块与布线基板的焊盘热压接而连接。
这种热压接方式中使用的布线基板在凸块的连接区域的阻焊剂上具有开口部，在开口部中使布线的一部分或者焊盘露出。在该连接区域中，在阻焊剂与其衬底(预浸料)之间存在台阶，在供给NCP(Non-Conductive Past，非导电性胶粘剂)时，有时在连接区域内、或者凸块的周围残留有孔洞。这种孔洞会导致邻接的凸块间的短路不良、NCP树脂的紧贴性不良、或者可靠性的恶化。
发明内容
一个实施方式提供能够抑制在倒装芯片连接的连接区域产生孔洞的情况的半导体装置及其制造方法。
本实施方式的半导体装置具备布线基板，该布线基板包含布线层和设于该布线层上的绝缘层，在设于所述绝缘层的开口部中使所述布线层的一部分露出。导电材料被埋入开口部，覆盖该开口部内的布线层。半导体芯片具有插入到开口部内并连接于导电材料的电极。在从半导体芯片的搭载方向观察时，电极与布线层分离，在电极与布线层之间夹设有导电材料。
附图说明
图1是表示第一实施方式的半导体装置的构成例的剖面图。
图2是表示图1的框B1的构成的放大剖面图。
图3是表示阻焊层、开口部、布线层以及电极柱的位置关系的俯视图。
图4是表示第一实施方式的半导体装置的制造方法的一个例子的图。
图5是表示接着图4的半导体装置的制造方法的一个例子的图。
图6是表示接着图5的半导体装置的制造方法的一个例子的图。
图7是表示接着图6的半导体装置的制造方法的一个例子的图。
图8是表示接着图7的半导体装置的制造方法的一个例子的图。
图9是表示接着图8的半导体装置的制造方法的一个例子的图。
图10是表示接着图9的半导体装置的制造方法的一个例子的图。
图11是表示接着图10的半导体装置的制造方法的一个例子的图。
图12是表示接着图11的半导体装置的制造方法的一个例子的图。
图13是表示接着图12的半导体装置的制造方法的一个例子的图。
图14是表示接着图13的半导体装置的制造方法的一个例子的图。
图15是表示接着图14的半导体装置的制造方法的一个例子的图。
图16是表示第二实施方式的半导体芯片与布线基板的连接部分的构成例的放大剖面图。
图17是表示第二实施方式的阻焊层、开口部、布线层以及电极柱的位置关系的俯视图。
图18是表示第三实施方式的半导体芯片与布线基板的连接部分的构成例的放大剖面图。
图19是表示第四实施方式的半导体芯片与布线基板的连接部分的构成例的放大剖面图。
具体实施方式
以下，参照附图对本发明的实施方式进行说明。本实施方式并不限定本发明。在以下的实施方式中，布线基板的上下方向表示以搭载有半导体芯片的面为上方的情况下的相对方向，有时与遵循重力加速度的上下方向不同。附图为示意性或者概念性的图，各部分的比率等并不一定与现实相同。在说明书与附图中，对于与在已出现的附图中描述过的要素相同的要素，标注相同的附图标记并适当省略详细的说明。
(第一实施方式)图1是表示第一实施方式的半导体装置的构成例的剖面图。半导体装置1具备布线基板10、半导体芯片20、30～33、粘合层40～43、隔件芯片50、粘合层60、金属材料70、树脂层80、接合线90、以及密封树脂91。半导体装置1例如是NAND型闪存的封装。
布线基板10也可以是包含布线层11与绝缘层15的印刷基板、中介层。在布线层11中例如使用铜、镍或者它们的合金等低电阻金属。在绝缘层15中例如使用玻璃环氧树脂等绝缘性材料。在图中，仅在绝缘层15的表面与背面设有布线层11。但是，布线基板10也可以具有将多个布线层11以及多个绝缘层15层叠而构成的多层布线构造。布线基板10例如也可以具有如中介层那样贯通其表面与背面的贯通电极12。
在布线基板10的表面设有设于布线层11上的阻焊层14。阻焊层14是用于保护布线层11不受金属材料70影响并抑制短路不良的绝缘层。在阻焊层14设有开口部OP，布线层11的一部分以及绝缘层15从开口部OP露出。
在布线基板10的背面也设有设于布线层11上的阻焊层14。在从阻焊层14露出的布线层11设有金属凸块13。金属凸块13是为了将未图示的其他部件与布线基板10电连接而设置的。
半导体芯片20例如是控制存储器芯片的控制器芯片。在半导体芯片20的表面设有未图示的半导体元件。半导体元件例如可以是构成控制器的CMOS(Complementary MetalOxide Semiconductor，互补金属氧化物半导体)电路。在半导体芯片20的背面设有与半导体元件电连接的电极柱21。在电极柱21中例如使用了铜、镍或者它们的合金等低电阻金属材料。
电极柱21被插入于布线基板10的开口部OP，电极柱21的下端部配置于比开口部OP的上端低的位置。在电极柱21的周围设有金属材料70。电极柱21经由金属材料70而与在开口部OP中露出的布线层11电连接。
金属材料70被埋入布线基板10的开口部OP内，覆盖在开口部OP内露出的布线层11。在金属材料70中例如使用了焊料、银、铜等低电阻金属材料。金属材料70是如后述那样被作为液体或者糊状的金属材料加以供给，之后固化而形成的。金属材料70在开口部OP内覆盖布线基板10的布线层11，并且也覆盖半导体芯片20的电极柱21的侧面。由此，金属材料70能够将半导体芯片20的电极柱21与布线基板10的布线层11电连接。电极柱21与布线层11分离且不直接接触。即，在电极柱21与布线层11之间夹设有金属材料70。
在半导体芯片20的周围以及半导体芯片20与布线基板10之间设有树脂层(底部填充)80。树脂层80例如是使NCP(Non Conductive Past)固化而成的，将半导体芯片20的周围覆盖而保护。
在半导体芯片20之上经由粘合层40粘合有半导体芯片30。半导体芯片30例如是包含NAND型闪存的存储器芯片。半导体芯片30在其表面具有半导体元件(未图示)。半导体元件例如也可以是存储器单元阵列及其周边电路(CMOS电路)。存储器单元阵列也可以是将多个存储器单元三维配置而成的立体型存储器单元阵列。另外，在半导体芯片30上经由粘合层41粘合有半导体芯片31。在半导体芯片31上经由粘合层42粘合有半导体芯片32。在半导体芯片32上经由粘合层43粘合有半导体芯片33。半导体芯片31～33例如与半导体芯片30相同，例如是包含NAND型闪存的存储器芯片。半导体芯片30～33也可以是相同的存储器芯片。在图中，除了作为控制器芯片的半导体芯片20之外，还层叠有作为四个存储器芯片的半导体芯片30～33。但是，半导体芯片的层叠数可以是3以下，也可以是5以上。
半导体芯片30比半导体芯片20大，半导体芯片30的外缘位于半导体芯片20的外缘的外侧。在半导体芯片20的周围，在半导体芯片30与布线基板10的阻焊层14之间设有隔件芯片50。隔件芯片50经由粘合层60粘合于阻焊层14上。另外，在隔件芯片50的上表面粘合有粘合层40，半导体芯片30经由粘合层40粘合于隔件芯片50的上表面。
接合线90连接于布线基板10、半导体芯片30～33的任意的焊盘。为了利用接合线90连接，半导体芯片30～33错开焊盘大小地层叠。另外，半导体芯片20利用电极柱21进行倒装芯片连接，因此未进行引线接合。但是，半导体芯片20也可以除了基于电极柱21的连接之外还进行引线接合。
而且，密封树脂91将半导体芯片20、30～33、隔件芯片50、树脂层80、接合线90等密封。由此，半导体装置1是将多个半导体芯片20、30～33在布线基板10上作为一个半导体封装而构成的。
图2是表示图1的框B1的构成的放大剖面图。图3是表示阻焊层、开口部、布线层以及电极柱的位置关系的俯视图。在阻焊层14设有开口部OP，布线层11的一部分露出。金属材料70被埋入开口部OP内，与布线层11的一部分接触。电极柱21插入于金属材料70内，经由金属材料70电连接于布线层11。
电极柱21的下端部21b向开口部OP内插入。由此，电极柱21的下端部21b的高度H21位于比阻焊层14的上表面14a的高度H14靠下方。由此，电极柱21接触并插入到在开口部OP内填充的液体或者糊状的金属材料70内。金属材料70从电极柱21的下端部21b沿着侧面攀升，从开口部OP的上端朝向斜上方直至电极柱21的侧面为止具有锥形。如此，金属材料70沿电极柱21的侧面从开口部OP鼓起。金属材料70沿电极柱21的侧面从开口部OP鼓起与插入于与开口部OP的电极柱21的体积相同的量或其以上的量。金属材料70以与电极柱21的侧面接触的方式从开口部OP鼓起，使得金属材料70与电极柱21之间的接触电阻变小。
在图2中，电极柱21的下端部21b的高度H21位于比阻焊层14的高度H14低并且比布线层11的上表面11a的高度H11高的位置。但是，电极柱21的下端部21b的高度H21也可以位于比布线层11的上表面11a的高度H11低的位置。而且，电极柱21的下端部21b也可以与布线基板10的绝缘层15的上表面15a接触。在电极柱21的正下方未设有布线层11，因此电极柱21的下端部21b能够与绝缘层15的上表面15a接触。即，下端部21b的高度H21也可以与绝缘层15的表面的高度相等。如此，电极柱21的下端部21b只要位于比阻焊层14的高度H14低的位置，则可以定位于任意的位置。电极柱21的下端部21b越接近绝缘层15的上表面15a，半导体芯片20越接近布线基板10，能够减少半导体装置1的封装的厚度。因而，可以说电极柱21的下端部21b越接近绝缘层15的上表面15a越优选。
另外，在电极柱21的正下方不存在布线层11，而是设有金属材料70。如图3所示，在从半导体芯片20的搭载方向(图2的Z方向的上方)观察时，电极柱21与布线层11分离，在电极柱21与布线层11之间夹设作为“导电材料”的金属材料70。
布线层11的一部分在从上述搭载方向观察时从开口部OP的侧面朝向开口部OP的中心部突出。由此，布线部11与金属材料70的接触面积变大，布线部11与金属材料70之间的接触电阻变小。
在本实施方式中，将液体或者糊状的金属材料(例如焊料糊剂、铜或者银糊剂、铜或者银纳米墨等)70预先填充于开口部OP内，将半导体芯片20的电极柱21插入(浸渍)于开口部OP内的金属材料70。由此，能够抑制在开口部OP内产生孔洞，并抑制电极柱21与布线层11的接触不良。
另外，在平面布局中，电极柱21不与布线层11重叠，且与布线层11分离。即，在平面布局中，电极柱21与布线层11之间不干扰。由此，电极柱21的下端部21b的高度H21可以设为比布线层11的上表面11a的高度H11低。而且，电极柱21的下端部21b也可以到达绝缘层15的上表面15a。通过使电极柱21的下端部21b接近绝缘层15的上表面15a，能够减薄半导体装置1的封装的厚度。
接下来，对本实施方式的半导体装置1的制造方法进行说明。
图4～图15是表示第一实施方式的半导体装置的制造方法的一个例子的图。首先，在半导体晶圆W形成半导体元件。图4是形成有半导体元件的半导体晶圆W的立体图。在半导体晶圆W上形成有半导体元件，聚酰亚胺PI覆盖半导体元件。半导体晶圆W包含在后述的切割工序中被单片化的多个半导体芯片20(或者30～33)。
接下来，如图5所示，在聚酰亚胺PI上粘附保护带TP1。接下来，使保护带TP1为下方，利用研磨机G对半导体晶圆W的背面进行研磨。
在剥离保护带TP1之后，如图7所示，在张设于晶圆环WR内的挠性的树脂带TP2上粘附半导体晶圆W的背面。接下来，使用激光振荡器LG，沿半导体晶圆W的表面或者背面的切割线照射激光。由此，在切割线形成槽(groove)。
接下来，如图9所示，利用切割刀片DB沿切割线的槽切断半导体晶圆W。由此，半导体晶圆W被单片化为半导体芯片20(或者30～33)。单片化后的半导体芯片20(或者30～33)为了安装于布线基板10而被从树脂带TP2拾取。
另一方面，在布线基板10中，形成绝缘层15、布线层11、贯通电极12、阻焊层14。接下来，使用形成于阻焊层14上的掩模材料M1，在阻焊层14形成开口部OP。此时，开口部OP形成为使布线层11及其周边的绝缘层15露出。
接下来，虽然未图示，涂覆助焊剂而将在开口部OP中露出的布线层11的表面的氧化膜去除。接下来，对布线基板10进行热处理而进行等离子体处理。接下来，如图10所示，向布线基板10的表面以及开口部OP供给液体或者糊状的金属材料70。液体或者糊状的金属材料70覆盖在开口部OP中露出的布线层11。
接下来，如图11所示，利用工具100在布线基板10的掩模材料M1的表面上扫过。工具100例如也可以是由树脂、金属等构成的板状的刮削器。通过利用工具100在布线基板10上向A1方向扫过，从而如图12所示那样使液体或者糊状的金属材料70填充于开口部OP，同时将剩余的金属材料70从布线基板10去除。A1方向是与布线基板10的表面大致平行的方向。即，刮板工具100一边在布线基板10上向A1方向扫过，一边使金属材料70在开口部OP内留置，并且进行擦拭以从布线基板10去除剩余的金属材料70。由此，如图13所示，在开口部OP内填充金属材料70。金属材料70几乎不残留在掩模材料M1上。另外，即使金属材料70残留在掩模材料M1上，也可通过去除掩模材料M1而从阻焊层14上去除金属材料70。另外，也可以使金属材料70回流，以使金属材料70更可靠地填充于开口部OP内。
接下来，拾取在图9所示的工序中形成的半导体芯片20，将半导体芯片20的电极柱21插入开口部OP内的金属材料70中。此时，液体或者糊状的金属材料70若接触电极柱21的下端部，则从其下端部沿着侧面攀升。由此，金属材料70形成为从开口部OP的上端朝向斜上方直至电极柱21的侧面地具有锥形。由此，金属材料70沿电极柱21的侧面从开口部OP鼓起。金属材料70沿电极柱21的侧面从开口部OP鼓起与插入于开口部OP的电极柱21的体积相同的量或者其以上的量。由于金属材料70以接触电极柱21的侧面的方式从开口部OP鼓起，使得金属材料70与电极柱21之间的接触电阻变小。
另外，电极柱21的下端部只要比阻焊层14的上表面低即可。即，电极柱21的下端部也可以插入到布线层11的上表面的下方，也可以仅插入到比布线层11的上表面高的位置。这是因为，电极柱21即使不与布线层11直接接触，也能够经由金属材料70电连接于布线层11。
而且，如参照图3说明的那样，在电极柱21的正下方不存在布线层11。由此，在从半导体芯片20的搭载方向观察时，电极柱21与布线层11分离，在电极柱21与布线层11之间夹设金属材料70。如此，即使在电极柱21的正下方未设有布线层11，电极柱21也能够经由金属材料70电连接于布线层11。
电极柱21的下端部也可以与绝缘层15的上表面接触。由此，半导体芯片20与布线基板10的距离变近，能够减小半导体装置1的封装的厚度。
接下来，对布线基板10进行烘烤，使液体或者糊状的金属材料70的溶剂挥发。电极柱21与金属材料70通过金属扩散而连接。若烘烤结束，则金属材料70比烘烤前固化。由此，半导体芯片20相对于布线基板10的位置被大致决定。
接下来，如图15所示，半导体芯片20被供给树脂层80。树脂层80例如是底部填充材料，进入半导体芯片20与布线基板10之间，将金属材料70的周围以及半导体芯片20的侧面覆盖。接下来，在半导体芯片20的周边的布线基板10上经由粘合层60粘合隔件芯片50。隔件芯片50的上表面的高度优选的是与半导体芯片20的上表面的高度大致相等。由此，层叠于半导体芯片20上的半导体芯片30～33的平坦性提高。
之后，如图1所示，将在背面粘附有粘合层40的半导体芯片30搭载于半导体芯片20上，将在背面粘附有粘合层41的半导体芯片31搭载于半导体芯片30上，将在背面粘附有粘合层42的半导体芯片32搭载于半导体芯片31上，将在背面粘附有粘合层43的半导体芯片33搭载于半导体芯片32上。
接下来，利用接合线90将半导体芯片30～33的焊盘以及布线基板10上的焊盘连接。而且，利用密封树脂91将半导体芯片20、30～33、接合线90等密封，获得图1所示的构造。
如以上那样，在本实施方式中，在将糊状的金属材料(例如焊料糊剂)70供给到布线基板10上之后，利用工具100擦拭金属材料70。由此，将金属材料70填充于开口部OP内。之后，将半导体芯片20的电极柱21插入开口部OP内的金属材料70。
如果在电极柱21预先形成有焊料凸块而将该焊料凸块以倒装芯片的方式连接于布线基板10的情况下，为了去除凸块表面的氧化膜而一边向连接部供给助焊剂一边执行倒装芯片连接。此时，由于助焊剂的流动，在开口部OP的内部、电极柱21的周围产生孔洞(卷入孔洞)。
与此相对，在本实施方式中，向预先填充于开口部OP内的金属材料(焊料)70中插入电极柱21。由此，在倒装芯片连接时，开口部OP已被金属材料70填充，因此不会在开口部OP的内部或者电极柱21的周围产生孔洞。另外，无需使焊料凸块预先附着于电极柱21，在倒装芯片连接时不需要助焊剂的供给。因而，能够抑制在开口部OP的内部、电极柱21的周围产生卷入孔洞。
(第二实施方式)图16是表示第二实施方式的半导体芯片与布线基板的连接部分的构成例的放大剖面图。图17是表示第二实施方式的阻焊层、开口部、布线层以及电极柱的位置关系的俯视图。在第二实施方式中，布线层11的一部分面对开口部OP的内表面，在该内表面露出。即，如图16所示，布线层11不向开口部OP突出，而仅是面对开口部OP。即使是这种构成，金属材料70也能够不与布线层11接触，能够将电极柱21与布线层11电连接。
第二实施方式的其他构成也可以与第一实施方式的对应的构成相同。因而，第二实施方式能够获得与第一实施方式相同的效果。
(第三实施方式)图18是表示第三实施方式的半导体芯片与布线基板的连接部分的构成例的放大剖面图。根据第三实施方式，电极柱21的下端部21b的高度H21比布线层11的上表面11a的高度H11靠下方。由此，金属材料70与电极柱21的侧面在相对较大的面积内接触。由此，金属材料70与电极柱21之间的接触电阻进一步变小。第三实施方式的其他构成也可以与第一实施方式的对应构成相同。由此，第三实施方式能够获得与第一实施方式相同的效果。另外，第三实施方式也可以与第二实施方式进行组合。
(第四实施方式)图19是表示第四实施方式的半导体芯片与布线基板的连接部分的构成例的放大剖面图。根据第四实施方式，电极柱21的下端部21b与绝缘层(预浸料)15的上表面15a接触。即，下端部21b的高度H21与布线基板10的绝缘层15的上表面15a大致相等。由此，金属材料70能够与电极柱21的侧面以更大的面积接触。由此，金属材料70与电极柱21之间的接触电阻进一步变小。第四实施方式的其他构成也可以与第一实施方式的对应构成相同。由此，第四实施方式能够获得与第一实施方式相同的效果。另外，第四实施方式也可以与第二实施方式进行组合。
(第五实施方式)在第一至第四实施方式中，如图13～图15所示，将半导体芯片20与布线基板10连接之后进行树脂层80的供给。但是，在第五实施方式中，在将金属材料70设于布线基板10后，向布线基板10供给NCP(非导电糊剂)作为树脂层80。之后，将半导体芯片20与布线基板10一边加热一边按压而使之连接。此时，位于布线基板10与半导体芯片20之间的NCP由于加热与按压而流动，从布线基板10与半导体芯片20之间泄漏而沿半导体芯片20的侧面攀升。因而，在本实施方式中，半导体芯片20、布线基板10以及树脂层80也成为图1所示的样式。在该情况下，也能够获得与第一～第四实施方式相同的效果。
(第六实施方式)在第六实施方式中，叙述取代使用NCP而使用了(非导电性膜)的连接方法。在本实施方式中，将金属材料70设于布线基板10。作为树脂层80将NCF(非导电性膜)设于半导体芯片20的形成有电极柱21的面上。之后将半导体芯片20与布线基板10一边加热一边按压而使之连接。此时，位于布线基板10与半导体芯片20之间的NCF由于加热与按压而流动，从布线基板10与半导体芯片20之间泄漏而沿半导体芯片20的侧面攀升。因而，在本实施方式中半导体芯片20、布线基板10以及树脂层80也成为图1所示的方式。在该情况下，也能够获得与第一至第五实施方式相同的效果。
(其他实施方式)(a)在上述实施方式中，金属材料70通过使用刮板而被设于布线基板10的开口部OP。除此之外，也可以通过丝网印刷、分注、喷墨等各种方法将金属材料70设于开口部OP。在该情况下，也能够获得与上述实施方式相同的效果。(b)在上述实施方式中，在将电极柱21插入开口部OP内的金属材料70时，也可以一边加热半导体芯片20或者布线基板10一边进行。在该情况下，也能够获得与上述实施方式相同的效果。(c)在上述实施方式中，也可以取代金属材料70而使用导电性的树脂等(例如PEDOT：PSS等)。在该情况下，也能够获得与上述实施方式相同的效果。除此之外，只要是导电性材料即可，也可以取代金属材料70而使用任意的材料。
虽然说明了本发明的几个实施方式，但这些实施方式是作为例子而提出的，并不意图限定发明的范围。这些实施方式能够以其他各种方式实施，在不脱离发明的主旨的范围内，能够进行各种省略、替换、变更。这些实施方式、其变形包含在发明的范围、主旨中，同样包含在权利要求书所记载的发明与其等效的范围内。

Claims (18)

1.一种半导体装置，其中，具备：
布线基板，包含布线层和设于该布线层上的绝缘层，在设于所述绝缘层的开口部中使所述布线层的一部分露出；
导电材料，被埋入所述开口部，覆盖该开口部内的所述布线层；以及
半导体芯片，具有插入到所述开口部内并连接于所述导电材料的电极，
在从所述半导体芯片的搭载方向观察时，所述电极与所述布线层分离，在所述电极与所述布线层之间夹设有所述导电材料。
2.根据权利要求1所述的半导体装置，其中，
所述电极的下端位于比所述布线层的上表面靠下方的位置。
3.根据权利要求1所述的半导体装置，其中，
所述电极的下端位于比所述布线层的上表面靠上方的位置。
4.根据权利要求1所述的半导体装置，其中，
在从所述搭载方向观察时，所述布线层的一部分从所述开口部突出。
5.根据权利要求1所述的半导体装置，其中，
所述布线层的一部分面对所述开口部的内表面，并在该内表面露出。
6.根据权利要求1至5中任一项所述的半导体装置，其中，
所述导电材料沿所述电极的侧面从所述开口部鼓起。
7.根据权利要求6所述的半导体装置，其中，
所述导电材料沿所述电极的侧面从所述开口部鼓起与插入于所述开口部的所述电极的体积相同的量或其以上的量。
8.根据权利要求1所述的半导体装置，其中，
所述电极与所述布线基板的所述开口部的底部接触。
9.根据权利要求1所述的半导体装置，其中，
在所述布线层以及所述电极中使用了铜、镍或者它们的合金，
在所述导电材料中使用了焊料、银、铜。
10.一种半导体装置的制造方法，其中，具备如下步骤：
包含布线层和设于该布线层上的绝缘层，向以使所述布线层的一部分露出的方式设于该绝缘层的开口部供给液体或者糊状的导电材料，
将设于半导体芯片的电极插入到所述开口部内的所述导电材料，
使所述导电材料固化。
11.根据权利要求10所述的半导体装置的制造方法，其中，
在从所述半导体芯片的搭载方向观察时，所述电极与所述布线层分离，所述导电材料位于所述电极与所述布线层之间。
12.根据权利要求10所述的半导体装置的制造方法，其中，
所述电极的下端插入至所述布线层的上表面的下方。
13.根据权利要求10所述的半导体装置的制造方法，其中，
所述电极的下端插入至所述布线层的上表面的上方。
14.根据权利要求10所述的半导体装置的制造方法，其中，
所述电极以与所述布线基板的所述开口部的底部接触的方式插入。
15.根据权利要求10所述的半导体装置的制造方法，其中，
在所述布线层以及所述电极中使用了铜、镍或者它们的合金，
在所述导电材料中使用了焊料、银糊剂、铜糊剂。
16.根据权利要求10至15中任一项所述的半导体装置的制造方法，其中，
向所述布线基板的表面上供给所述导电材料，利用工具在所述布线基板的表面上扫过，从而使所述导电材料填充于所述开口部，同时将剩余的所述导电材料从所述布线基板去除，由此向所述开口部供给导电材料。
17.根据权利要求10至15中任一项所述的半导体装置的制造方法，其中，
在将设于所述半导体芯片的电极插入所述开口部内的所述导电材料之前，
向所述布线基板与所述半导体芯片之间供给绝缘树脂。
18.根据权利要求10至15中任一项所述的半导体装置的制造方法，其中，
在将设于所述半导体芯片的电极插入所述开口部内的所述导电材料之后，
向所述布线基板与所述半导体芯片之间供给绝缘树脂。
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