TW202131418A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

Info

Publication number
TW202131418A
TW202131418A TW109126855A TW109126855A TW202131418A TW 202131418 A TW202131418 A TW 202131418A TW 109126855 A TW109126855 A TW 109126855A TW 109126855 A TW109126855 A TW 109126855A TW 202131418 A TW202131418 A TW 202131418A
Authority
TW
Taiwan
Prior art keywords
electrode
opening
semiconductor device
wiring layer
wiring
Prior art date
Application number
TW109126855A
Other languages
English (en)
Other versions
TWI758815B (zh
Inventor
丹羽恵一
Original Assignee
日商鎧俠股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商鎧俠股份有限公司 filed Critical 日商鎧俠股份有限公司
Publication of TW202131418A publication Critical patent/TW202131418A/zh
Application granted granted Critical
Publication of TWI758815B publication Critical patent/TWI758815B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199—Material of the matrix
    • H01L2224/13294—Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/132 - H01L2224/13291
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13347—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the bump connector during or after the bonding process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/8101—Cleaning the bump connector, e.g. oxide removal step, desmearing
    • H01L2224/81011—Chemical cleaning, e.g. etching, flux
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81455—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81909—Post-treatment of the bump connector or bonding area
    • H01L2224/8193—Reshaping
    • H01L2224/81935—Reshaping by heating means, e.g. reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8314—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85447—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85455—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06575—Auxiliary carrier between devices, the carrier having no electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Abstract

按照本實施形態之半導體裝置，具備：配線基板，包含配線層與設於該配線層上的絕緣層，於設於前述絕緣層的開口部使前述配線層的一部分露出。導電材料，被埋入開口部，被覆該開口部內的配線層。半導體晶片，具有被插入開口部內而連接至導電材料之電極。從半導體晶片的搭載方向觀看時，電極與配線層相隔距離，在電極與配線層之間介著導電材料。

Description

半導體裝置及其製造方法
本實施形態有關半導體裝置及其製造方法。 關連申請案之引用 本申請案以依2020年2月7日申請之先行的日本國專利申請案第2020-19933號之優先權利益為基礎，且求取其利益，其內容全體藉由引用而被包含於此。
作為將半導體晶片對配線基板覆晶(flip-chip)連接之方法，有大量迴焊(mass reflow)方式或熱壓接方式。其中按照熱壓接方式之覆晶連接中，當將半導體晶片搭載於配線基板上時，藉由熱使焊料熔融，使半導體晶片的凸塊與配線基板的焊墊熱壓接而連接。
這樣的熱壓接方式中使用的配線基板，是在凸塊的連接區域的阻焊劑(solder resist)具有開口部，於開口部使配線的一部分或焊墊露出。此連接區域中，在阻焊劑與其基底(預浸材；pre-preg)之間有高低差，當供給NCP(Non-Conductive Paste；非導電性膠)時可能會在連接區域內或是凸塊的周圍留下孔隙(void)。這樣的孔隙，會造成鄰接的凸塊間的短路不良、NCP樹脂的密合性不良、或是可靠性的惡化。
一個實施形態，提供一種能夠抑制在覆晶連接的連接區域產生孔隙之半導體裝置及其製造方法。
按照本實施形態之半導體裝置，具備：配線基板，包含配線層與設於該配線層上的絕緣層，於設於前述絕緣層的開口部使前述配線層的一部分露出。導電材料，被埋入開口部，被覆該開口部內的配線層。半導體晶片，具有被插入開口部內而連接至導電材料之電極。從半導體晶片的搭載方向觀看時，電極與配線層相隔距離，在電極與配線層之間介著導電材料。
以下參照圖面說明本發明之實施形態。本實施形態並不限縮本發明。以下實施形態中，配線基板的上下方向，是示意當將供半導體晶片搭載的面訂為上的情形之相對方向，可能和遵照重力加速度的上下方向相異。圖面為模型化或概念性質之物，各部分的比率等，未必限於和現實之物相同。說明書及圖面中，有關已揭露之圖面，對於和前述者相同的要素係標記同一符號並適當省略詳細說明。
(第1實施形態)　圖1為按照第1實施形態之半導體裝置的構成例示意截面圖。半導體裝置1，具備配線基板10、半導體晶片20、30～33、接著層40～43、間隔片(spacer chip)50、接著層60、金屬材料70、樹脂層80、打線90、密封樹脂91。半導體裝置1，例如為NAND型快閃記憶體的封裝。
配線基板10，可為包含配線層11與絕緣層15之印刷基板或中介板(interposer)。在配線層11，例如使用銅、鎳或它們的合金等的低電阻金屬。在絕緣層15，例如使用玻璃環氧樹脂等的絕緣性材料。圖中，僅在絕緣層15的表面與背面設有配線層11。但，配線基板10亦可具有將複數個配線層11及複數個絕緣層15予以層積而構成之多層配線構造。配線基板10，例如亦可像中介板般具有貫通其表面與背面之貫通電極12。
在配線基板10的表面，設有設於配線層11上之阻焊劑層14。阻焊劑層14，為用來保護配線層11不受金屬材料70影響，而抑制短路不良之絕緣層。在阻焊劑層14設有開口部OP，配線層11的一部分及絕緣層15從開口部OP露出。
在配線基板10的背面，亦設有設於配線層11上之阻焊劑層14。在從阻焊劑層14露出的配線層11，設有金屬凸塊13。金屬凸塊13，被設置用來將未圖示的其他零件與配線基板10予以電性連接。
半導體晶片20，例如為控制記憶體晶片的控制器晶片。在半導體晶片20的表面，設有未圖示的半導體元件。半導體元件，例如可為構成控制器的CMOS (Complementary Metal Oxide Semiconductor；互補式金屬氧化物半導體)電路。在半導體晶片20的背面，設有與半導體元件電性連接之電極柱21。在電極柱21，例如使用銅、鎳或它們的合金等的低電阻金屬材料。
電極柱21，被插入至配線基板10的開口部OP，電極柱21的下端部被配置於比開口部OP的上端還低的位置。在電極柱21的周圍，設有金屬材料70。電極柱21，透過金屬材料70而於開口部OP與露出的配線層11電性連接。
金屬材料70，被埋入配線基板10的開口部OP內，將在開口部OP內露出的配線層11予以被覆。在金屬材料70，例如使用焊料、銀、銅等的低電阻金屬材料。金屬材料70，如後述般是以液體或膏狀的金屬材料的方式被供給，其後硬化而形成。金屬材料70，在開口部OP內被覆配線基板10的配線層11，且亦被覆半導體晶片20的電極柱21的側面。藉此，金屬材料70能夠將半導體晶片20的電極柱21與配線基板10的配線層11予以電性連接。電極柱21，和配線層11相隔距離而無直接接觸。亦即，在電極柱21與配線層11之間介著金屬材料70。
在半導體晶片20的周圍、及半導體晶片20與配線基板10之間，設有樹脂層(底部填充劑；underfill) 80。樹脂層80，例如為使NCP(Non Conductive Paste)硬化而成之物，將半導體晶片20的周圍予以被覆保護。
在半導體晶片20的上方，透過接著層40接著有半導體晶片30。半導體晶片30，例如為包含NAND型快閃記憶體的記憶體晶片。半導體晶片30，在其表面具有半導體元件(未圖示)。半導體元件，例如可為記憶體單元陣列及其周邊電路(CMOS電路)。記憶體單元陣列，亦可為將複數個記憶體單元三維配置而成之立體型記憶體單元陣列。此外，在半導體晶片30上，透過接著層41接著有半導體晶片31。在半導體晶片31上，透過接著層42接著有半導體晶片32。在半導體晶片32上，透過接著層43接著有半導體晶片33。半導體晶片31～33，例如如同半導體晶片30般，例如為包含NAND型快閃記憶體的記憶體晶片。半導體晶片30～33亦可為同一的記憶體晶片。圖中，除了作為控制器晶片的半導體晶片20外，還層積有作為4個記憶體晶片的半導體晶片30～33。但，半導體晶片的層積數可為3以下，亦可為5以上。
半導體晶片30比半導體晶片20還大，半導體晶片30的外緣位於半導體晶片20的外緣的外側。於半導體晶片20的周圍，在半導體晶片30與配線基板10的阻焊劑層14之間，設有間隔片50。間隔片50，透過接著層60接著於阻焊劑層14上。此外，在間隔片50的上面接著有接著層40，半導體晶片30透過接著層40而接著於間隔片50的上面。
打線90，連接至配線基板10、半導體晶片30～33的任意的焊墊。為了以打線90連接，半導體晶片30～33係錯開恰好焊墊的份量而被層積。另，半導體晶片20是藉由電極柱21而被覆晶連接，故未被打線接合。但，半導體晶片20亦可除電極柱21所做的連接外再加上打線接合。
又，密封樹脂91，將半導體晶片20、30～33、間隔片50、樹脂層80、打線90等予以密封。藉此，半導體裝置1，將複數個半導體晶片20、30～33於配線基板10上構成作為1個半導體封裝。
圖2為圖1的框B1的構成示意擴大截面圖。圖3為阻焊劑層、開口部、配線層及電極柱的位置關係示意俯視圖。在阻焊劑層14設有開口部OP，配線層11的一部分係露出。金屬材料70，被埋入開口部OP內，與配線層11的一部分接觸。電極柱21被插入至金屬材料70內，透過金屬材料70電性連接至配線層11。
電極柱21的下端部21b，往開口部OP內被插入。故，電極柱21的下端部21b的高度H21，位於比阻焊劑層14的上面14a的高度H14還下方。藉此，電極柱21接觸而被插入至充填於開口部OP內的液體或膏狀的金屬材料70內。金屬材料70，從電極柱21的下端部21b循著側面攀上，從開口部OP的上端往斜上方至電極柱21的側面為止具有推拔。像這樣，金屬材料70沿著電極柱21的側面從開口部OP隆起。金屬材料70，沿著電極柱21的側面從開口部OP隆起和被插入開口部OP的電極柱21的體積恰好相同或其以上的份量。金屬材料70以接觸電極柱21的側面之方式從開口部OP隆起，藉此，金屬材料70與電極柱21之間的接觸電阻會變小。
圖2中，電極柱21的下端部21b的高度H21位於比阻焊劑層14的高度H14還低，且比配線層11的上面11a的高度H11還高的位置。但，電極柱21的下端部21b的高度H21，亦可位於比配線層11的上面11a的高度H11還低的位置。又，電極柱21的下端部21b，亦可接觸配線基板10的絕緣層15的上面15a。在電極柱21的正下方未設有配線層11，故電極柱21的下端部21b能夠接觸絕緣層15的上面15a。亦即，下端部21b的高度H21，亦可和絕緣層15的表面的高度相等。像這樣，電極柱21的下端部21b，只要位於比阻焊劑層14的高度H14還低的位置，則可置放於任意的位置。電極柱21的下端部21b愈接近絕緣層15的上面15a，則半導體晶片20愈接近配線基板10，能夠減薄半導體裝置1的封裝的厚度。是故，電極柱21的下端部21b，可以說愈接近絕緣層15的上面15a愈好。
此外，在電極柱21的正下方不存在配線層11，而設有金屬材料70。如圖3所示，從半導體晶片20的搭載方向(圖2的Z方向的上方)觀看時，電極柱21與配線層11相隔距離，在電極柱21與配線層11之間介著作為「導電材料」的金屬材料70。
配線層11的一部分，從上述搭載方向觀看時，係從開口部OP的側面朝向開口部OP的中心部突出。藉此，配線部11與金屬材料70之接觸面積會變大，配線部11與金屬材料70之間的接觸電阻會變小。
本實施形態中，將液體或膏狀的金屬材料(例如焊料膏、銅或銀膏、銅或銀奈米墨水等)70事先充填於開口部OP內，而將半導體晶片20的電極柱21插入(浸漬)於開口部OP內的金屬材料70。藉此，能夠抑制在開口部OP內產生孔隙，而抑制電極柱21與配線層11之接觸不良。
此外，於俯視佈局下，電極柱21不與配線層11重複，而和配線層11相隔距離。亦即，於俯視佈局下，電極柱21不和配線層11干涉。藉此，電極柱21的下端部21b的高度H21，能夠做成比配線層11的上面11a的高度H11還低。又，電極柱21的下端部21b，亦可到達絕緣層15的上面15a。藉由將電極柱21的下端部21b趨近絕緣層15的上面15a，能夠減薄半導體裝置1的封裝的厚度。
接下來說明按照本實施形態之半導體裝置1的製造方法。
圖4～圖15為按照第1實施形態之半導體裝置的製造方法的一例示意圖。首先，在半導體晶圓W形成半導體元件。圖4為形成有半導體元件的半導體晶圓W的立體圖。在半導體晶圓W上形成有半導體元件，聚醯亞胺PI被覆半導體元件。半導體晶圓W，包含於後述的切割工程會被分片化之複數個半導體晶片20(或30～33)。
接下來如圖5所示，在聚醯亞胺PI上貼附保護膠帶TP1。接下來將保護膠帶TP1面朝下，將半導體晶圓W的背面以磨床G研磨。
將保護膠帶TP1剝離後，如圖7所示，將半導體晶圓W的背面貼附於撐開在晶圓環WR內的可撓性的樹脂膠帶TP2。接下來，使用雷射振盪器LG，沿著半導體晶圓W的表面或背面的切割線照射雷射光。藉此，在切割線形成溝(groove)。
接下來如圖9所示，以切割刀DB沿著切割線的溝將半導體晶圓W切斷。藉此，半導體晶圓W被分片化成半導體晶片20(或30～33)。被分片化的半導體晶片20(或30～33)，為了被組裝至配線基板10，而從樹脂膠帶TP2被拾取。
另一方面，配線基板10中，形成絕緣層15、配線層11、貫通電極12、阻焊劑層14。接下來使用形成於阻焊劑層14上的遮罩材M1，在阻焊劑層14形成開口部OP。此時，開口部OP是以將配線層11及其周邊的絕緣層15露出之方式形成。
接下來雖未圖示，但塗布助焊劑將於開口部OP露出的配線層11的表面的氧化膜除去。接下來將配線基板10做熱處理，進行電漿處理。接下來如圖10所示，在配線基板10的表面及開口部OP供給液體或膏狀的金屬材料70。液體或膏狀的金屬材料70，將於開口部OP露出的配線層11被覆。
接下來如圖11所示，在配線基板10的遮罩材M1的表面上以工具100掃掠。工具100，例如可為由樹脂、金屬等所成之板狀的刮刀。以工具100在配線基板10上往A1方向掃掠，藉此如圖12所示，使液體或膏狀的金屬材料70充填於開口部OP，同時將剩餘的金屬材料70從配線基板10除去。A1方向，相對於配線基板10的表面為略平行方向。亦即，刮板工具100一面在配線基板10上往A1方向掃掠，使金屬材料70殘留在開口部OP內，且將剩餘的金屬材料70拭取以便從配線基板10除去。藉此，如圖13所示，金屬材料70便被充填於開口部OP內。金屬材料70幾乎不會留在遮罩材M1上。此外，即使金屬材料70留在遮罩材M1上，藉由除去遮罩材M1，金屬材料70便可從阻焊劑層14上被除去。另，亦可將金屬材料70迴焊，以使金屬材料70在開口部OP內更確實地充填。
接下來拾取圖9所示工程中形成的半導體晶片20，將半導體晶片20的電極柱21插入開口部OP內的金屬材料70。此時，液體或膏狀的金屬材料70若接觸電極柱21的下端部，則從該下端部循著側面攀上。故，金屬材料70會以從開口部OP的上端往斜上方至電極柱21的側面為止具有推拔之方式形成。藉此，金屬材料70沿著電極柱21的側面從開口部OP隆起。金屬材料70，沿著電極柱21的側面從開口部OP隆起和被插入開口部OP的電極柱21的體積恰好相同或其以上的份量。金屬材料70以接觸電極柱21的側面之方式從開口部OP隆起，藉此，金屬材料70與電極柱21之間的接觸電阻會變小。
另，電極柱21的下端部只要比阻焊劑層14的上面還低即可。亦即，電極柱21的下端部亦可被插入至比配線層11的上面還下方，亦可僅被插入至比配線層11的上面還高的位置。這是因為電極柱21即使不和配線層11直接接觸，也能透過金屬材料70電性連接至配線層11。
又，如參照圖3說明般，在電極柱21的正下方不存在配線層11。故，從半導體晶片20的搭載方向觀看時，電極柱21與配線層11相隔距離，在電極柱21與配線層11之間介著金屬材料70。像這樣，即使在電極柱21的正下方未設有配線層11，電極柱21也能透過金屬材料70電性連接至配線層11。
電極柱21的下端部，亦可接觸絕緣層15的上面。藉此，半導體晶片20與配線基板10之距離會變近，能夠減薄半導體裝置1的封裝的厚度。
接下來將配線基板10烘烤而使液體或膏狀的金屬材料70的溶劑揮發。電極柱21與金屬材料70藉由金屬擴散而連接。一旦烘烤結束，金屬材料70會比烘烤前更硬化。藉此，相對於配線基板10之半導體晶片20的位置便幾乎決定。
接下來如圖15所示，樹脂層80被供給至半導體晶片20。樹脂層80例如為底部填充(underfill)材，侵入半導體晶片20與配線基板10之間，而將金屬材料70的周圍及半導體晶片20的側面予以被覆。接下來在半導體晶片20的周邊的配線基板10上透過接著層60將間隔片50接著。間隔片50的上面的高度，較佳是和半導體晶片20的上面的高度幾乎相等。藉此，層積於半導體晶片20上的半導體晶片30～33的平坦性會提升。
其後如圖1所示，將在背面貼附有接著層40的半導體晶片30搭載於半導體晶片20上，將在背面貼附有接著層41的半導體晶片31搭載於半導體晶片30上，將在背面貼附有接著層42的半導體晶片32搭載於半導體晶片31上，將在背面貼附有接著層43的半導體晶片33搭載於半導體晶片32上。
接下來以打線90連接半導體晶片30～33的焊墊及配線基板10上的焊墊。又，以密封樹脂91將半導體晶片20、30～33、打線90等予以密封，得到圖1所示的構造。
像以上這樣，本實施形態中，將膏狀的金屬材料(例如焊料膏)70供給至配線基板10上之後，以工具100拭取金屬材料70。藉此，將金屬材料70充填於開口部OP內。其後，將半導體晶片20的電極柱21插入開口部OP內的金屬材料70。
如果事先在電極柱21形成焊料凸塊，而將此焊料凸塊覆晶連接至配線基板10的情形下，覆晶連接是一面對連接部供給助焊劑一面執行，以便除去凸塊表面的氧化膜。此時，由於助焊劑的流動，在開口部OP的內部或電極柱21的周圍會發生孔隙(內包(involved)孔隙)。
相對於此，本實施形態中，是對事先充填於開口部OP內的金屬材料(焊料)70插入電極柱21。故，覆晶連接時，開口部OP已經以金屬材料70充填，故在開口部OP的內部或電極柱21的周圍不會發生孔隙。此外，不必使焊料凸塊事先附著於電極柱21，覆晶連接時不需要助焊劑的供給。是故，能夠抑制在開口部OP的內部或電極柱21的周圍發生內包孔隙。
(第2實施形態)　圖16為按照第2實施形態之半導體晶片與配線基板之連接部分的構成例示意擴大截面圖。圖17為按照第2實施形態之阻焊劑層、開口部、配線層及電極柱的位置關係示意俯視圖。第2實施形態中，配線層11的一部分面向開口部OP的內面，於該內面露出。亦即如圖16所示，配線層11未對開口部OP突出，僅是面向。即使是這樣的構成，金屬材料70也能接觸配線層11，能夠將電極柱21與配線層11電性連接。
第2實施形態的其他構成，可和第1實施形態的相對應之構成同樣。是故，第2實施形態能夠獲得和第1實施形態同樣的效果。
(第3實施形態)　圖18為按照第3實施形態之半導體晶片與配線基板之連接部分的構成例示意擴大截面圖。按照第3實施形態，電極柱21的下端部21b的高度H21，位於比配線層11的上面11a的高度H11還下方。藉此，金屬材料70和電極柱21的側面能夠以比較廣的面積接觸。故，金屬材料70與電極柱21之間的接觸電阻會變更小。第3實施形態的其他構成，可和第1實施形態的相對應之構成同樣。藉此，第3實施形態能夠獲得和第1實施形態同樣的效果。此外，第3實施形態亦可與第2實施形態組合。
(第4實施形態)　圖19為按照第4實施形態之半導體晶片與配線基板之連接部分的構成例示意擴大截面圖。按照第4實施形態，電極柱21的下端部21b接觸絕緣層(預浸材)15的上面15a。亦即，下端部21b的高度H21和配線基板10的絕緣層15的上面15a幾乎相等。藉此，金屬材料70和電極柱21的側面能夠以更廣的面積接觸。故，金屬材料70與電極柱21之間的接觸電阻會變更小。第4實施形態的其他構成，可和第1實施形態的相對應之構成同樣。藉此，第4實施形態能夠獲得和第1實施形態同樣的效果。此外，第4實施形態亦可與第2實施形態組合。
(第5實施形態)　第1至第4實施形態中，如圖13～圖15所示般，係將半導體晶片20與配線基板10連接之後進行樹脂層80的供給。但，第5實施形態中，係將金屬材料70設置於配線基板10之後，對配線基板10供給NCP(非導電性膏)作為樹脂層80。其後一面將半導體晶片20與配線基板10加熱一面抵壓使其連接。此時，位於配線基板10與半導體晶片20之間的NCP，會藉由加熱與抵壓而流動，從配線基板10與半導體晶片20之間漏出而攀上半導體晶片20的側面。是故，本實施形態中同樣地半導體晶片20與配線基板10與樹脂層80會成為如圖1所示般的形態。在此情形下亦能夠獲得和第1～第4實施形態同樣的效果。
(第6實施形態)　第6實施形態中，講述使用(非導電性膜)來取代使用NCP的連接方法。本實施形態中，將金屬材料70設置於配線基板10。將NCF(非導電性膜)作為樹脂層80而設置於半導體晶片20的形成有電極柱21的面。其後一面將半導體晶片20與配線基板10加熱一面抵壓使其連接。此時，位於配線基板10與半導體晶片20之間的NCF，會藉由加熱與抵壓而流動，從配線基板10與半導體晶片20之間漏出而攀上半導體晶片20的側面。是故，本實施形態中同樣地半導體晶片20與配線基板10與樹脂層80會成為如圖1所示般的形態。在此情形下亦能夠獲得和第1至第5實施形態同樣的效果。
(其他實施形態)　(a)上述實施形態中，金屬材料70是藉由使用刮板而被設置於配線基板10的開口部OP。除此外，金屬材料70亦可以網版印刷、點膠機、噴墨等各式各樣的方法而被設置於開口部OP。在此情形下亦能夠獲得和上述實施形態同樣的效果。(b)上述實施形態中，將電極柱21插入開口部OP內的金屬材料70時，亦可一面加熱半導體晶片20或配線基板10一面進行。在此情形下亦能夠獲得和上述實施形態同樣的效果。(c)上述實施形態中，亦可使用導電性的樹脂等(例如PEDOT：PSS等)來取代金屬材料70。在此情形下亦能夠獲得和上述實施形態同樣的效果。此外，取代金屬材料70的只要是導電性材料則可使用任意物。
雖已說明了本發明的幾個實施形態，但該些實施形態僅是提出作為例子，並非意圖限定發明的範圍。該些實施形態，可以其他各種形態來實施，在不脫離發明要旨之範圍內，可進行種種省略、置換、變更。該些實施形態或其變形，均包含於發明之範圍或要旨中，同樣地包含於申請專利範圍所記載之發明及其均等範圍內。
1:半導體裝置 10:配線基板 11:配線層 11a:配線層11的上面 12:貫通電極 13:金屬凸塊 14:阻焊劑層 14a:阻焊劑層14的上面 15:絕緣層 15a:絕緣層15的上面 20,30~33:半導體晶片 21:電極柱 21b:電極柱21的下端部 40~43:接著層 50:間隔片 60:接著層 70:金屬材料 80:樹脂層 90:打線 91:密封樹脂 100:工具 DB:切割刀 G:磨床 LG:雷射振盪器 M1:遮罩材 OP:開口部 PI:聚醯亞胺 TP1:保護膠帶 TP2:樹脂膠帶 W:半導體晶圓
[圖1]按照第1實施形態之半導體裝置的構成例示意截面圖。 [圖2]圖1的框B1的構成示意擴大截面圖。 [圖3]阻焊劑層、開口部、配線層及電極柱的位置關係示意俯視圖。 [圖4]按照第1實施形態之半導體裝置的製造方法的一例示意圖。 [圖5]接續圖4之半導體裝置的製造方法的一例示意圖。 [圖6]接續圖5之半導體裝置的製造方法的一例示意圖。 [圖7]接續圖6之半導體裝置的製造方法的一例示意圖。 [圖8]接續圖7之半導體裝置的製造方法的一例示意圖。 [圖9]接續圖8之半導體裝置的製造方法的一例示意圖。 [圖10]接續圖9之半導體裝置的製造方法的一例示意圖。 [圖11]接續圖10之半導體裝置的製造方法的一例示意圖。 [圖12]接續圖11之半導體裝置的製造方法的一例示意圖。 [圖13]接續圖12之半導體裝置的製造方法的一例示意圖。 [圖14]接續圖13之半導體裝置的製造方法的一例示意圖。 [圖15]接續圖14之半導體裝置的製造方法的一例示意圖。 [圖16]按照第2實施形態之半導體晶片與配線基板之連接部分的構成例示意擴大截面圖。 [圖17]按照第2實施形態之阻焊劑層、開口部、配線層及電極柱的位置關係示意俯視圖。 [圖18]按照第3實施形態之半導體晶片與配線基板之連接部分的構成例示意擴大截面圖。 [圖19]按照第4實施形態之半導體晶片與配線基板之連接部分的構成例示意擴大截面圖。
10:配線基板
11:配線層
11a:配線層11的上面
14:阻焊劑層
14a:阻焊劑層14的上面
15:絕緣層
15a:絕緣層15的上面
20:半導體晶片
21:電極柱
21b:電極柱21的下端部
70:金屬材料
80:樹脂層
OP:開口部

Claims (18)

  1. 一種半導體裝置，具備：配線基板，包含配線層與設於該配線層上的絕緣層，於設於前述絕緣層的開口部使前述配線層的一部分露出；及 導電材料，被埋入前述開口部，被覆該開口部內的前述配線層；及 半導體晶片，具有被插入前述開口部內而連接至前述導電材料之電極； 從前述半導體晶片的搭載方向觀看時，前述電極與前述配線層相隔距離，在前述電極與前述配線層之間介著前述導電材料。
  2. 如請求項1記載之半導體裝置，其中，前述電極的下端，位於比前述配線層的上面還下方。
  3. 如請求項1記載之半導體裝置，其中，前述電極的下端，位於比前述配線層的上面還上方。
  4. 如請求項1記載之半導體裝置，其中，從前述搭載方向觀看時，前述配線層的一部分從前述開口部突出。
  5. 如請求項1記載之半導體裝置，其中，前述配線層的一部分面向前述開口部的內面，於該內面露出。
  6. 如請求項1至5中任一項記載之半導體裝置，其中，前述導電材料，沿著前述電極的側面從前述開口部隆起。
  7. 如請求項6記載之半導體裝置，其中，前述導電材料，沿著前述電極的側面從前述開口部隆起和被插入前述開口部的前述電極的體積恰好相同或其以上的份量。
  8. 如請求項1記載之半導體裝置，其中，前述電極接觸前述配線基板的前述開口部的底部。
  9. 如請求項1記載之半導體裝置，其中，在前述配線層及前述電極，使用銅、鎳或它們的合金， 在前述導電材料，使用焊料、銀、銅。
  10. 一種半導體裝置的製造方法，具備：對包含配線層與設於該配線層上之絕緣層，以露出前述配線層的一部分之方式設於該絕緣層的開口部供給液體或膏狀的導電材料， 將設於半導體晶片的電極插入前述開口部內的前述導電材料而使前述導電材料硬化。
  11. 如請求項10記載之半導體裝置的製造方法，其中，從前述半導體晶片的搭載方向觀看時，前述電極與前述配線層相隔距離，前述導電材料位在前述電極與前述配線層之間。
  12. 如請求項10記載之半導體裝置的製造方法，其中，前述電極的下端，被插入至比前述配線層的上面還下方。
  13. 如請求項10記載之半導體裝置的製造方法，其中，前述電極的下端，被插入至比前述配線層的上面還上方。
  14. 如請求項10記載之半導體裝置的製造方法，其中，前述電極以接觸前述配線基板的前述開口部的底部之方式被插入。
  15. 如請求項10記載之半導體裝置的製造方法，其中，在前述配線層及前述電極，使用銅、鎳或它們的合金， 在前述導電材料，使用焊料、銀膏、銅膏。
  16. 如請求項10至15中任一項記載之半導體裝置的製造方法，其中，對前述配線基板的表面上供給前述導電材料而在前述配線基板的表面上以工具掃掠，藉此使前述導電材料充填前述開口部，同時將剩餘的前述導電材料從前述配線基板除去，藉此導電材料被供給至前述開口部。
  17. 如請求項10至15中任一項記載之半導體裝置的製造方法，其中，在將設於半導體晶片的電極插入前述開口部內的前述導電材料之前， 絕緣樹脂被供給至前述配線基板與前述半導體晶片之間。
  18. 如請求項10至15中任一項記載之半導體裝置的製造方法，其中，在將設於半導體晶片的電極插入前述開口部內的前述導電材料之後， 絕緣樹脂被供給至前述配線基板與前述半導體晶片之間。
TW109126855A 2020-02-07 2020-08-07 半導體裝置及其製造方法 TWI758815B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2020-019933 2020-02-07
JP2020019933A JP2021125643A (ja) 2020-02-07 2020-02-07 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
TW202131418A true TW202131418A (zh) 2021-08-16
TWI758815B TWI758815B (zh) 2022-03-21

Family

ID=77178295

Family Applications (1)

Application Number Title Priority Date Filing Date
TW109126855A TWI758815B (zh) 2020-02-07 2020-08-07 半導體裝置及其製造方法

Country Status (4)

Country Link
US (1) US11482502B2 (zh)
JP (1) JP2021125643A (zh)
CN (1) CN113257772A (zh)
TW (1) TWI758815B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9627367B2 (en) * 2014-11-21 2017-04-18 Micron Technology, Inc. Memory devices with controllers under memory packages and associated systems and methods

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07112041B2 (ja) * 1986-12-03 1995-11-29 シャープ株式会社 半導体装置の製造方法
JP2716336B2 (ja) * 1993-03-10 1998-02-18 日本電気株式会社 集積回路装置
JP2751912B2 (ja) * 1996-03-28 1998-05-18 日本電気株式会社 半導体装置およびその製造方法
JP4631223B2 (ja) * 2001-07-04 2011-02-16 パナソニック株式会社 半導体実装体およびそれを用いた半導体装置
JP2004014854A (ja) * 2002-06-07 2004-01-15 Shinko Electric Ind Co Ltd 半導体装置
JP4387231B2 (ja) * 2004-03-31 2009-12-16 新光電気工業株式会社 キャパシタ実装配線基板及びその製造方法
TWI278081B (en) 2005-12-22 2007-04-01 Siliconware Precision Industries Co Ltd Electronic carrier board and package structure thereof
KR20080042012A (ko) * 2006-11-08 2008-05-14 산요덴키가부시키가이샤 소자 탑재용 기판, 그 제조 방법, 반도체 모듈 및 휴대기기
JP5215605B2 (ja) * 2007-07-17 2013-06-19 ラピスセミコンダクタ株式会社 半導体装置の製造方法
JP5378707B2 (ja) * 2008-05-29 2013-12-25 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US20110174527A1 (en) * 2008-06-30 2011-07-21 Masayuki Nagamatsu Element mounting board, semiconductor module, semiconductor device, method for fabricating the element mounting board, and method for fabricating semiconductor device
JP5547615B2 (ja) * 2010-11-15 2014-07-16 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
JP2014123592A (ja) 2012-12-20 2014-07-03 Ibiden Co Ltd プリント配線板の製造方法及びプリント配線板
US20140183744A1 (en) * 2012-12-28 2014-07-03 Texas Instruments Incorporated Package substrate with bondable traces having different lead finishes
KR102111739B1 (ko) * 2013-07-23 2020-05-15 삼성전자주식회사 반도체 패키지 및 그 제조방법
WO2015011284A2 (en) 2013-07-25 2015-01-29 Fondazione Telethon Inhibitors of fapp2 and uses thereof
JP6547745B2 (ja) 2014-06-27 2019-07-24 ソニー株式会社 半導体装置およびその製造方法
JP6220799B2 (ja) 2015-02-03 2017-10-25 新光電気工業株式会社 配線基板及びその製造方法
JP6609633B2 (ja) * 2015-10-15 2019-11-20 ルネサスエレクトロニクス株式会社 半導体装置

Also Published As

Publication number Publication date
US11482502B2 (en) 2022-10-25
TWI758815B (zh) 2022-03-21
JP2021125643A (ja) 2021-08-30
CN113257772A (zh) 2021-08-13
US20210249373A1 (en) 2021-08-12

Similar Documents

Publication Publication Date Title
US8575763B2 (en) Semiconductor device and method of manufacturing the same
KR100621438B1 (ko) 감광성 폴리머를 이용한 적층 칩 패키지 및 그의 제조 방법
TWI277187B (en) Semiconductor device and manufacturing method for the same
US20140295620A1 (en) Method of manufacturing semiconductor device having plural semiconductor chips stacked one another
KR100652242B1 (ko) 플립칩형 반도체장치, 이의 제조를 위한 제조방법 및 이런 플립칩형 반도체장치를 사용하여 전자제품을 제조하기 위한 제조방법
TWI550729B (zh) Semiconductor device manufacturing method and semiconductor device
JP4992904B2 (ja) 半導体装置の製造方法
JP2014063974A (ja) チップ積層体、該チップ積層体を備えた半導体装置、及び半導体装置の製造方法
JPWO2008038345A6 (ja) 半導体装置の製造方法
KR20180037238A (ko) 반도체 장치 및 그 제조 방법
JP2016062995A (ja) 半導体装置および半導体装置の製造方法
TW201128721A (en) Manufacturing method of semiconductor device
TWI627689B (zh) 半導體裝置
TW201535541A (zh) 半導體裝置之製造方法及半導體裝置
JP2013168577A (ja) 半導体装置の製造方法
JPWO2005076352A1 (ja) 半導体装置および半導体装置の製造方法
JP2012221989A (ja) 半導体装置製造装置、及び半導体装置の製造方法
CN112447620A (zh) 半导体装置及其制造方法
TWI758815B (zh) 半導體裝置及其製造方法
JP5547703B2 (ja) 半導体装置の製造方法
JP2008258318A (ja) 半導体チップ及びその実装方法、半導体装置
JP2005340450A (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
JP2013110188A (ja) 半導体装置及びその製造方法
JP2012138394A (ja) 半導体装置の製造方法
JP2003297977A (ja) 電子部品の製造方法