JP2013110188A - 半導体装置及びその製造方法 - Google Patents
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Abstract
【解決手段】絶縁基材11の表面上に導電箔12が配置され、導電箔12を覆って、その一部を露出する複数の第1の開口部17A、及び複数の第2の開口部17Bを有する保護膜17が配置されている。各第1の開口部17Aで露出する導電箔12の表面上に導電突起体14が配置される。表面に複数のパッド電極12を有した半導体チップ20は、その裏面が複数の導電突起体14と対向するように、ダイボンドペースト15を介して保護膜17上に固着される。各第2の開口部17Bで露出する導電箔12は、それぞれボンディングワイヤを介してパッド電極21と接続される。絶縁基材11の表面上の半導体チップ20等は、封止材16に覆われて封止される。
【選択図】図2
Description
絶縁基材11の表面上の導電箔12、第1の保護膜17、半導体チップ20、複数のボンディングワイヤ13を、封止材16で覆って封止する。
12 導電箔(配線パターン) 13 ボンディングワイヤ
14 導電突起体 15 ダイボンドペースト
16 封止材 17 第1の保護膜
17A 第1の開口部 17B 第2の開口部
18 第2の保護膜 20 半導体チップ
21 パッド電極 22 裏面電極
Claims (6)
- 絶縁基材と、
前記絶縁基材の表面上に配線パターンとして配置された導電箔と、
前記導電箔の一部を露出する複数の第1の開口部、及び複数の第2の開口部を有し、前記導電箔を含む前記絶縁基材の表面を覆う保護膜と、
前記複数の第1の開口部で露出する前記導電箔の表面上に配置された複数の導電突起体と、
表面に複数のパッド電極を有し、裏面が前記複数の導電突起体と対向して直接接するように、ダイボンドペーストを介して前記保護膜上に固着された半導体チップと、
前記複数の第2の開口部で露出する前記導電箔と前記複数のパッド電極をそれぞれ接続する複数のボンディングワイヤと、
前記絶縁基材の表面上の前記導電箔、前記保護膜、前記半導体チップ、前記複数のボンディングワイヤを覆って封止する封止材と、を備え、
前記複数の第1の開口部において、前記導電箔と前記導電突起体からなる積層体は、前記半導体チップを前記絶縁基材の表面に対して平行に支持する高さを有することを特徴とする半導体装置。 - 前記保護膜は有機樹脂を含むソルダーレジストであることを特徴とする請求項1に記載の半導体装置。
- 前記絶縁基板を貫通するビアホールを備え、前記導電箔は前記ビアホールを通して前記絶縁基材の裏面上に延在することを特徴とする請求項1または請求項2に記載の半導体装置。
- 前記導電箔は、銅を含む金属材料を用いたメッキ膜からなることを特徴とする請求項1乃至請求項3のいずれかに記載の半導体装置。
- 表面に配線パターンとして導電箔が形成され、前記導電箔の一部を露出する複数の第1の開口部及び複数の第2の開口部を有して前記導電箔を覆う保護膜が形成された絶縁基材と、表面に複数のパッド電極を有した半導体チップと、を準備し、
前記複数の第1の開口部で露出する前記導電箔の表面上に複数の導電突起体を形成する工程と、
前記導電突起体の形成工程の後、前記保護膜上にダイボンドペーストを形成する工程と、
前記ダイボンドペーストの塗布工程の後、前記半導体チップを、その裏面が前記複数の導電突起体と対向して直接接するように前記保護膜上に圧着し、前記ダイボンドペーストを介して固着する工程と、
ワイヤボンダーによって形成される複数のボンディングワイヤを介して、前記複数の第2の開口部で露出する前記導電箔と前記複数のパッド電極をそれぞれ接続する工程と、
前記絶縁基材の表面上の前記導電箔、前記保護膜、前記半導体チップ、前記複数のボンディングワイヤを、封止材で覆って封止する工程と、を備え、
前記複数の第1の開口部において、前記導電箔と前記導電突起体からなる積層体は、前記半導体チップを前記絶縁基材の表面に対して平行に支持する高さを有することを特徴とする半導体装置の製造方法。 - 前記導電突起体を形成する工程は、前記ワイヤボンダーにより、溶融した金属材料を前記第1の開口部で露出する前記導電箔の表面上に点状に溶着する工程を含むことを特徴とする請求項5に記載の半導体装置の製造方法。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015095489A (ja) * | 2013-11-08 | 2015-05-18 | 新光電気工業株式会社 | 半導体装置 |
EP3244445A1 (en) * | 2016-05-10 | 2017-11-15 | Rosemount Aerospace Inc. | Method to provide die attach stress relief using gold stud bumps |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US6127724A (en) * | 1996-10-31 | 2000-10-03 | Tessera, Inc. | Packaged microelectronic elements with enhanced thermal conduction |
JP2008141109A (ja) * | 2006-12-05 | 2008-06-19 | Kyocer Slc Technologies Corp | 配線基板およびその製造方法 |
JP2009054747A (ja) * | 2007-08-27 | 2009-03-12 | Fujitsu Microelectronics Ltd | 半導体装置及びその製造方法 |
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6127724A (en) * | 1996-10-31 | 2000-10-03 | Tessera, Inc. | Packaged microelectronic elements with enhanced thermal conduction |
JP2008141109A (ja) * | 2006-12-05 | 2008-06-19 | Kyocer Slc Technologies Corp | 配線基板およびその製造方法 |
JP2009054747A (ja) * | 2007-08-27 | 2009-03-12 | Fujitsu Microelectronics Ltd | 半導体装置及びその製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015095489A (ja) * | 2013-11-08 | 2015-05-18 | 新光電気工業株式会社 | 半導体装置 |
EP3244445A1 (en) * | 2016-05-10 | 2017-11-15 | Rosemount Aerospace Inc. | Method to provide die attach stress relief using gold stud bumps |
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