TWI395316B - 多晶片模組封裝件 - Google Patents
多晶片模組封裝件 Download PDFInfo
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- TWI395316B TWI395316B TW096137018A TW96137018A TWI395316B TW I395316 B TWI395316 B TW I395316B TW 096137018 A TW096137018 A TW 096137018A TW 96137018 A TW96137018 A TW 96137018A TW I395316 B TWI395316 B TW I395316B
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- wafer
- conductive adhesive
- module package
- chip module
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Description
本發明係有關於多晶片模組封裝件,尤指具有切換晶片及驅動晶片之多晶片模組封裝件。
智慧型電源切換(Smart Power Switching:SPS)封裝件係為一種應用於電子產品的電源設備,其通常包括電晶體及控制積體電路,其中,所述電晶體係為切換晶片,所述控制積體電路係為驅動晶片。
鑑於習知智慧型電源切換封裝件之多種缺失,美國專利號6,756,689揭示一種如第5圖所示之封裝結構。該封裝結構5包括一導線架之晶片座50。切換晶片51及驅動晶片52分別透過導電黏著劑53及絕緣黏著膠帶54設置於該晶片座50上。
惟,此封裝結構5存在諸多缺點。例如,由於導電黏著劑53與絕緣黏著膠帶54係由不同的材料製成,在將絕緣黏著膠帶54接置於晶片座50之前須先執行一固化製程以固化導電黏著劑53,如此不僅增加了封裝結構5之製程的複雜度,而且提高了製程成本。並且由於導電黏著劑53與絕緣黏著膠帶54之材料不同,其熱膨脹系數(Coefficient of Thermal Expansion:CTE)的不匹配導致隨後的溫度循環中不同的熱應力施加於切換晶片51及驅動晶片52上,從而影響封裝結構5之信賴性。此外,切換晶片51及驅動晶片52係共平面接置於晶片座50上,因而要求晶片座50之尺寸必須足夠晶片接置。然而晶片座50之尺寸愈大,則來自晶片座50的熱應力愈大,如此容易使晶片座50與封裝膠體55之間發生脫層現象,嚴重影響封裝結構5之信賴性。
如第6圖所示,美國專利號6,756,689復揭示另一種封裝結構6,包括:晶片座60;透過導電黏著劑62設置於該晶片座60上之切換晶片61;透過絕緣黏著膠帶64堆曡於該切換晶片61上之驅動晶片63;以及包覆晶片座60、切換晶片61及驅動晶片63之封裝膠體65。
此封裝結構係將驅動晶片63堆曡於切換晶片61上而相對縮小晶片座60之尺寸,以避免脫層問題。然而由於導電黏著劑62與絕緣黏著膠帶64係由不同的材料製成,在將絕緣黏著膠帶64接置於切換晶片61之前仍須先執行固化製程以固化導電黏著劑62。而且由於習知固化製程通常會污染供接置絕緣黏著膠帶64之切換晶片61的頂面610,還需執行一後處理製程以清潔該頂面610,因而增加了縂的製程複雜度並提高了製程成本。
如第7圖所示,美國專利號6,756,689復揭示一種封裝結構7,其係透過一種液態不導電黏著劑74將驅動晶片73黏置於切換晶片71。然而該液態不導電黏著劑74與導電黏著劑72係為不同材質,如此須執行兩獨立的固化製程,不僅增加了製程複雜性,同時亦提高了製程成本。此外,由於驅動晶片73係透過液態不導電黏著劑74接置於切換晶片71上,因而可能發生晶片傾斜的現象,降低封裝結構7的信賴度。
因此,如何改進多晶片模組封裝件以有效克服上述習知結構所存在之缺失,確為所需迫切解決之課題。
鑑於前述習知技術之缺失,本發明之目的係在提供一種多晶片模組封裝件,其使用相互隔離之晶片承載件及相同的晶片接置黏著劑以保證信賴性,並籍由相同的晶片接置黏著劑簡化製程、降低製程成本。
為達前述及其他目的,本發明第一實施例之多晶片模組封裝件係包括:透過第一導電黏著劑接置並電性連接至第一晶片承載件之第一晶片;透過第二導電黏著劑接置並電性連接至第二晶片承載件之第二晶片,其中,該第二晶片承載件與第一晶片承載件相互隔開,且該第二導電黏著劑與第一導電黏著劑由相同的黏著材料製成;用以電性連接所述第一晶片至第二晶片之複數導電元件;以及包覆所述第一晶片、第一晶片承載件、第二晶片、第二晶片承載件及複數導電元件之封裝膠體,其中該第一晶片承載件及第二晶片承載件之部分外露出該封裝膠體。
其中,第一晶片承載件及第二晶片承載件可為導線架或基板,該第一晶片及第二晶片分別為切換晶片及驅動晶片,該導電元件係為焊線,例如銅線或金線。
本發明第二實施例之多晶片模組封裝件係包括:晶片承載件;第一晶片,係透過第一導電黏著劑接置並電性連接至該晶片承載件;第二晶片,係透過第二導電黏著劑堆疊並電性連接至所述第一晶片,其中,該第二導電黏著劑與第一導電黏著劑係由相同的黏著材料製成;絕緣層,係形成於該第一晶片之主動面上並夾置於第一晶片及第二導電黏著劑之間以使第二晶片與第一晶片相互隔離;複數導電元件,用以電性連接所述第一晶片至第二晶片;以及封裝膠體,係包覆所述第一晶片、第二晶片、晶片承載件及複數導電元件,並使該晶片承載件部分外露出該封裝膠體。
其中,該絕緣層係可由抗蝕劑材料或例如氧化物、氮化物等介電材料或其他不導電材料製成。
本發明第三實施例之多晶片模組封裝件係包括:晶片承載件;第一晶片,係透過第一導電黏著劑接置並電性連接至該晶片承載件;第二晶片,係透過第二導電黏著劑堆疊至該第一晶片,其中,該第二導電黏著劑與第一導電黏著劑係由相同的黏著材料製成;絕緣層,係形成於該第二晶片之非主動面上並夾置於第二晶片及第二導電黏著劑之間以使第二晶片與第一晶片相互隔離;複數導電元件,用以電性連接所述第一晶片至第二晶片;以及封裝膠體,係包覆所述第一晶片、第二晶片、晶片承載件及複數導電元件,並使該晶片承載件部分外露出該封裝膠體。
本發明第四實施例之多晶片模組封裝件係包括:晶片承載件;第一晶片,係透過第一導電黏著劑接置並電性連接至該晶片承載件;第二晶片,係透過第二導電黏著劑接置並電性連接至該晶片承載件,其中,該第二導電黏著劑與第一導電黏著劑係由相同的黏著材料製成;絕緣層,係形成於該第二晶片之非主動面上並夾置於第二晶片及第二導電黏著劑之間以使第二晶片與第一晶片相互隔離;複數導電元件,用以電性連接所述第一晶片至第二晶片;以及封裝膠體,係包覆所述第一晶片、第二晶片、晶片承載件及複數導電元件,並使承載件部分外露出該封裝膠體。
其中,上述絕緣層可在晶圓級形成,亦即,可在將晶圓切割形成複數獨立晶片之前在晶圓上形成上述絕緣層。
綜上所述,由於第二導電黏著劑與第一導電黏著劑係由相同的黏著材料製成,係可籍由同一固化製程加以固化,從而簡化了製程並降低了製程成本。絕緣層的設置保證了第一晶片與第二晶片之間的隔離。同時,相同材料製成的第二導電黏著劑與第一導電黏著劑有效克服了熱膨脹系數不匹配的問題,俾可提高產品之信賴性。
以下係藉由特定的具體實施例說明本發明之實施方式,熟習此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點與功效。
請參閱第1圖,係為本發明之多晶片模組封裝件之第一實施例之剖面示意圖。如第1圖所示,該多晶片模組封裝件1包括:一導線架之第一晶片座10(出於簡化目的,僅圖示導線架之晶片座10);切換晶片11,係透過第一導電黏著劑12接置並電性連接至該第一晶片座10;所述導線架(未圖示)之第二晶片座13,係與所述第一晶片座10間隔一定距離;驅動晶片14,係透過第二導電黏著劑15接置並電性連接至所述第二晶片座13;複數焊線16,用以電性連接所述切換晶片11至驅動晶片14;以及封裝膠體17,係包覆所述第一晶片座10、第二晶片座13、切換晶片11、驅動晶片14、以及複數焊線16,並使第一晶片座10的底面100及第二晶片座13的底面130外露出該封裝膠體17。
由於第一晶片座10與第二晶片座13相互隔開,因而第一晶片座10與第二晶片座13之尺寸可較小,以相應減少隨後的溫度循環中施加其上之熱應力,從而有效避免第一晶片座10及第二晶片座13與封裝膠體17之間發生脫層,籍以提高該多晶片模組封裝件1之信賴性。
再者,由於相互隔開之第一晶片座10與第二晶片座13實現了切換晶片11與驅動晶片14之間的相互隔離,而第一導電黏著劑12及第二導電黏著劑15係為同樣的黏著材料例如銀膠或焊料,因而只需執行單個固化製程即可同時固化第一導電黏著劑12及第二導電黏著劑15。相應地,第一導電黏著劑12及第二導電黏著劑15可同時施加至對應的第一及第二晶片座10、13,因此避免了習知技術中需在接置絕緣黏著膠帶之前先接置導電黏著劑於晶片座上並固化的問題,從而簡化了多晶片模組封裝件1之製程並降低了成本。此外,相較習知技術需在固化製程完成後在黏置例如聚醯胺之絕緣黏著膠帶之前進行必要的清潔製程以清潔受固化製程污染的絕緣黏著膠帶的預定黏置區域,本實施例之固化製程係於焊晶製程結束後執行,第二晶片座13無污染之憂,因而毋需任何後處理製程,俾有利於進一步簡化製程並降低製程成本。
本實施例可使用例如金線或銅線等焊線電性連接切換晶片11與第一晶片座10以及驅動晶片14與第二晶片座13,為簡化說明,圖中未標示出上述焊線,並且由於打線作業係為習知技術,在此略去詳細描述。
封裝膠體17係可籍由習知模壓製程形成,在此同樣略去詳細描述。
請參閱第2圖,係為本發明之多晶片模組封裝件之第二實施例之剖面示意圖。
如圖所示,晶片模組封裝件2係具有一導線架(未圖示)之晶片座20,切換晶片21係透過第一導電黏著劑22接置於晶片座20並透過複數焊線(未圖示)電性連接至該晶片座20,隨後將驅動晶片23透過第二導電黏著劑24堆疊於該切換晶片21上並籍由複數焊線25電性連接至該切換晶片21,接著形成包覆晶片座20、切換晶片21、驅動晶片23及焊線25之封裝膠體26,並使晶片座20之底面(未圖示)外露出該封裝膠體26。
為確保切換晶片21與驅動晶片23之隔離,於切換晶片21之主動面210上形成絕緣層27。該絕緣層27係為氧化物或氮化物構成之介電層或阻層,其可形成於供切割形成單個切換晶片21之晶圓上。由於驅動晶片23籍由絕緣層27而實現與切換晶片21之隔離,使得第二導電黏著劑24與第一導電黏著劑22可由相同的材質構成,因而可在驅動晶片23的焊晶製程結束後執行固化製程,以避免固化製程污染絕緣層27並使第二導電黏著劑24施加於絕緣層27上而不影響信賴性。
另外,由於固化製程係在焊晶製程及打線製程結束後執行,因而形成於切換晶片21之主動面210上並外露出絕緣層27之焊墊211不會受到污染,俾可保證切換晶片21與驅動晶片23之間籍由焊線25實現的電性連接品質。
請參閱第3圖,係為本發明之多晶片模組封裝件之第三實施例之剖面示意圖。
如圖所示,本實施例之多晶片模組封裝件3與上述第二實施例之多晶片模組封裝件2之結構大體相似,區別僅在於本實施例之絕緣層37係形成於驅動晶片33之非主動面330上,夾置於第二導電黏著劑34與驅動晶片33之間。絕緣層37可形成於供切割形成單個驅動晶片33之晶圓(未圖示)底面上,以便在多晶片模組封裝件3之裝配中無需執行額外的成形製程。
請參閱第4圖,係為本發明之多晶片模組封裝件之第四實施例之剖面示意圖。
如圖所示,本實施例之多晶片模組封裝件4係具有一導線架(未圖示)之晶片座40,以供切換晶片41及驅動晶片43分別透過第一導電黏著劑42及第二導電黏著劑44接置於其上並透過複數焊線(未圖示)與其電性連接。驅動晶片43復在其非主動面上形成有絕緣層47,以確保切換晶片41與驅動晶片43之隔離並使第一及第二導電黏著劑42、44得以籍由相同的黏著材質製成。本實施例復利用複數焊線45電性連接切換晶片41與驅動晶片43,並形成包覆晶片座40、切換晶片41、驅動晶片43及焊線45之封裝膠體46,並使晶片座40之底面440外露出該封裝膠體46。
由於第一及第二導電黏著劑42、44係由相同的黏著材質構成,因此可將第一及第二導電黏著劑42、44同時施加於晶片座40的頂面401,並在完成切換晶片41及驅動晶片43之焊晶製程後只需執行一次固化製程,相較習知技術,本實施例之多晶片模組封裝件4的製程更為簡化,同時由於固化製程係在焊晶製程及打線製程之後執行,晶片座40之頂面401的預定區域不會受到污染,如此得以提升多晶片模組封裝件4的信賴性。
上述實施例僅例示性說明本發明之原理及其功效,而非用於限制本發明,任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修飾與改變。因此,本發明之權利保護範圍,應如後述之申請專利範圍所列。
1、2、3、4...多晶片模組封裝件
10...第一晶片座
100...底面
11、21、41、51、61、71...切換晶片
12、22、42...第一導電黏著劑
13...第二晶片座
130...底面
14、23、33、43、52、63、73...驅動晶片
15、24、34、44...第二導電黏著劑
16、25、45...焊線
17、26、46、55、65...封裝膠體
20、40、50、60...晶片座
210...主動面
211...焊墊
27、37、47...絕緣層
330...非主動面
401...頂面
440...底面
5、6、7...封裝結構
53、62、72...導電黏著劑
54、64...絕緣黏著膠帶
610...頂面
74...液態不導電黏著劑
第1圖係本發明之多晶片模組封裝件之第一實施例之剖面示意圖;第2圖係本發明之多晶片模組封裝件之第二實施例之剖面示意圖;第3圖係本發明之多晶片模組封裝件之第三實施例之剖面示意圖;第4圖係本發明之多晶片模組封裝件之第四實施例之剖面示意圖;第5圖係習知多晶片模組封裝件之剖面示意圖;第6圖係另一習知多晶片模組封裝件之剖面示意圖;以及第7圖係另一習知多晶片模組封裝件之剖面示意圖。
1...多晶片模組封裝件
10...第一晶片座
100...底面
11...切換晶片
12...第一導電黏著劑
13...第二晶片座
130...底面
14...驅動晶片
15...第二導電黏著劑
16...焊線
17...封裝膠體
Claims (22)
- 一種多晶片模組封裝件,係包括:第一晶片,係為切換晶片,係透過第一導電黏著劑接置並電性連接至第一晶片承載件;第二晶片,係為驅動晶片,係透過第二導電黏著劑接置並電性連接至第二晶片承載件,其中,該第二晶片承載件與第一晶片承載件相互隔開,且該第二導電黏著劑與第一導電黏著劑由相同的黏著材料製成;複數導電元件,用以電性連接所述第一晶片至第二晶片;以及封裝膠體,係包覆所述第一晶片、第一晶片承載件、第二晶片、第二晶片承載件及複數導電元件,並分別使第一晶片承載件及第二晶片承載件之部分外露出該封裝膠體。
- 如申請專利範圍第1項之多晶片模組封裝件,其中,該第一晶片承載件及第二晶片承載件係為導線架,其分別具有一晶片座,以供接置所述第一晶片及第二晶片。
- 如申請專利範圍第1項之多晶片模組封裝件,其中,該導電元件係為銲線。
- 如申請專利範圍第1項之多晶片模組封裝件,其中,該第一導電黏著劑與第二導電黏著劑係為銀膠。
- 一種多晶片模組封裝件,係包括:晶片承載件;第一晶片,係透過第一導電黏著劑接置並電性連 接至該晶片承載件;第二晶片,係透過第二導電黏著劑堆疊並電性連接至所述第一晶片,其中,該第二導電黏著劑與第一導電黏著劑係由相同的黏著材料製成;絕緣層,係形成於該第一晶片上並夾置於第一晶片及第二導電黏著劑之間以使第二晶片與第一晶片相互隔離;複數導電元件,用以電性連接所述第一晶片至第二晶片;以及封裝膠體,係包覆所述第一晶片、第二晶片、晶片承載件及複數導電元件,並使該晶片承載件部分外露出該封裝膠體。
- 如申請專利範圍第5項之多晶片模組封裝件,其中,該絕緣層係為介電層或防焊層。
- 如申請專利範圍第5項之多晶片模組封裝件,其中,該絕緣層之材質係為氧化物或氮化物。
- 如申請專利範圍第5項之多晶片模組封裝件,其中,該絕緣層係形成於一用以形成第一晶片之晶圓上。
- 如申請專利範圍第5項之多晶片模組封裝件,其中,該導電元件係為銲線。
- 如申請專利範圍第5項之多晶片模組封裝件,其中,該第一導電黏著劑與第二導電黏著劑係為銀膠。
- 一種多晶片模組封裝件,係包括:晶片承載件; 第一晶片,係透過第一導電黏著劑接置並電性連接至該晶片承載件;第二晶片,係透過第二導電黏著劑堆疊至該第一晶片,其中,該第二導電黏著劑與第一導電黏著劑係由相同的黏著材料製成;絕緣層,係形成於該第二晶片上並夾置於第二晶片及第二導電黏著劑之間以使第二晶片與第一晶片相互隔離;複數導電元件,用以電性連接所述第一晶片至第二晶片;以及封裝膠體,係包覆所述第一晶片、第二晶片、晶片承載件及複數導電元件,並使該晶片承載件部分外露出該封裝膠體。
- 如申請專利範圍第11項之多晶片模組封裝件,其中,該絕緣層係為介電層或防焊層。
- 如申請專利範圍第11項之多晶片模組封裝件,其中,該絕緣層之材質係為氧化物或氮化物。
- 如申請專利範圍第11項之多晶片模組封裝件,其中,該絕緣層係形成於一用以形成第二晶片之晶圓上。
- 如申請專利範圍第11項之多晶片模組封裝件,其中,該導電元件係為銲線。
- 如申請專利範圍第11項之多晶片模組封裝件,其中,該第一導電黏著劑與第二導電黏著劑係為銀膠。
- 一種多晶片模組封裝件,係包括: 晶片承載件;第一晶片,係透過第一導電黏著劑接置並電性連接至該晶片承載件;第二晶片,係透過第二導電黏著劑接置並電性連接至該晶片承載件,其中,該第二導電黏著劑與第一導電黏著劑係由相同的黏著材料製成;絕緣層,係形成於該第二晶片上並夾置於第二晶片及第二導電黏著劑之間以使第二晶片與第一晶片相互隔離;複數導電元件,用以電性連接所述第一晶片至第二晶片;以及封裝膠體,係包覆所述第一晶片、第二晶片、晶片承載件及複數導電元件,並使承載件部分外露出該封裝膠體。
- 如申請專利範圍第17項之多晶片模組封裝件,其中,該絕緣層係為介電層或防焊層。
- 如申請專利範圍第17項之多晶片模組封裝件,其中,該絕緣層之材質係為氧化物或氮化物。
- 如申請專利範圍第17項之多晶片模組封裝件,其中,該絕緣層係形成於一用以形成第二晶片之晶圓上。
- 如申請專利範圍第17項之多晶片模組封裝件,其中,該導電元件係為銲線。
- 如申請專利範圍第17項之多晶片模組封裝件,其中,該第一導電黏著劑與第二導電黏著劑係為銀膠。
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US11/894,341 US20090051019A1 (en) | 2007-08-20 | 2007-08-20 | Multi-chip module package |
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US7750451B2 (en) * | 2007-02-07 | 2010-07-06 | Stats Chippac Ltd. | Multi-chip package system with multiple substrates |
US8816487B2 (en) * | 2008-03-18 | 2014-08-26 | Stats Chippac Ltd. | Integrated circuit packaging system with package-in-package and method of manufacture thereof |
US7847375B2 (en) * | 2008-08-05 | 2010-12-07 | Infineon Technologies Ag | Electronic device and method of manufacturing same |
DE102011113255B4 (de) * | 2011-09-13 | 2021-03-04 | Infineon Technologies Ag | Chipmodule und Verfahren zur Herstellung eines Chipmoduls |
US8963305B2 (en) | 2012-09-21 | 2015-02-24 | Freescale Semiconductor, Inc. | Method and apparatus for multi-chip structure semiconductor package |
KR102116979B1 (ko) | 2013-10-28 | 2020-06-05 | 삼성전자 주식회사 | 적층 반도체 패키지 |
US20150168994A1 (en) * | 2013-12-13 | 2015-06-18 | Cirque Corporation | Secure cage created by re-distribution layer metallization in fan-out wafer level packaging process |
US9673170B2 (en) | 2014-08-05 | 2017-06-06 | Infineon Technologies Ag | Batch process for connecting chips to a carrier |
KR102287396B1 (ko) | 2014-10-21 | 2021-08-06 | 삼성전자주식회사 | 시스템 온 패키지 모듈과 이를 포함하는 모바일 컴퓨팅 장치 |
US9887119B1 (en) | 2016-09-30 | 2018-02-06 | International Business Machines Corporation | Multi-chip package assembly |
JP2018110169A (ja) * | 2016-12-28 | 2018-07-12 | 富士電機株式会社 | 半導体装置および半導体装置製造方法 |
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CN101373761A (zh) | 2009-02-25 |
US20120217657A1 (en) | 2012-08-30 |
US20090051019A1 (en) | 2009-02-26 |
CN101373761B (zh) | 2012-06-27 |
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