JP2021125643A - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
JP2021125643A
JP2021125643A JP2020019933A JP2020019933A JP2021125643A JP 2021125643 A JP2021125643 A JP 2021125643A JP 2020019933 A JP2020019933 A JP 2020019933A JP 2020019933 A JP2020019933 A JP 2020019933A JP 2021125643 A JP2021125643 A JP 2021125643A
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Prior art keywords
opening
wiring layer
electrode
semiconductor chip
semiconductor device
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JP2020019933A
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恵一 丹羽
Keiichi Niwa
恵一 丹羽
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Kioxia Corp
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Kioxia Corp
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Priority to JP2020019933A priority Critical patent/JP2021125643A/ja
Priority to TW109126855A priority patent/TWI758815B/zh
Priority to CN202010875391.7A priority patent/CN113257772A/zh
Priority to US17/008,513 priority patent/US11482502B2/en
Publication of JP2021125643A publication Critical patent/JP2021125643A/ja
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Abstract

【課題】フリップチップ接続の接続領域にボイドが生じることを抑制することができる半導体装置およびその製造方法を提供する。
【解決手段】本実施形態による半導体装置は、配線層と該配線層上に設けられた絶縁層とを含み、前記絶縁層に設けられた開口部において前記配線層の一部を露出させた配線基板を備える。導電材料は、開口部に埋め込まれ、該開口部内の配線層を被覆する。半導体チップは、開口部内に挿入され導電材料に接続する電極を有する。半導体チップの搭載方向から見たときに、電極と配線層とは離間しており、電極と配線層との間には導電材料が介在する。
【選択図】図２

Description

本実施形態は、半導体装置およびその製造方法に関する。
半導体チップを配線基板へフリップチップ接続する方法として、マスリフロー方式または熱圧着方式がある。このうち熱圧着方式によるフリップチップ接続では、半導体チップを配線基板上に搭載したときに、熱によりはんだを溶融させて、半導体チップのバンプと配線基板のパッドとを熱圧着させて接続する。
このような熱圧着方式で用いられる配線基板は、バンプの接続領域のソルダレジストに開口部を有し、開口部において配線の一部またはパッドを露出させる。この接続領域では、ソルダレジストとその下地（プリプレグ）との間に段差があり、ＮＣＰ（Non-Conductive Past）を供給したときに接続領域内、あるいは、バンプの周囲にボイドが残ってしまうことがある。このようなボイドは、隣接するバンプ間のショート不良、ＮＣＰ樹脂の密着性不良、あるいは、信頼性の悪化に繋がる。
特許第６２２０７９９号公報 特開２０１４−１２３５９２号公報 米国特許第７６９６６２３号公報
フリップチップ接続の接続領域にボイドが生じることを抑制することができる半導体装置およびその製造方法を提供する。
本実施形態による半導体装置は、配線層と該配線層上に設けられた絶縁層とを含み、前記絶縁層に設けられた開口部において前記配線層の一部を露出させた配線基板を備える。導電材料は、開口部に埋め込まれ、該開口部内の配線層を被覆する。半導体チップは、開口部内に挿入され導電材料に接続する電極を有する。半導体チップの搭載方向から見たときに、電極と配線層とは離間しており、電極と配線層との間には導電材料が介在する。
第１実施形態による半導体装置の構成例を示す断面図。 図１の枠Ｂ１の構成を示す拡大断面図。 ソルダレジスト層、開口部、配線層および電極ピラーの位置関係を示す平面図。 第１実施形態による半導体装置の製造方法の一例を示す図。 図４に続く、半導体装置の製造方法の一例を示す図。 図５に続く、半導体装置の製造方法の一例を示す図。 図６に続く、半導体装置の製造方法の一例を示す図。 図７に続く、半導体装置の製造方法の一例を示す図。 図８に続く、半導体装置の製造方法の一例を示す図。 図９に続く、半導体装置の製造方法の一例を示す図。 図１０に続く、半導体装置の製造方法の一例を示す図。 図１１に続く、半導体装置の製造方法の一例を示す図。 図１２に続く、半導体装置の製造方法の一例を示す図。 図１３に続く、半導体装置の製造方法の一例を示す図。 図１４に続く、半導体装置の製造方法の一例を示す図。 第２実施形態による半導体チップと配線基板との接続部分の構成例を示す拡大断面図。 第２実施形態によるソルダレジスト層、開口部、配線層および電極ピラーの位置関係を示す平面図。 第３実施形態による半導体チップと配線基板との接続部分の構成例を示す拡大断面図。 第４実施形態による半導体チップと配線基板との接続部分の構成例を示す拡大断面図。
以下、図面を参照して本発明に係る実施形態を説明する。本実施形態は、本発明を限定するものではない。以下の実施形態において、配線基板の上下方向は、半導体チップが搭載される面を上とした場合の相対方向を示し、重力加速度に従った上下方向と異なる場合がある。図面は模式的または概念的なものであり、各部分の比率などは、必ずしも現実のものと同一とは限らない。明細書と図面において、既出の図面に関して前述したものと同様の要素には同一の符号を付して詳細な説明は適宜省略する。
（第１実施形態）
図１は、第１実施形態による半導体装置の構成例を示す断面図である。半導体装置１は、配線基板１０と、半導体チップ２０、３０〜３３と、接着層４０〜４３と、スペーサチップ５０と、接着層６０と、金属材料７０と、樹脂層８０と、ボンディングワイヤ９０と、封止樹脂９１とを備えている。半導体装置１は、例えば、ＮＡＮＤ型フラッシュメモリのパッケージである。
配線基板１０は、配線層１１と絶縁層１５とを含むプリント基板やインタポーザでよい。配線層１１には、例えば、銅、ニッケルまたはそれらの合金等の低抵抗金属が用いられる。絶縁層１５には、例えば、ガラスエポキシ樹脂等の絶縁性材料が用いられる。図では、絶縁層１５の表面と裏面のみに配線層１１が設けられている。しかし、配線基板１０は、複数の配線層１１および複数の絶縁層１５を積層して構成された多層配線構造を有していてもよい。配線基板１０は、例えば、インタポーザのように、その表面と裏面とを貫通する貫通電極１２を有してもよい。
配線基板１０の表面には、配線層１１上に設けられたソルダレジスト層１４が設けられている。ソルダレジスト層１４は、金属材料７０から配線層１１を保護し、ショート不良を抑制するための絶縁層である。ソルダレジスト層１４には、開口部ＯＰが設けられており、配線層１１の一部および絶縁層１５は開口部ＯＰから露出されている。
配線基板１０の裏面にも、配線層１１上に設けられたソルダレジスト層１４が設けられている。ソルダレジスト層１４から露出された配線層１１には、金属バンプ１３が設けられている。金属バンプ１３は、図示しない他の部品と配線基板１０とを電気的に接続するために設けられている。
半導体チップ２０は、例えば、メモリチップを制御するコントローラチップである。半導体チップ２０の表面には、図示しない半導体素子が設けられている。半導体素子は、例えば、コントローラを構成するＣＭＯＳ（Complementary Metal Oxide Semiconductor）回路でよい。半導体チップ２０の裏面には、半導体素子と電気的に接続される電極ピラー２１が設けられている。電極ピラー２１には、例えば、銅、ニッケルまたはそれらの合金等の低抵抗金属材料が用いられている。
電極ピラー２１は、配線基板１０の開口部ＯＰに挿入されており、電極ピラー２１の下端部は、開口部ＯＰの上端よりも低い位置に配置される。電極ピラー２１の周囲には、金属材料７０が設けられている。電極ピラー２１は、金属材料７０を介して開口部ＯＰにおいて露出された配線層１１と電気的に接続される。
金属材料７０は、配線基板１０の開口部ＯＰ内に埋め込まれ、開口部ＯＰ内で露出された配線層１１を被覆している。金属材料７０には、例えば、はんだ、銀、銅等の低抵抗金属材料が用いられている。金属材料７０は、後述するように、液体またはペースト状の金属材料として供給され、その後、硬化して形成される。金属材料７０は、開口部ＯＰ内で配線基板１０の配線層１１を被覆し、かつ、半導体チップ２０の電極ピラー２１の側面も被覆している。これにより、金属材料７０は、半導体チップ２０の電極ピラー２１と配線基板１０の配線層１１とを電気的に接続することができる。電極ピラー２１は、配線層１１と離間しており直接接触していない。即ち、電極ピラー２１と配線層１１との間には、金属材料７０が介在する。
半導体チップ２０の周囲、および、半導体チップ２０と配線基板１０との間には、樹脂層（アンダフィル）８０が設けられている。樹脂層８０は、例えば、ＮＣＰ（Non Conductive Past）を硬化させたものであり、半導体チップ２０の周囲を被覆して保護する。
半導体チップ２０の上には、接着層４０を介して半導体チップ３０が接着されている。半導体チップ３０は、例えば、ＮＡＮＤ型フラッシュメモリを含むメモリチップである。半導体チップ３０は、その表面に半導体素子（図示せず）を有する。半導体素子は、例えば、メモリセルアレイおよびその周辺回路（ＣＭＯＳ回路）でよい。メモリセルアレイは、複数のメモリセルを三次元配置した立体型メモリセルアレイでもよい。また、半導体チップ３０上には、接着層４１介して半導体チップ３１が接着されている。半導体チップ３１上には、接着層４２介して半導体チップ３２が接着されている。半導体チップ３２上には、接着層４３介して半導体チップ３３が接着されている。半導体チップ３１〜３３は、例えば、半導体チップ３０と同様に、例えば、ＮＡＮＤ型フラッシュメモリを含むメモリチップである。半導体チップ３０〜３３は、同一のメモリチップでもよい。図では、コントローラチップとしての半導体チップ２０の他、４つのメモリチップとしての半導体チップ３０〜３３が積層されている。しかし、半導体チップの積層数は、３以下でも、５以上であってもよい。
半導体チップ３０は、半導体チップ２０よりも大きく、半導体チップ３０の外縁は、半導体チップ２０の外縁の外側にある。半導体チップ２０の周囲において、半導体チップ３０と配線基板１０のソルダレジスト層１４との間には、スペーサチップ５０が設けられている。スペーサチップ５０は、接着層６０を介してソルダレジスト層１４上に接着されている。また、スペーサチップ５０の上面には接着層４０が接着されており、半導体チップ３０は、スペーサチップ５０の上面に接着層４０を介して接着されている。
ボンディングワイヤ９０は、配線基板１０、半導体チップ３０〜３３の任意のパッドに接続されている。ボンディングワイヤ９０で接続するために、半導体チップ３０〜３３は、パッドの分だけずらされて積層されている。尚、半導体チップ２０は、電極ピラー２１によってフリップチップ接続されているので、ワイヤボンディングはされていない。しかし、半導体チップ２０も、電極ピラー２１による接続に加えて、ワイヤボンディングしても構わない。
さらに、封止樹脂９１が、半導体チップ２０、３０〜３３、スペーサチップ５０、樹脂層８０、ボンディングワイヤ９０等を封止している。これにより、半導体装置１は、複数の半導体チップ２０、３０〜３３を配線基板１０上において１つの半導体パッケージとして構成されている。
図２は、図１の枠Ｂ１の構成を示す拡大断面図である。図３は、ソルダレジスト層、開口部、配線層および電極ピラーの位置関係を示す平面図である。ソルダレジスト層１４には、開口部ＯＰが設けられており、配線層１１の一部が露出されている。金属材料７０が開口部ＯＰ内に埋め込まれており、配線層１１の一部と接触している。電極ピラー２１は、金属材料７０内に挿入されており、金属材料７０を介して配線層１１に電気的に接続されている。
電極ピラー２１の下端部２１ｂは、開口部ＯＰ内へ挿入されている。よって、電極ピラー２１の下端部２１ｂの高さＨ２１は、ソルダレジスト層１４の上面１４ａの高さＨ１４よりも下方にある。これにより、電極ピラー２１は、開口部ＯＰ内に充填された液体またはペースト状の金属材料７０内に接触し挿入される。金属材料７０は、電極ピラー２１の下端部２１ｂから側面を伝って這い上がり、開口部ＯＰの上端から斜め上方へ向かって電極ピラー２１の側面までテーパーを有する。このように、金属材料７０は、電極ピラー２１の側面に沿って開口部ＯＰから盛り上がっている。金属材料７０は、開口部ＯＰに挿入されている電極ピラー２１の体積と同じかそれ以上の分だけ、電極ピラー２１の側面に沿って開口部ＯＰから盛り上がっている。金属材料７０が電極ピラー２１の側面に接触するように開口部ＯＰから盛り上がっていることによって、金属材料７０と電極ピラー２１との間の接触抵抗が小さくなる。
図２では、電極ピラー２１の下端部２１ｂの高さＨ２１は、ソルダレジスト層１４の高さＨ１４よりも低く、かつ、配線層１１の上面１１ａの高さＨ１１よりも高い位置にある。しかし、電極ピラー２１の下端部２１ｂの高さＨ２１は、配線層１１の上面１１ａの高さＨ１１よりも低い位置にあってもよい。さらに、電極ピラー２１の下端部２１ｂは、配線基板１０の絶縁層１５の上面１５ａに接触していても構わない。電極ピラー２１の直下には、配線層１１は設けられていないので、電極ピラー２１の下端部２１ｂは、絶縁層１５の上面１５ａに接触することができる。即ち、下端部２１ｂの高さＨ２１は、絶縁層１５の表面の高さと等しくてもよい。このように、電極ピラー２１の下端部２１ｂは、ソルダレジスト層１４の高さＨ１４よりも低い位置にあれば、任意の位置に位置付けてよい。電極ピラー２１の下端部２１ｂが絶縁層１５の上面１５ａに近付くほど、半導体チップ２０は、配線基板１０に近づき、半導体装置１のパッケージの厚みを薄くすることができる。従って、電極ピラー２１の下端部２１ｂは、絶縁層１５の上面１５ａに近付くほど好ましいと言える。
また、電極ピラー２１の直下には、配線層１１が存在せず、金属材料７０が設けられている。図３に示すように、半導体チップ２０の搭載方向（図２のＺ方向の上方）から見たときに、電極ピラー２１と配線層１１とは離間しており、電極ピラー２１と配線層１１との間には「導電材料」としての金属材料７０が介在する。
配線層１１の一部は、上記搭載方向から見たときに、開口部ＯＰの側面から開口部ＯＰの中心部へ向かって突出している。これにより、配線部１１と金属材料７０との接触面積が大きくなり、配線部１１と金属材料７０との間の接触抵抗が小さくなる。
本実施形態では、液体またはペースト状の金属材料（例えば、はんだペースト、銅または銀ペースト、銅または銀ナノインク等）７０を開口部ＯＰ内に予め充填し、半導体チップ２０の電極ピラー２１を開口部ＯＰ内の金属材料７０に挿入（浸漬）する。これにより、開口部ＯＰ内にボイドが生じることを抑制し、電極ピラー２１と配線層１１との接触不良を抑制することができる。
また、平面レイアウトにおいて、電極ピラー２１は、配線層１１と重複しておらず、配線層１１と離間している。即ち、平面レイアウトにおいて、電極ピラー２１は、配線層１１と干渉しない。これにより、電極ピラー２１の下端部２１ｂの高さＨ２１は、配線層１１の上面１１ａの高さＨ１１よりも低くすることができる。さらに、電極ピラー２１の下端部２１ｂは、絶縁層１５の上面１５ａに達していても構わない。電極ピラー２１の下端部２１ｂを絶縁層１５の上面１５ａに近付けることによって、半導体装置１のパッケージの厚みを薄くすることができる。
次に、本実施形態による半導体装置１の製造方法を説明する。
図４〜図１５は、第１実施形態による半導体装置の製造方法の一例を示す図である。まず、半導体ウェハＷに半導体素子を形成する。図４は、半導体素子が形成された半導体ウェハＷの斜視図である。半導体ウェハＷ上に半導体素子が形成されており、ポリイミドＰＩが半導体素子を被覆している。半導体ウェハＷは、後述のダイシング工程において個片化される複数の半導体チップ２０（または３０〜３３）を含んでいる。
次に、図５に示すように、ポリイミドＰＩ上に保護テープＴＰ１を貼付する。次に、保護テープＴＰ１を下にして、半導体ウェハＷの裏面をグラインダＧで研磨する。
保護テープＴＰ１を剥がした後、図７に示すように、ウェハリングＷＲ内に張られた可撓性の樹脂テープＴＰ２に半導体ウェハＷの裏面を貼り付ける。次に、レーザ発振器ＬＧを用いて、半導体ウェハＷの表面または裏面のダイシングラインに沿ってレーザ光を照射する。これにより、ダイシングラインに溝（グルーブ）が形成される。
次に、図９に示すように、ダイシングブレードＤＢで、ダイシングラインの溝に沿って半導体ウェハＷを切断する。これにより、半導体ウェハＷは半導体チップ２０（または３０〜３３）に個片化される。個片化された半導体チップ２０（または３０〜３３）は、配線基板１０に実装されるために、樹脂テープＴＰ２からピックアップされる。
一方、配線基板１０では、絶縁層１５、配線層１１、貫通電極１２、ソルダレジスト層１４を形成する。次に、ソルダレジスト層１４上に形成されたマスク材Ｍ１を用いて、ソルダレジスト層１４に開口部ＯＰを形成する。このとき、開口部ＯＰは、配線層１１およびその周辺の絶縁層１５を露出するように形成される。
次に、図示しないが、フラックスを塗布して開口部ＯＰにおいて露出されている配線層１１の表面の酸化膜を除去する。次に、配線基板１０を熱処理して、プラズマ処理を行う。次に、図１０に示すように、配線基板１０の表面および開口部ＯＰに、液体またはペースト状の金属材料７０を供給する。液体またはペースト状の金属材料７０は、開口部ＯＰにおいて露出された配線層１１を被覆する。
次に、図１１に示すように、配線基板１０のマスク材Ｍ１の表面上を工具１００で走査する。工具１００は、例えば、樹脂、金属等からなる板状のスクレーパでよい。工具１００で配線基板１０上をＡ１方向へ走査することによって、図１２に示すように、液体またはペースト状の金属材料７０を開口部ＯＰに充填させつつ、余剰の金属材料７０を配線基板１０から除去する。Ａ１方向は、配線基板１０の表面に対して略平行方向である。即ち、スキージ工具１００は、配線基板１０上をＡ１方向へ走査しながら、開口部ＯＰ内に金属材料７０を残置させ、かつ、余剰の金属材料７０を配線基板１０から除去するように拭い取る。これにより、図１３に示すように、開口部ＯＰ内に金属材料７０が充填される。金属材料７０は、マスク材Ｍ１上にはほとんど残らない。また、金属材料７０がマスク材Ｍ１上に残っても、マスク材Ｍ１を除去することによって、金属材料７０はソルダレジスト層１４上から除去され得る。尚、金属材料７０が開口部ＯＰ内をより確実に充填するように、金属材料７０をリフローしてもよい。
次に、図９に示す工程で形成された半導体チップ２０をピックアップして、半導体チップ２０の電極ピラー２１を、開口部ＯＰ内の金属材料７０に挿入する。このとき、液体またはペースト状の金属材料７０は、電極ピラー２１の下端部に接触すると、その下端部から側面を伝って這い上がる。よって、金属材料７０は、開口部ＯＰの上端から斜め上方へ向かって電極ピラー２１の側面までテーパーを有するように形成される。これにより、金属材料７０は、電極ピラー２１の側面に沿って開口部ＯＰから盛り上がる。金属材料７０は、開口部ＯＰに挿入されている電極ピラー２１の体積と同じかそれ以上の分だけ、電極ピラー２１の側面に沿って開口部ＯＰから盛り上がる。金属材料７０が電極ピラー２１の側面に接触するように開口部ＯＰから盛り上がっていることによって、金属材料７０と電極ピラー２１との間の接触抵抗が小さくなる。
尚、電極ピラー２１の下端部は、ソルダレジスト層１４の上面より低ければよい。即ち、電極ピラー２１の下端部は、配線層１１の上面よりも下方まで挿入されていてもよいし、配線層１１の上面よりも高い位置まで挿入されているだけでもよい。電極ピラー２１は、配線層１１とは直接接触していなくても、金属材料７０を介して配線層１１に電気的に接続することができるからである。
さらに、図３を参照して説明したように、電極ピラー２１の直下には、配線層１１が存在しない。よって、半導体チップ２０の搭載方向から見たときに、電極ピラー２１と配線層１１とは離間しており、電極ピラー２１と配線層１１との間には金属材料７０が介在する。このように、電極ピラー２１の直下に配線層１１は設けられていなくても、電極ピラー２１は、金属材料７０を介して配線層１１に電気的に接続することができる。
電極ピラー２１の下端部は、絶縁層１５の上面に接触してもよい。これにより、半導体チップ２０と配線基板１０との距離が近くなり、半導体装置１のパッケージの厚みを薄くすることができる。
次に、配線基板１０をベークして液体またはペースト状の金属材料７０の溶剤を揮発させる。電極ピラー２１と金属材料７０とが、金属拡散により接続される。ベークが終了すると、金属材料７０はベーク前よりも硬化する。これにより、配線基板１０に対する半導体チップ２０の位置がほぼ決定される。
次に、図１５に示すように、半導体チップ２０に樹脂層８０が供給される。樹脂層８０は、例えば、アンダーフィル材であり、半導体チップ２０と配線基板１０との間に入り込み、金属材料７０の周囲および半導体チップ２０の側面を被覆する。次に、半導体チップ２０の周辺の配線基板１０上に接着層６０を介してスペーサチップ５０を接着する。スペーサチップ５０の上面の高さは、半導体チップ２０の上面の高さとほぼ等しいことが好ましい。これにより、半導体チップ２０上に積層される半導体チップ３０〜３３の平坦性が向上する。
その後、図１に示すように、接着層４０を裏面に貼り付けた半導体チップ３０を半導体チップ２０上に搭載し、接着層４１を裏面に貼り付けた半導体チップ３１を半導体チップ３０上に搭載し、接着層４２を裏面に貼り付けた半導体チップ３２を半導体チップ３１上に搭載し、接着層４３を裏面に貼り付けた半導体チップ３３を半導体チップ３２上に搭載する。
次に、ボンディングワイヤ９０で、半導体チップ３０〜３３のパッドおよび配線基板１０上のパッドを接続する。さらに、封止樹脂９１で、半導体チップ２０、３０〜３３、ボンディングワイヤ９０等を封止し、図１に示す構造が得られる。
以上のように、本実施形態では、ペースト状の金属材料（例えば、はんだペースト）７０を配線基板１０上に供給した後、工具１００で金属材料７０を拭い取る。これにより、金属材料７０を開口部ＯＰ内に充填する。その後、半導体チップ２０の電極ピラー２１を開口部ＯＰ内の金属材料７０に挿入する。
もし、電極ピラー２１にはんだバンプを予め形成しておいて、このはんだバンプを配線基板１０にフリップチップ接続する場合、フリップチップ接続は、バンプ表面の酸化膜を除去するために接続部にフラックスを供給しながら実行される。このとき、フラックスの流れによって、開口部ＯＰの内部や電極ピラー２１の周囲でボイド（巻き込みボイド）が発生する。
これに対し、本実施形態では、開口部ＯＰ内に予め充填された金属材料（はんだ）７０に、電極ピラー２１を挿入する。よって、フリップチップ接続の際には、開口部ＯＰは金属材料７０ですでに充填されているので、開口部ＯＰの内部または電極ピラー２１の周囲にボイドは発生しない。また、電極ピラー２１にはんだバンプを予め付着させる必要は無く、フリップチップ接続の際にフラックスの供給が不要である。従って、開口部ＯＰの内部や電極ピラー２１の周囲で巻き込みボイドが発生することを抑制することができる。
（第２実施形態）
図１６は、第２実施形態による半導体チップと配線基板との接続部分の構成例を示す拡大断面図である。図１７は、第２実施形態によるソルダレジスト層、開口部、配線層および電極ピラーの位置関係を示す平面図である。第２実施形態では、配線層１１の一部は、開口部ＯＰの内面に面しており、該内面において露出されている。即ち、図１６に示すように、配線層１１は、開口部ＯＰに突出しておらず、面しているだけである。このような構成であっても、金属材料７０は、配線層１１に接触することができ、電極ピラー２１と配線層１１とを電気的に接続することができる。
第２実施形態のその他の構成は、第１実施形態の対応する構成と同様でよい。従って、第２実施形態は，第１実施形態と同様の効果を得ることができる。
（第３実施形態）
図１８は、第３実施形態による半導体チップと配線基板との接続部分の構成例を示す拡大断面図である。第３実施形態によれば、電極ピラー２１の下端部２１ｂの高さＨ２１は、配線層１１の上面１１ａの高さＨ１１よりも下方にある。これにより、金属材料７０は、電極ピラー２１の側面と比較的広い面積において接触できる。よって、金属材料７０と電極ピラー２１との間の接触抵抗がさらに小さくなる。第３実施形態のその他の構成は、第１実施形態の対応する構成と同様でよい。これにより、第３実施形態は、第１実施形態と同様の効果を得ることができる。また、第３実施形態は、第２実施形態と組み合わせてもよい。
（第４実施形態）
図１９は、第４実施形態による半導体チップと配線基板との接続部分の構成例を示す拡大断面図である。第４実施形態によれば、電極ピラー２１の下端部２１ｂが、絶縁層（プレプリグ）１５の上面１５ａに接触している。即ち、下端部２１ｂの高さＨ２１は、配線基板１０の絶縁層１５の上面１５ａとほぼ等しい。これにより、金属材料７０は、電極ピラー２１の側面とさらに広い面積に接触できる。よって、金属材料７０と電極ピラー２１との間の接触抵抗がさらに小さくなる。第４実施形態のその他の構成は、第１実施形態の対応する構成と同様でよい。これにより、第４実施形態は、第１実施形態と同様の効果を得ることができる。また、第４実施形態は、第２実施形態と組み合わせてもよい。
（第５実施形態）
第１から第４実施形態においては、図１３〜図１５に示す様に、半導体チップ２０と配線基板１０とを接続したのちに樹脂層８０の供給を行っている。しかし、第５実施形態では、金属材料７０を配線基板１０に設けたあと、配線基板１０に樹脂層８０としてＮＣＰ（非導電ペースト）を供給する。その後に半導体チップ２０と配線基板１０とを加熱しながら押圧し接続させる。このとき、配線基板１０と半導体チップ２０の間にあるＮＣＰは、加熱と押圧により流動して、配線基板１０と半導体チップ２０の間から漏れ出して半導体チップ２０の側面を這い上がる。したがって、本実施形態においても半導体チップ２０と配線基板１０と樹脂層８０とは図１に示す様な形態になる。
この場合でも第１〜第４実施形態と同様の効果を得ることができる。
（第６実施形態）
第６実施形態において、ＮＣＰを用いる代わりに、（非導電性フィルム）を用いた接続方法について述べる。本実施形態では、金属材料７０を配線基板１０に設ける。樹脂層８０としてＮＣＦ（非導電性フィルム）を、半導体チップ２０の電極ピラー２１が形成された面に設ける。その後に半導体チップ２０と配線基板１０とを加熱しながら押圧し接続させる。このとき、配線基板１０と半導体チップ２０の間にあるＮＣＦは、加熱と押圧により流動して、配線基板１０と半導体チップ２０の間から漏れ出して半導体チップ２０の側面を這い上がる。したがって、本実施形態においても半導体チップ２０と配線基板１０と樹脂層８０とは図１に示す様な形態になる。
この場合でも第１から第５実施形態と同様の効果を得ることができる。
（その他の実施形態）
（ａ）上記実施形態において、金属材料７０はスキージを使用することで配線基板１０の開口部ＯＰに設けられた。他にも、スクリーン印刷、ディスペンサ、インクジェット等様々な方法で金属材料７０が開口部ＯＰに設けられてもよい。この場合でも上記実施形態と同様の効果を得ることができる。
（ｂ）上記実施形態において、電極ピラー２１を開口部ＯＰ内の金属材料７０に挿入する際、半導体チップ２０または配線基板１０を加熱しながら行ってもよい。この場合でも上記実施形態と同様の効果を得ることができる。
（ｃ）上記実施形態において、金属材料７０の代わりに導電性の樹脂等（例えばＰＥＤＯＴ：ＰＳＳ等）を用いてもよい。この場合でも上記実施形態と同様の効果を得ることができる。他、金属材料７０の代わりに導電性材料であればどのようなものを用いてもよい。
本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれると同様に、特許請求の範囲に記載された発明とその均等の範囲に含まれるものである。
１ 半導体装置、１０ 配線基板、１４ ソルダレジスト層、１５ 絶縁層、２１ 電極ピラー、２０，３０〜３３ 半導体チップ、４０〜４３ 接着層、５０ スペーサチップ、６０ 接着層、７０ 金属材料、８０ 樹脂層、９０ ボンディングワイヤ、９１ 封止樹脂、ＯＰ 開口部、１１ 配線層

Claims (12)

  1. 配線層と該配線層上に設けられた絶縁層とを含み、前記絶縁層に設けられた開口部において前記配線層の一部を露出させた配線基板と、
    前記開口部に埋め込まれ、該開口部内の前記配線層を被覆する導電材料と、
    前記開口部内に挿入され前記導電材料に接続する電極を有する半導体チップとを備え、
    前記半導体チップの搭載方向から見たときに、前記電極と前記配線層とは離間しており、前記電極と前記配線層との間には前記導電材料が介在する、半導体装置。
  2. 前記電極の下端は、前記配線層の上面よりも下方に位置する、請求項１に記載の半導体装置。
  3. 前記電極の下端は、前記配線層の上面よりも上方に位置する、請求項１に記載の半導体装置。
  4. 前記搭載方向から見たときに、前記配線層の一部は、前記開口部から突出している、請求項１から請求項３のいずれか一項に記載の半導体装置。
  5. 前記配線層の一部は、前記開口部の内面に面しており、該内面において露出されている、請求項１から請求項３のいずれか一項に記載の半導体装置。
  6. 前記導電材料は、前記電極の側面に沿って前記開口部から盛り上がっている、請求項１から請求項５のいずれか一項に記載の半導体装置。
  7. 前記導電材料は、前記開口部に挿入されている前記電極の体積と同じかそれ以上の分だけ、前記電極の側面に沿って前記開口部から盛り上がっている、請求項６に記載の半導体装置。
  8. 前記電極は、前記配線基板の前記開口部の底部に接触している、請求項１から請求項７のいずれか一項に記載の半導体装置。
  9. 配線層と該配線層上に設けられた絶縁層とを含み、前記配線層の一部を露出するように該絶縁層に設けられた開口部に、液体またはペースト状の導電材料を供給し、
    半導体チップに設けられた電極を、前記開口部内の前記導電材料に挿入し、
    前記導電材料を硬化させる、ことを具備する半導体装置の製造方法。
  10. 前記配線基板の表面上に前記導電材料を供給し、前記配線基板の表面上を工具で走査することによって、前記導電材料を前記開口部に充填させつつ、余剰の前記導電材料を前記配線基板から除去することで前記開口部に導電材料が供給される請求項９に記載の半導体装置の製造方法。
  11. 前記半導体チップに設けられた電極を、前記開口部内の前記導電材料に挿入する前に、
    前記配線基板と前記半導体チップとの間に絶縁樹脂が供給される請求求項９または１０に記載の半導体装置の製造方法。
  12. 前記半導体チップに設けられた電極を、前記開口部内の前記導電材料に挿入した後に、
    前記配線基板と前記半導体チップとの間に絶縁樹脂が供給される請求求項９または１０に記載の半導体装置の製造方法。
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