JP5022756B2 - 半導体チップの実装方法 - Google Patents
半導体チップの実装方法 Download PDFInfo
- Publication number
- JP5022756B2 JP5022756B2 JP2007097492A JP2007097492A JP5022756B2 JP 5022756 B2 JP5022756 B2 JP 5022756B2 JP 2007097492 A JP2007097492 A JP 2007097492A JP 2007097492 A JP2007097492 A JP 2007097492A JP 5022756 B2 JP5022756 B2 JP 5022756B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- sealing resin
- semiconductor
- resin
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- Wire Bonding (AREA)
Description
5,5a 封止樹脂 6 (突起電極の)外側 10 半導体チップ
11 パッド電極 12 実装基板 20 半導体装置 100 半導体基板
101 突起電極 102 支持体 103 半導体チップ 104 保護膜
105 パッド電極 106 実装基板 107 封止樹脂
Claims (2)
- 半導体基板と、前記半導体基板の一方の面上に形成された複数の突起電極と、前記半導体基板の一方の面上に部分的に形成された封止樹脂とを備えた半導体チップを形成する工程と、
一方の面上に電極が形成された実装基板を準備し、前記突起電極と前記電極とを電気的に接触させ、かつ前記封止樹脂を軟化させて前記半導体チップと前記実装基板とを前記封止樹脂を介して接着させる工程と、
その後前記封止樹脂を硬化させる工程とを有し、
前記半導体チップを形成する工程は、前記突起電極の外側が前記封止樹脂から露出するように行われ、
前記封止樹脂は、前記半導体基板の一方の面上にペースト状の樹脂を形成する工程と、その後第1の熱処理を施して前記樹脂を半硬化させる工程を経て形成され、
前記半導体チップと前記実装基板とを前記封止樹脂を介して接着させる工程は、前記第1の熱処理よりも高温の第2の熱処理を施して前記封止樹脂の流動性を増加させる工程を含み、
前記封止樹脂を硬化させる工程は、前記第2の熱処理よりも高温の第3の熱処理を施す工程を含み、この封止樹脂を硬化させる工程の後においても前記突起電極の外側が前記封止樹脂から露出されていることを特徴とする半導体チップの実装方法。 - 前記封止樹脂は、前記複数の突起電極で囲まれていることを特徴とする請求項1に記載の半導体チップの実装方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007097492A JP5022756B2 (ja) | 2007-04-03 | 2007-04-03 | 半導体チップの実装方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007097492A JP5022756B2 (ja) | 2007-04-03 | 2007-04-03 | 半導体チップの実装方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008258318A JP2008258318A (ja) | 2008-10-23 |
JP5022756B2 true JP5022756B2 (ja) | 2012-09-12 |
Family
ID=39981608
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007097492A Expired - Fee Related JP5022756B2 (ja) | 2007-04-03 | 2007-04-03 | 半導体チップの実装方法 |
Country Status (1)
Country | Link |
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JP (1) | JP5022756B2 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8450859B2 (en) | 2008-10-27 | 2013-05-28 | Panasonic Corporation | Semiconductor device mounted structure and its manufacturing method |
US9368374B2 (en) | 2009-02-27 | 2016-06-14 | Dexerials Corporation | Method of manufacturing semiconductor device |
JP5423563B2 (ja) * | 2010-04-23 | 2014-02-19 | デクセリアルズ株式会社 | 半導体チップの製造方法 |
JP5720748B2 (ja) * | 2013-09-19 | 2015-05-20 | デクセリアルズ株式会社 | 半導体チップの製造方法 |
JP7360850B2 (ja) * | 2019-09-02 | 2023-10-13 | リンテック株式会社 | アンダーフィル剤塗布装置およびアンダーフィル剤塗布方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3648277B2 (ja) * | 1995-01-12 | 2005-05-18 | 株式会社東芝 | 半導体装置 |
JPH11219984A (ja) * | 1997-11-06 | 1999-08-10 | Sharp Corp | 半導体装置パッケージおよびその製造方法ならびにそのための回路基板 |
JP4206631B2 (ja) * | 2000-10-12 | 2009-01-14 | 住友ベークライト株式会社 | 熱硬化性液状封止樹脂組成物、半導体素子の組立方法及び半導体装置 |
JP3817594B2 (ja) * | 2002-02-27 | 2006-09-06 | 京セラキンセキ株式会社 | フリップチップの固着方法 |
JP3854979B2 (ja) * | 2004-08-05 | 2006-12-06 | 松下電器産業株式会社 | 電子部品の実装方法及び基板モジュール |
-
2007
- 2007-04-03 JP JP2007097492A patent/JP5022756B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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JP2008258318A (ja) | 2008-10-23 |
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