TWI546922B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TWI546922B
TWI546922B TW103145151A TW103145151A TWI546922B TW I546922 B TWI546922 B TW I546922B TW 103145151 A TW103145151 A TW 103145151A TW 103145151 A TW103145151 A TW 103145151A TW I546922 B TWI546922 B TW I546922B
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Taiwan
Prior art keywords
substrate
support material
conductive bumps
solder support
semiconductor device
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TW103145151A
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English (en)
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TW201535639A (zh
Inventor
林俊成
許峰誠
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台灣積體電路製造股份有限公司
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Description

半導體裝置及其製造方法
本申請案揭示內容係關於半導體裝置以及製造半導體裝置的方法。
具有半導體裝置的電子設備在我們的日常生活中是不可或缺的。隨著電子技術的進步，電子設備越來越複雜且具有越來越大量的積體電路，用以執行所要達到的多重功能。因此，半導體裝置的製造包含越來越多的組裝步驟，並且涉及不同物理性質的各種材料。因此，對於簡化製程步驟與改良半導體裝置的結構，具有持續性的需求。
在半導體裝置的製造操作過程中，以許多半導體元件組裝與整合成為半導體裝置，因此必須操作具不同物理與熱性質的各種材料。因此，在將半導體裝置硬化與回銲之後，整合的半導體元件形成不理想的架構。該不理想的架構會造成半導體裝置的產量損失、電連接效能不佳、元件之間的接合性弱、元件內發生破裂、元件脫層等。再者，不理想的元件架構與半導體裝置產量損失更加重材料浪費並且增加製造成本。
由於涉及不同的半導體元件以及具有不同性質的各種材料以及半導體裝置的製造操作複雜度增加，使得改良半導體裝置的結構架構與解決上述缺陷有更多的挑戰。
本申請案揭示內容的一些實施例係提供一種半導體裝置，其包括第一基板，其包含位於該第一基板的第一表面上之複數個第一墊；第二基板，其包含位於該第二基板的第二表面上之複數個第二墊；複數個傳導凸塊，其係對應接合該複數個第一墊與該複數個第二墊；焊接支撐材料，其係位於該第一表面上並且環繞該複數個傳導凸塊；底膠填充材料，其係環繞該複數個傳導凸塊並且位於該焊接支撐材料與該第二表面之間；以及粗糙界面，其係位於該焊接支撐材料與該底膠填充材料之間，其中該粗糙界面包含複數個突出部與複數個凹部。
本申請案揭示內容的一些實施例係提供一種半導體裝置，其包括基板，其包含表面；複數個傳導凸塊，其係位於該表面上並且配置為球柵陣列(BGA)；以及焊接支撐材料，其係位於該表面上方並且環繞該複數個傳導凸塊，其中該焊接支撐材料具有粗糙表面，其包含複數個突出部與複數個凹部，用於接收底膠填充材料。
本申請案揭示內容的一些實施例係提供一種製造半導體裝置的方法，其包括提供基板；在該基板的表面上，配置複數個墊；在該複數個墊上，對應配置複數個傳導凸塊；配置焊接支撐材料，其環繞該複數個傳導凸塊並且位於該基板的該表面上方；以及形成該焊接支撐材料的粗糙表面，其包含複數個突出部與複數個凹部。
100‧‧‧半導體裝置
101‧‧‧基板
101a‧‧‧晶粒
101b‧‧‧重佈層(RDL)
101c‧‧‧表面
102‧‧‧墊
103‧‧‧傳導凸塊
104‧‧‧焊接支撐材料
104a‧‧‧突出部
104b‧‧‧凹部
104c‧‧‧粗糙表面
104d‧‧‧間隙
104e‧‧‧間隔
105‧‧‧底膠填充材料
105a‧‧‧間隔
106‧‧‧基板
106a‧‧‧表面
107‧‧‧接合墊
108‧‧‧粗糙界面
109‧‧‧脫膜片
110‧‧‧參考線
111‧‧‧蝕刻劑
200‧‧‧半導體裝置
由以下詳細說明與附隨圖式得以最佳了解本申請案揭示內容之 各方面。強調根據產業之標準實施方式，各種特徵並非依比例繪示。實際上，為了清楚討論，可任意增大或縮小各種特徵的尺寸。
圖1係根據本申請案揭示內容的一些實施例說明半導體裝置的示意圖。
圖1A係根據本申請案揭示內容的一些實施例說明具有通過焊接支撐材料之粗糙表面的參考線之半導體裝置的示意圖。
圖1B係根據本申請案揭示內容的一些實施例說明焊接支撐材料的粗糙表面之放大圖。
圖2A係根據本申請案揭示內容的一些實施例說明具有一些傳導凸塊的半導體裝置之示意圖。
圖2B係根據本申請案揭示內容的一些實施例說明具有配置為球柵陣列(ball grid array)的一些傳導凸塊之半導體裝置的示意圖。
圖3係根據本申請案揭示內容的一些實施例說明具有第一基板與第二基板的半導體裝置之示意圖。
圖3A係根據本申請案揭示內容的一些實施例說明在兩個相鄰傳導凸塊之間的焊接支撐材料的粗糙表面之放大圖。
圖4係根據本申請案揭示內容的一些實施例說明製造半導體裝置的方法之流程圖。
圖4A係根據本申請案揭示內容的一些實施例說明具有第一基板的半導體裝置之示意圖。
圖4B係根據本申請案揭示內容的一些實施例說明第一基板上具有數墊的半導體裝置之示意圖。
圖4C係根據本申請案揭示內容的一些實施例說明具有一些傳導凸塊的半導體裝置之示意圖。
圖4D係根據本申請案揭示內容的一些實施例說明具有環繞傳導凸塊之焊接支撐材料的半導體裝置之示意圖。
圖4E係根據本申請案揭示內容的一些實施例說明第一基板上具有釋放膜的半導體裝置之示意圖。
圖4F係根據本申請案揭示內容的一些實施例說明具有粗糙表面的焊接支撐材料的半導體裝置之示意圖。
圖4G係根據本申請案揭示內容的一些實施例說明焊接支撐材料上具有蝕刻劑噴塗的半導體裝置之示意圖。
圖4H係根據本申請案揭示內容的一些實施例說明具有粗糙表面的焊接支撐材料的半導體裝置之示意圖。
圖4I係根據本申請案揭示內容的一些實施例說明半導體裝置與第二基板的示意圖。
圖4J係根據本申請案揭示內容的一些實施例說明第一基板的墊接合第二基板的墊之半導體裝置的示意圖。
圖4K係根據本申請案揭示內容的一些實施例說明第一基板與第二基板之間具有底膠填充材料之半導體裝置的示意圖。
以一些操作製造半導體裝置。在製造過程中，一些傳導凸塊(conductive bump)，例如焊接凸塊，以及焊球等係位於基板之底部表面上的數個接合墊上。而後，由焊接支撐材料(solder bracing material)環繞傳導凸塊，該焊接支撐材料係部分暴露且部分包覆該傳導凸塊。
當硬化焊接支撐材料時，硬化的焊接支撐材料提供保護予傳導凸塊，以免在後續製造操作過程中受到破壞。硬化的焊接支撐材料的表面係接觸黏著材料，該黏著材料為例如後續製程中的底膠填充(underfill)。傳導凸塊係接合另一基板上的接合墊，以及底膠填充材料係填充焊接支撐材料與基板之間的間隙。焊接支撐材料的表面係接 合底膠填充材料。
然而，焊接支撐材料與底膠填充材料具有不同的熱機械性質，因而它們之間的黏著強度在後續製造操作過程中可能逐漸降低。再者，在焊接支撐材料與底膠填充材料之間或是在焊接支撐材料與底膠填充材料之內，形成破裂或是應力集中點。該破裂甚至可能在後續製造操作過程中經由焊接支撐材料或是底膠填充材料傳遞而進一步減弱基板之間的電連接，並且在熱循環之後造成脫層，最後造成半導體裝置的故障。
以下詳細討論本申請案揭示內容的實施例之製造與用途。然而，應理解實施例提供許多可應用的本發明概念，其可實施於各種特定內容中。應理解以下的揭示內容係提供許多不同的實施例或是實施各種實施例之不同特徵的範例。以下所述之元件與配置的特定範例係用以簡化本申請案揭示內容。當然，以下說明僅為例示，而非用以限制本申請案之內容。
以下使用特定語言揭示圖式中所示之實施例或範例。然而，應理解實施例與範例並非用以限制本申請案之內容。該技藝中具有通常技術之人士可根據本申請案之內容而輕易理解所揭示之實施例中的任何變化與修飾以及本申請案所揭示之原理的任何進一步應用。
再者，應理解可僅簡要描述數個製程步驟以及/或裝置特徵。同樣地，可增加其他的製程步驟與/或特徵，以及可移除或改變一些以下的製程步驟與/或特徵，而仍屬於實施本申請案之申請專利範圍。因此，應理解以下說明僅為例示，並非用以推測需要一或多個步驟或是特徵。
此外，本申請案揭示內容在不同的範例中可重複元件符號與/或字母。此重複係為了簡化與清楚，而非指定不同實施例與/或架構之間的關係。
本申請案揭示內容係揭示具改良架構的半導體裝置。該半導體裝置係包含具粗糙表面的焊接支撐材料，該粗糙表面係與後續操作中的底膠填充材料接觸。焊接支撐材料的粗糙表面提供較多接觸面積給接合該焊接支撐材料的底膠填充材料，因而增加該焊接支撐材料與底膠填充材料之間的黏著強度。該粗糙表面具有足夠的表面粗造度，用以防止或甚至排除脫層問題以及半導體裝置內發生的破裂。具有粗糙表面的半導體裝置對於拉力測試(pull test)或是板層級熱循環測試(board level thermal cycling test)具有改良的可信賴度。因此，半導體裝置具有改良的效能。
圖1係半導體裝置100的實施例。半導體裝置100包含基板101。在一些實施例中，基板101攜載一些電路，並且支撐與積體電路連接的一些半導體元件。在一些實施例中，基板101係電路板，其包含一些電路用於電連接其上的元件。在一些實施例中，基板101係矽晶圓其可被製造成為後續製造操作中的積體電路(IC)。在一些實施例中，電路板係印刷電路板(PCB)。在一些實施例中，基板101係圓形。
在一些實施例中，基板101包含晶粒101a。晶粒101a係電連接至基板101內的電路。晶粒101a連接至基板101內的重佈層(redistribution layer，RDL)101b。RDL 101b係包含一些導電跡線(conductive trace)，用於電連接晶粒101a與外部電路至基板101。在一些實施例中，RDL係包含傳導材料，例如金、銀、銅、鎳、鎢、鋁、以及/或其合金。
在一些實施例中，墊102係位於基板101的表面101c上。墊102延伸平行於表面101c。在一些實施例中，墊102的俯視圖係圓形或是橢圓形。在一些實施例中，墊102係凸塊下金屬(under bump metallurgy，UBM)墊，用於接收傳導凸塊103，例如焊接凸塊、焊球、焊膏或類似物。UBM墊係可焊接的表面，其係暴露用於接收該傳導凸塊103，並且電連接至基板101內的電路。在例如回銲之加熱處 理之後，墊102係接合傳導凸塊103。在一些實施例中，墊102包含傳導材料，例如金、銀、銅、鎳、鎢、鋁、以及/或其合金。
在一些實施例中，傳導凸塊103係位於墊102上。在一些實施例中，藉由植球(ball drop)、模板印刷(stencil printing)、上漿(pasting)、電鍍、或類似方法，置放傳導凸塊103。在一些實施例中，傳導凸塊103係用以電連接位於另一基板上的墊。在一些實施例中，傳導凸塊103係由焊接材料製成，該焊接材料包含銅、錫、鋁、鋅、金、鉛、或類似物。在一些實施例中，傳導凸塊103係球形的銲球。
在一些實施例中，焊接支撐材料104係位於表面101c上，並且環繞傳導凸塊103。在一些實施例中，焊接支撐材料104亦環繞墊102的側壁。在一些實施例中，焊接支撐材料104係用以接收底膠填充材料。
在一些實施例中，焊接支撐材料104包含液體環氧化合物模塑料、介電膜、旋塗介電材料、或類似物。在一些實施例中，藉由成形、壓層、旋塗、或類似方法，置放焊接支撐材料。
在一些實施例中，焊接支撐材料104具有粗糙表面104c，其包含一些突出部104a以及一些凹部104b。突出部104a與凹部104b係彼此相間。在一些實施例中，粗糙表面104c係用於接收底膠填充材料。粗糙表面104c係提供更多接觸面積用於焊接支撐材料104與底膠填充材料之間的接合。在一些實施例中，粗糙表面104c係交錯構形(staggered configuration)。在一些實施例中，粗糙表面104c係彎曲表面，凹向基板101的表面101c。
在一些實施例中，粗糙表面104c的線粗糙度(line roughness)(Ra)係大於約1.3微米。在一些實施例中，粗糙表面104c的線粗糙度(Ra)係約1微米至約3微米。藉由線粗糙度量測法量測線粗糙度(Ra)，以下將進一步討論該量測法。
在一些實施例中，以受控的溫度與時間，藉由化學處理製備粗糙表面104c，例如在預定溫度與預定時間(duration)，以預定蝕刻劑進行化學蝕刻。在一些實施例中，藉由剝落膜而形成粗糙表面104c，該膜為例如位於部分硬化的焊接支撐材料104上之脫膜片(release film)。
在一些實施例中，粗糙表面104c上有一些間隙104d。間隙104d係位於突出部104a與凹部104b之間。在一些實施例中，粗糙表面104c的間隙104d係用於接收底膠填充材料。當傳導凸塊103與另一基板的墊接合時，用底膠填充材料填充間隙104d。
藉由不同的方法，量測焊接支撐材料104的粗糙表面104c之粗糙度。在一些實施例中，藉由線粗糙度(Ra)，判定焊接支撐材料104的粗糙度。在粗糙界面108的預定長度內，量測線粗糙度(Ra)。在一些實施例中，在圖1A所示的長度m’內，量測焊接支撐材料104的粗糙表面104c之線粗糙度(Ra)。在一些實施例中，該長度m’係約400微米。在一些實施例中，長度m’係約200微米至約600微米。在一些實施例中，該長度m’係與焊接支撐材料104所環繞的傳導凸塊103的尺寸成一比例。在一些實施例中，該長度m’與傳導凸塊103的尺寸之比例為1：3。在一些實施例中，該比例係約1：1.5至約1：10。
圖1B係焊接支撐材料104的粗糙表面104c的一部分之放大圖。在如圖1B所示的一些實施例中，在長度m’內，定義參考線110，用於量測粗糙表面104c的線粗糙度(Ra)。在一些實施例中，參考線110係定義於一位置，其中凹部104b(面積A)的面積總和係實質等於突出部104a(面積B)的面積總和。在一些實施例中，參考線110係通過粗糙表面104c的曲線。
在定義參考線110之後，得到長度m’內的粗糙表面104c上的一些高峰點。在一些實施例中，該高峰點係在粗糙表面104c之突出部104a的高峰位置以及粗糙表面104c之凹部104b的高峰位置。在一些實施例 中，高峰點(P1,P3,P5)係分別定義於凹部104b的高峰位置，以及高峰點(P2,P4,P6)係分別定義於突出部104a的高峰位置。
在定義高峰點(P1,P2,P3,P4,P5,P6)之後，分別得到參考線110與高峰點(P1,P2,P3,P4,P5,P6)之間的垂直距離。在一些實施例中，粗糙表面104c的線粗糙度(Ra)係參考線110與高峰點(P1,P2,P3,P4,P5,P6)之間的垂直距離總和之算術平均數。
在一些實施例中，該長度m’內的粗糙表面104c的線粗糙度(Ra)係大於約1.3微米。在一些實施例中，粗糙表面104c的線粗糙度(Ra)係約1微米至3微米。
圖2A係半導體裝置100的實施例。半導體裝置100包含基板101與基板101內的晶粒101a。在一些實施例中，基板101係晶粒基板。在一些實施例中，基板101包含基板101內的RDL 101b。RDL 101b連接晶粒101a至基板101的表面101c上的一些墊102。
在一些實施例中，一些傳導凸塊103係分別位於該墊102上。在一些實施例中，傳導凸塊103係配置為圖2B所示的球柵陣列(BGA)，圖2B係圖2A的仰視圖。傳導凸塊103係位於數列與數行中，如BGA或是矩陣。
在一些實施例中，焊接支撐材料104係環繞傳導凸塊103。傳導凸塊103係部分被焊接支撐材料104覆蓋，以及部分暴露用於接收另一基板上的墊。在一些實施例中，焊接支撐材料104係位於兩個相鄰傳導凸塊103之間。焊接支撐材料104填充兩個相鄰傳導凸塊103之間的間隔104e。
在如圖2A所示的一些實施例中，焊接支撐材料104具有粗糙表面104c，其包含一些突出部104a與一些凹部104b。粗糙表面104c係用於接收底膠填充材料。在如圖2B所示的一些實施例中，粗糙表面104c係環繞一些傳導凸塊103，並且位於半導體裝置100的底部上。從焊接支 撐材料104暴露部分的傳導凸塊103，以用於電連接另一基板。
圖3係半導體裝置200的實施例。半導體裝置200係包含基板101與基板101內的晶粒101a。在一些實施例中，基板101係晶粒基板。在一些實施例中，基板101包含基板101內的RDL 101b。RDL 101b連接晶粒101a至位於基板101的表面101c上的一些墊102。在一些實施例中，一些傳導凸塊103係分別位於墊102上。
在一些實施例中，焊接支撐材料104環繞傳導凸塊103。焊接支撐材料104係位於兩個相鄰的傳導凸塊103之間。焊接支撐材料104具有粗糙表面104c，其包含一些突出部104a與一些凹部104b。粗糙表面104c係用於接收底膠填充材料105。
在一些實施例中，基板106係用以電連接基板101內的電路。在一些實施例中，基板106係印刷電路板(PCB)。基板106包含一些接合墊107，其係位於基板106的表面106a上。接合墊107係用以接收墊102上對應的傳導凸塊103。傳導凸塊103係部分被焊接支撐材料104覆蓋，而部分暴露用於接收基板106上個別的接合墊107。傳導凸塊103係連接基板101上的墊102與基板106上的接合墊107，因而基板101的電路係電連接至基板106的電路。
在一些實施例中，底膠填充材料105係位於焊接支撐材料104的粗糙表面104c與基板106的表面106a之間。底膠填充材料105係環繞傳導凸塊103，並且填充兩個相鄰傳導凸塊103之間的間隔105a，因而傳導凸塊103係被焊接支撐材料104與底膠填充材料105包覆。
該底膠填充材料105係電絕緣黏著劑，用於固定基板101與基板106之間的接合。在一些實施例，底膠填充材料105包含環氧樹脂、環氧化合物模塑料或類似物。
在一些實施例中，焊接支撐材料104與底膠填充材料105之間有粗糙界面108。在一些實施例中，底膠填充材料105填充傳導凸塊103 之間的間隙104d，以配置粗糙界面108。在一些實施例中，粗糙界面108包含一些突出部104a與一些凹部104b。在一些實施例中，粗糙界面108係凹向基板101的表面101c。
在一些實施例中，粗糙表面108包含焊接支撐材料104的粗糙部與底膠填充材料105的粗糙部，其係與焊接支撐材料104的粗糙部互補。粗糙界面108接合焊接支撐材料104與底膠填充材料105。
在一些實施例中，藉由不同的方法，量測焊接支撐材料104的粗糙界面108之粗糙度。在一些實施例中，用線粗糙度(Ra)判定焊接支撐材料104的粗糙度。在粗糙界面108的預定長度內，量測線粗糙度(Ra)。在一些實施例中，在長度m內，量測粗糙界面108的線粗糙度(Ra)。該長度m係代表在距離d的中心處之距離d的一半之寬度，其中距離d係代表兩個相鄰傳導凸塊103的腰部之間的距離。在一些實施例中，從相鄰的傳導凸塊103其中之一的最外表面至該相鄰的傳導凸塊103之另一個的最外表面，量測距離d。在一些實施例中，距離d係相鄰的傳導凸塊103其中之一的最外表面與該相鄰的傳導凸塊103之另一個的最外表面之間的最短距離。
圖3A係焊接支撐材料104與底膠填充材料105的粗糙界面108之一部分的放大圖。在如圖3A所示之一些實施例中，在長度m內定義參考線110，用於量測粗糙界面108的線粗糙度(Ra)。長度m係距離d的一半距離。距離d係兩個相鄰傳導凸塊103的最外表面之間的距離。在一些實施例中，參考線110係定義於一位置，其中凹部104b(面積A’)的面積總和係實質等於突出部104a(面積B’)的面積總和。在一些實施例中，參考線110係通過粗糙界面108的曲線。
在定義參考線110之後，得到長度m內的粗糙界面108上的一些高峰點。在一些實施例中，該高峰點係在粗糙界面108之突出部104a的高峰位置以及粗糙界面108之凹部104b的高峰位置。在一些實施例 中，高峰點(P1’,P3’)係分別定義於凹部104b的高峰位置，以及高峰點(P2’,P4’)係分別定義於突出部104a的高峰位置。
在定義高峰點(P1’,P2’,P3’,P4’)之後，分別得到參考線110與高峰點(P1’,P2’,P3’,P4’)之間的垂直距離。在一些實施例中，粗糙界面108的線粗糙度(Ra)係參考線110與高峰點(P1’,P2’,P3’,P4’)之間的垂直距離總和之算術平均數。
在一些實施例中，長度m內的粗糙界面108之線粗糙度(Ra)係大於約1.3微米。在一些實施例中，粗糙界面108之線粗糙度(Ra)係約1微米至約3微米。
本申請案揭示內容亦揭示製造半導體裝置的方法。在一些實施例中，藉由一方法形成半導體裝置，該方法包含一些操作，其描述與說明並不被視為操作順序的限制。
圖4係製造半導體裝置的方法300之實施例。該方法300包含一些操作(301、302、303、304、305、306、307、308以及309)。
在操作301中，提供如4A所示之第一基板101。在一些實施例中，第一基板101係晶粒基板，其包含在第一基板101內的至少一晶粒101a。在一些實施例中，第一基板101係用於接收另一基板並且電連接另一基板。在一些實施例中，第一基板101包含矽。在一些實施例中，第一基板101包含第一基板101內的電路。該電路包含第一基板101內的一些導電跡線，以連接第一基板101上的一些半導體元件。
在操作302中，一些墊102係位於第一基板101的第一表面101c上，如圖4B所示。墊102係在第一表面101c上彼此相隔。在一些實施例中，各個墊102係用於接收傳導凸塊，作為第一基板101與另一基板之間的電連接。
在操作303中，一些傳導凸塊103係對應位於墊102上，如圖4C所示。傳導凸塊103係用於接合在個別墊102的表面102a上。在一些實施 例中，藉由刻板(stencil)、上焊料(solder pasting)、電鍍、或類似方法，在表面102a上形成傳導凸塊103。在一些實施例中，各個傳導凸塊103係焊球或焊膏或是類似物。在一些實施例中，各個傳導凸塊103係圓筒形、半球形或是球形。
在操作304中，焊接支撐材料104係位於第一表面101c上，並且環繞傳導凸塊103，如圖4D所示。在一些實施例中，焊接支撐材料104係位於至少兩相鄰傳導凸塊103之間。在一些實施例中，藉由成形、壓層或是旋塗，置放焊接支撐材料104。
在一些實施例中，形成焊接支撐材料104並且填充表面101c上方的兩相鄰傳導凸塊103之間的間隔，而後藉由熱處理，將焊接支撐材料104硬化，該熱處理為例如回銲，因而在表面101c以及傳導凸塊103之間的間隔上，形成焊接支撐材料104。在一些實施例中，用焊接支撐材料104包覆傳導凸塊103。傳導凸塊103係部分暴露而與另一基板接合。
在一些實施例中，藉由操作(305a、306a)形成焊接支撐材料104的粗糙表面104c，如圖4E與圖4F所示。在操作305a中，脫膜片109係位於焊接支撐材料104與傳導凸塊103上，如圖4E所示。在一些實施例中，脫膜片109係暫時附接與覆蓋傳導凸塊103的暴露部分與焊接支撐材料104。在一些實施例中，在傳導凸塊103與焊接支撐材料104上方，藉由成形或旋塗，形成脫膜片109。而後，藉由回銲或是其他熱處理，硬化脫膜片109。在一些實施例中，脫膜片109包含黏著材料，例如環氧樹脂。
在操作306a中，移除脫膜片109，形成粗糙表面104c，如圖4F所示。在一些實施例中，當焊接支撐材料104係部分硬化時，從焊接支撐材料104剝除脫膜片109，因而移除一些焊接支撐材料104，而形成粗糙表面104c。
在一些實施例中，脫膜片位於傳導凸塊103與焊接支撐材料104上經預定時間之後且在預定溫度下，移除脫膜片109，因而形成包含一些突出部104a與一些凹部104b的粗糙表面104c。在粗糙表面104c具有足夠的線粗糙度(Ra)，用於在後續操作中接收底膠填充材料。
在一些實施例中，藉由操作(305b、306b)形成焊接支撐材料104的粗糙表面104c，如圖4G與圖4H所示。在一些實施例中，藉由蝕刻，形成粗糙表面104c。在操作305b中，蝕刻劑111係位於焊接支撐材料104上，如圖4G所示。在一些實施例中，在蝕刻之前，翻轉半導體裝置100。傳導凸塊103係面朝上，如圖4G所示。在一些實施例中，在翻轉半導體裝置100之後，藉由噴塗將蝕刻劑111置於焊接支撐材料104上。蝕刻劑111塗佈在焊接支撐材料104上。在一些實施例中，在焊接支撐材料上，選擇性噴塗蝕刻劑111。
在操作306b中，用蝕刻劑111蝕刻移除一些焊接支撐材料104，形成粗糙表面104c，如圖4H所示。在一些實施例中，在預定時間內及預定溫度下，蝕刻劑111在焊接支撐材料104上，因而蝕刻劑111移除且蝕刻一些焊接支撐材料104，以形成焊接支撐材料104的粗糙表面104c。在一些實施例中，在預定時間內及預定溫度下，形成包含一些突出部104a與一些凹部104b的粗糙表面104c，因而粗糙表面104c具有足夠的線粗糙度(Ra)，用於在後續操作中接收底膠填充材料。在一些實施例中，翻轉半導體裝置100，因而在蝕刻之後，傳導凸塊103係面朝向而進行後續操作。
在操作307中，提供第二基板106，如圖4I所示。在一些實施例中，第二基板106係PCB，其包含第二基板106內的電路。在一些實施例中，第二基板106係用於電連接第二基板106的電路與第一基板101的電路。在一些實施例中，第二基板106為條形(strip form)。在一些實施例中，第二基板106包含陶瓷、銅、或其他。
在一些實施例中，一些接合墊107係位於第二基板106上。在一些實施例中，接合墊107係沿著第二基板106的表面106a延伸。在一些實施例中，接合墊107係用於分別接收第一基板101上的傳導凸塊103。
在操作308中，第一基板101上的傳導凸塊103係與第二基板106的接合墊107對應接合，如圖4J所示。在一些實施例中，傳導凸塊103係附接於接合墊107上，用以電連接第一基板101內的電路與第二基板106。藉由傳導凸塊103，接合第一基板101的墊102與第二基板106的接合墊107。
在一些實施例中，當第一基板101的墊102與第二基板106的接合墊107接合時，傳導凸塊103形成為焊接凸塊或是焊球。在一些實施例，傳導凸塊103為球形。在一些實施例中，藉由上焊料(solder pasting)使得傳導凸塊103位於墊102與接合墊107之間。
在操作309中，底膠填充材料105係位於焊接支撐材料104與第二基板106之間，如圖4K所示。在一些實施例中，底膠填充材料105流入且填充粗糙表面104c的突出部104a與凹部104b之間的一些間隙104d，使得底膠填充材料105環繞傳導凸塊103的暴露部分。傳導凸塊103最終係被焊接支撐材料104與底膠填充材料105包覆。
在一些實施例中，在配置底膠填充材料105之後，藉由在焊接支撐材料104與底膠填充材料105之間形成粗糙界面104c，而促使第一基板101與第二基板106之間的接合。在一些實施例中，粗糙界面104c包含焊接支撐材料104的粗糙部以及底膠填充材料的粗糙部，其係與焊接支撐材料104的粗糙部互補。
在一些實施例中，粗糙界面104c在焊接支撐材料104與底膠填充材料105之間提供一些摩擦力，因而促使第一基板101與第二基板106之間的接合。
粗糙界面104c增加焊接支撐材料104與底膠填充材料105之間以及第一基板101與第二基板106之間的接合強度。因此，改良半導體裝置200的可信賴度。在焊接支撐材料與底膠填充材料之間含有粗糙界面104c的半導體裝置200已將破裂與脫層的發生最小化，並且在拉力測試(pull test)、板層級熱循環測試(board level thermal cycling test)或其他測試中具有改良的效能。
在一些實施例中，半導體裝置包含第一基板與第二基板，該第一基板含有複數個第一墊位於第一基板的第一表面上，該第二基板含有複數個第二墊位於該基板的第二表面上，複數個傳導凸塊對應接合該複數個第一墊與該複數個第二墊，焊接支撐材料位於該第一表面上並且環繞該複數個傳導凸塊，底膠填充材料環繞該複數個傳導凸塊並且位於該焊接支撐材料與該第二表面之間，以及粗糙界面位於該焊接支撐材料與該底膠填充材料之間，該粗糙界面包含複數個突出部與複數個凹部。
在一些實施例中，粗糙界面具有線粗糙度(Ra)，其係大於約1.3微米。在一些實施例中，粗糙界面包含焊接支撐材料的粗糙部以及底膠填充材料的粗糙部，其係與該焊接支撐材料的粗糙部互補。
在一些實施例中，粗糙界面的寬度係實質等於約一半的兩個相鄰傳導凸塊之間的距離。在一些實施例中，底膠填充材料係位於焊接支撐材料上，並且填充該複數個突出部與該複數個凹部。
在一些實施例中，粗糙界面係凹向第一表面。在一些實施例中，第一基板係晶粒基板，以及第二基板係印刷電路板(PCB)。在一些實施例中，粗糙界面係交錯構形(staggered configuration)。
在一些實施例中，半導體裝置係包含具有一表面的基板、位於該表面上且配置為球柵陣列(BGA)的複數個傳導凸塊、位於該表面上方且環繞該複數個傳導凸塊的焊接支撐材料、該焊接支撐材料具有粗 糙表面，其含有複數個突出部與複數個凹部，用於接收底膠填充材料。在一些實施例中，粗糙表面的線粗糙度(Ra)係大於約1.3微米。在一些實施例中，焊接支撐材料係包含液體環氧化合物模塑料、介電膜或旋塗介電材料。
在一些實施例中，製造半導體裝置的方法包含提供基板、在該基板的表面上，配置複數個墊、在該複數個墊上，對應配置複數個傳導凸塊、配置環繞該複數個傳導凸塊且位於該基板的該表面上方的焊接支撐材料，以及形成該焊接支撐材料的粗糙表面，其包含複數個突出部與複數個凹部。
在一些實施例中，形成具有線粗糙度(Ra)大於約1.3微米的該粗糙表面。在一些實施例中，該方法進一步包含在該焊接支撐材料及該複數個傳導凸塊上，配置脫膜片。在一些實施例中，該方法進一步包含當該焊接支撐材料係部分硬化時，移除位於該焊接支撐材料及該複數個傳導凸塊上的脫膜片。
在一些實施例中，該方法進一步包含在兩個相鄰傳導凸塊之間的距離之一半的寬度中，量測該粗糙表面的線粗糙度(Ra)。在一些實施例中，該方法進一步包含定義通過該粗糙表面的參考線，用於量測該粗糙表面的線粗糙度(Ra)。在一些實施例中，該方法進一步包含藉由探針接觸該焊接支撐材料上的複數個點而量測該粗糙表面的線粗糙度(Ra)。
在一些實施例中，該方法進一步包括移除該複數個傳導凸塊之間的該焊接支撐材料的複數個部分，以形成該粗糙表面。在一些實施例中，該方法進一步包含在預定時間內及預定溫度下，以預定的蝕刻劑蝕刻該焊接支撐材料，以形成該粗糙表面。
上述的範例與說明已充分描述本發明的方法與特徵。應理解不脫離本發明之精神的任何修飾或變化係被涵蓋於本發明的保護範圍 內。
再者，本申請案的範圍不受限於說明書中所述之製程、機械、製造、物質組合物、手段、方法以及步驟的特定實施例。熟知此技藝之人士可從本申請案揭示內容，輕易理解根據本申請案揭示內容，可使用進行與本申請案所述對應實施例實質相同的功能或是達到實質相同的結果之現存的或是未來發展的製程、機械、製造、物質的組合物、手段、方法或步驟。
據此，申請專利範圍包含例如製程、機械、製造、物質的組合物、手段、方法或是步驟。除此之外，每一請求項組成個別的實施例，並且不同請求項與實施例之組合仍係屬本發明的範圍。
100‧‧‧半導體裝置
101‧‧‧基板
101a‧‧‧晶粒
101b‧‧‧重佈層(RDL)
101c‧‧‧表面
102‧‧‧墊
103‧‧‧傳導凸塊
104‧‧‧焊接支撐材料
104a‧‧‧突出部
104b‧‧‧凹部
104c‧‧‧粗糙表面
104d‧‧‧間隙

Claims (10)

  1. 一種半導體裝置，其包括：第一基板，其包含位於該第一基板的第一表面上之複數個第一墊；第二基板，其包含位於該第二基板的第二表面上之複數個第二墊；複數個傳導凸塊，其係對應接合該複數個第一墊與該複數個第二墊；焊接支撐材料，其係位於該第一表面上並且環繞該複數個傳導凸塊；底膠填充材料，其係環繞該複數個傳導凸塊並且位於該焊接支撐材料與該第二表面之間；以及粗糙界面，其係位於該焊接支撐材料與該底膠填充材料之間，其中該粗糙界面包含複數個突出部與複數個凹部，該焊接支撐材料被該第一基板、該底膠填充材料及該第二基板完全包覆。
  2. 如請求項1所述之半導體裝置，其中該粗糙界面的線粗糙度(Ra)係大於約1.3微米。
  3. 如請求項1所述之半導體裝置，其中該粗糙界面包含該焊接支撐材料的粗糙部以及該底膠填充材料的粗糙部，其係與該焊接支撐材料的該粗糙部互補。
  4. 如請求項1所述之半導體裝置，其中該粗糙界面的寬度係實質等於兩個相鄰傳導凸塊之間約一半的距離。
  5. 一種半導體裝置，其包括：第一基板，其包含位於該第一基板的第一表面上之複數個第 一墊；第二基板，其包含位於該第二基板的第二表面上之複數個第二墊；複數個傳導凸塊，其係對應接合該複數個第一墊與該複數個第二墊；焊接支撐材料，其係位於該第一表面上方並且環繞該複數個傳導凸塊；以及底膠填充材料，其係環繞該複數個傳導凸塊及該焊接支撐材料，其中該焊接支撐材料具有粗糙表面，其包含複數個突出部與複數個凹部，該粗糙表面與該底膠填充材料接合，該底膠填充材料從該第一基板橫向地突出以包覆該焊接支撐材料。
  6. 如請求項5所述之半導體裝置，其中該粗糙表面的線粗糙度(Ra)係大於約1.3微米。
  7. 一種製造半導體裝置的方法，其包括：提供基板；在該基板的表面上，配置複數個墊；在該複數個墊上，對應配置複數個傳導凸塊；配置焊接支撐材料，其環繞該複數個傳導凸塊並且位於該基板的該表面上方；在該焊接支撐材料及該複數個傳導凸塊上配置脫膜片；以及移除在該焊接支撐材料及該複數個傳導凸塊上的該脫膜片，以形成該焊接支撐材料的粗糙表面，其包含複數個突出部與複數個凹部。
  8. 如請求項7所述之方法，其中當該焊接支撐材料係部分硬化時，移除位於該焊接支撐材料及該複數個傳導凸塊上的該脫膜片。
  9. 如請求項7所述之方法，其進一步包括在兩個相鄰傳導凸塊之間的距離之一半的寬度中，量測該粗糙表面的線粗糙度(Ra)；或定義通過該粗糙表面的參考線，用於量測該粗糙表面的線粗糙度(Ra)。
  10. 如請求項7所述之方法，其進一步包括移除該複數個傳導凸塊之間的該焊接支撐材料的複數個部分，以形成該粗糙表面。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102373440B1 (ko) * 2017-03-17 2022-03-14 삼성디스플레이 주식회사 디스플레이 패널 및 이를 구비하는 디스플레이 장치
JP7207150B2 (ja) * 2019-05-15 2023-01-18 株式会社デンソー 半導体装置
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Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6512182B2 (en) * 2001-03-12 2003-01-28 Ngk Spark Plug Co., Ltd. Wiring circuit board and method for producing same
US6696644B1 (en) * 2002-08-08 2004-02-24 Texas Instruments Incorporated Polymer-embedded solder bumps for reliable plastic package attachment
US20040155358A1 (en) * 2003-02-07 2004-08-12 Toshitsune Iijima First and second level packaging assemblies and method of assembling package
TWI240399B (en) * 2004-04-06 2005-09-21 Advanced Semiconductor Eng Chip package structure and process for fabricating the same
TWI309456B (en) * 2004-04-27 2009-05-01 Advanced Semiconductor Eng Chip package structure and process for fabricating the same
CN101826496B (zh) 2005-05-23 2015-03-18 揖斐电株式会社 印刷线路板及其制造方法
WO2006126361A1 (ja) * 2005-05-24 2006-11-30 Matsushita Electric Industrial Co., Ltd. ハンダバンプ形成方法および半導体素子の実装方法
US7786001B2 (en) * 2007-04-11 2010-08-31 International Business Machines Corporation Electrical interconnect structure and method
TW200903756A (en) * 2007-06-18 2009-01-16 Samsung Electronics Co Ltd Semiconductor chip package, semiconductor package including semiconductor chip package, and method of fabricating semiconductor package
JP2009099597A (ja) * 2007-10-12 2009-05-07 Nec Electronics Corp 半導体装置およびその製造方法
US7821130B2 (en) 2008-03-31 2010-10-26 Infineon Technologies Ag Module including a rough solder joint
US8426959B2 (en) * 2009-08-19 2013-04-23 Samsung Electronics Co., Ltd. Semiconductor package and method of manufacturing the same
US8058108B2 (en) * 2010-03-10 2011-11-15 Ati Technologies Ulc Methods of forming semiconductor chip underfill anchors
US8629053B2 (en) * 2010-06-18 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Plasma treatment for semiconductor devices
JP5675443B2 (ja) * 2011-03-04 2015-02-25 新光電気工業株式会社 配線基板及び配線基板の製造方法
US9437564B2 (en) * 2013-07-09 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method of fabricating same
US9589862B2 (en) * 2013-03-11 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming same

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US10020275B2 (en) 2018-07-10
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US20150187716A1 (en) 2015-07-02
US11742310B2 (en) 2023-08-29
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DE102014118931A1 (de) 2015-07-02
DE102014118931B4 (de) 2022-12-01

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