TWI574364B - 封裝體及其製作方法 - Google Patents

封裝體及其製作方法 Download PDF

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Publication number
TWI574364B
TWI574364B TW103145293A TW103145293A TWI574364B TW I574364 B TWI574364 B TW I574364B TW 103145293 A TW103145293 A TW 103145293A TW 103145293 A TW103145293 A TW 103145293A TW I574364 B TWI574364 B TW I574364B
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Taiwan
Prior art keywords
pad portion
bonding pad
metal wire
substrate
package
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TW103145293A
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English (en)
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TW201532231A (zh
Inventor
李明機
梁裕民
陳玉芬
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台灣積體電路製造股份有限公司
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Publication of TW201532231A publication Critical patent/TW201532231A/zh
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Description

封裝體及其製作方法
本發明係關於一種封裝體，特別係關於一種具有由焊墊重疊的嵌入金屬導線之基板的封裝體。
在一個像是覆晶晶片尺寸封裝(flip chip Chip Scale Package,fcCSP)的封裝體中，透過銅柱導線直連(bump on trace,BOT)互連，一積體電路(integrated circuit,IC)可能被安裝在基板上(例如：印刷電路板(printed circuit board,PCB)或其它積體電路載體)。
有鑑於對更小封裝體的需求，經常嘗試的是減少相鄰凸塊之間的距離，其中以凸塊間距為人所知。一種減少凸塊間距的方式是藉由縮短在BOT互連中所使用的金屬導線的寬度。不幸地是，減少金屬導線的寬度可能導致一些不想要或不利的結果。
一種實施例封裝體包括：一導電柱，安裝在積體電路晶片上，此導電柱具有階梯形狀，一金屬導線，部分 嵌入一基板中，此金屬導線具有一接合墊部從此基板突出，以及一焊接部，電耦合此導電柱至此金屬導線的此接合墊部。
一種實施例封裝體包括：一導電柱，安裝在一積體電路晶片上，此導電柱具有一階梯形狀且定義一導電柱高度，一金屬導線，部分嵌入一基板中，此金屬導線具有一接合墊部從此基板突出，此接合墊部定義一接合墊部高度，此接合墊部高度大於或等於此導電柱高度，以及一焊接部，電耦合此導電柱至此金屬導線的此接合墊部。
一種形成一封裝體之製作方法，包括：安裝具有階梯形狀的一導電柱在一積體電路晶片上，部分嵌入一金屬導線在一基板中，此金屬導線具有一接合墊部從此基板突出，以及電耦合此導電柱至此金屬導線的此接合墊部。
10‧‧‧實施例封裝體
12‧‧‧導電柱
14‧‧‧裝置層
16‧‧‧積體電路晶片
18‧‧‧基板
20‧‧‧接合墊部
22‧‧‧導線
24‧‧‧焊接部
26‧‧‧底部封膠或封膠化合物
30‧‧‧金屬材料
32‧‧‧突出焊墊結構
34‧‧‧光刻膠
36‧‧‧抗焊塗層
為了更加徹底的了解本案發明和其優點，參照下列敘述搭配附圖，其中：第1圖說明具有階梯形狀的導電柱和提供突出的接合墊部的部分嵌入金屬導線的實施例封裝體的截面圖；第1A-1B圖說明傳統的探針測試配置的截面圖；第1C圖說明實施例的探針測試配置的截面圖；第2圖說明具有階梯形狀的導電柱和提供階梯形狀突出接合墊部的部分嵌入金屬導線的實施例封裝體的截面圖； 第3圖說明具有階梯形狀的導電柱和提供反向階梯形狀突出接合墊部的部分嵌入金屬導線的實施例封裝體的截面圖；第4圖說明具有提供較長的突出接合墊部的部分嵌入金屬導線的實施例封裝體；第5圖說明具有提供甚至更長的突出接合墊部的部分嵌入金屬導線的實施例封裝體；第6A-6F圖共同地繪示形成第1-3圖的實施例封裝體的流程；第7A-7F圖共同地繪示形成第4-5圖的實施例封裝體的流程；第8A-8B圖說明傳統封裝體的截面圖；以及第8C圖說明使用突出和嵌入兩種導線的實施例封裝體的截面圖。
除非另外指出，否則在不同圖片中的數字和符號參考相對應的段落，以這些圖片清楚的說明這些實施例相關的方面，且並不需要依比例繪製。
以下詳細討論本案實施例的製作和利用，但是，應該知道的是本案發明提供許多可實施的發明概念，可以在各種特定內容中被體現，被討論的特定實施例僅作為釋義且並不用來限制本案發明範圍。
本案發明將以在特定內容中的一些實施例來描 述，即一種與BOT互連合併的封裝體，但是，本案中的概念也可以應用在其它的封裝體、互連封裝或半導體結構。
現在參考第1圖，說明實施例封裝體10，以下將更徹底的解釋，舉例來說，由於在積體電路晶片16和基板18之間的熱膨脹係數(coefficient of thermal expansion,CTE)不匹配，導電柱12的幾何形狀可預防或是抑制導電柱12從積體電路晶片16的裝置層14中的介電層脫層。
此外，金屬導線22的連接墊部20的幾何形狀可預防或是抑制相鄰導線間之焊接部24的不欲產生之橋接、導電柱12和金屬導線22之間的冷接合(cold joining)，以及金屬導線22從基板18剝落。
在第1圖中，為了底部封膠或封膠化合物26的引入，當凸塊間距縮減時，導電柱12和/或金屬導線22的構型也確保在積體電路晶片16和基板18之間有足夠的相隔距離，此構型也提供足夠的空間以允許BOT連接的測試，例如使用探針或是其他的測試配備，精確來說，如第1A-1B圖所示，在傳統的測試構型中可能歷經一些測試困難，在第1A圖中，如果導線22的接合墊部20突出在基板18的頂部表面之上，當探針針尖不慎同時接觸預設導線22的接合墊部20和相鄰的鄰近導線22的接合墊部20，可能會觸發表示斷路的假警報。在第1B圖中，當所有的導線22嵌入在基板18中時，探針針尖不易接觸導線22。相反的，如第1C圖所示，當導線22的構型交替，使得一條導線22包括一突出的接合 墊部20和嵌入在基板18中的鄰近導線22，在第1A-1B圖所遇到的困難或問題即可被克服，換句話說，使用圖1C的定位，探測的間距至少為兩倍。
如第1圖所示，實施例封裝體10包括積體電路晶片16(亦稱裸晶)，在一實施例中，積體電路晶片16包括一或更多有介電材料的裝置層14。舉例來說，介電材料可能為超低介電係數(extrememly low-k,ELK)介電質，如本文所用，ELK和具有約或少於2.5的介電常數的介電材料有關，且更佳的，介電常數在1.9和2.5之間，裝置層14可能包括單層介電材料或是多層介電材料。
導電柱12安裝在積體電路晶片16的底側，在一實施例中，導電柱12接合或是緊鄰在積體電路晶片16中的最外的裝置層14中的介電材料，如圖所示，晶片在覆晶封裝過程中被翻覆後，導電柱12在積體電路晶片16的下方延伸。
在一實施例中，導電柱12具有階梯形狀，與反向的截錐相似，因此，當導電柱12延伸離開積體電路晶片16且朝向基板18，導電柱12的直徑或是寬度縮減，換句話說，如第1圖所示的位向，導電柱12從底部(靠近積體電路晶片16)至頂部(靠近焊接部)逐漸變小。
雖然第1圖中的導電柱被描述具有線形的錐形，導電柱12可能具有彎曲的、梯形的側壁或其他構型，且仍被考慮具有階梯形狀，在一實施例中，導電柱12由適合的材料形成，舉例來說：銅、鎳、金、鈀、鈦或其合金。
依然參考第1圖，實施例封裝體10也包括金屬導線22，在一實施例中，金屬導線22由銅、鎳、金、鋁、銀或其合金形成。在一實施例中，金屬導線22以表面處理覆蓋，舉例來說，表面處理如：有機保焊劑(organic solderability preservative,OSP)、化錫(immersion tin)等等。
金屬導線22被部分嵌入基板18，因為金屬導線22被部分嵌入，金屬導線22可提供接合墊部20，如圖所示，接合墊部20突出或是從下面的基板18突出，換句話說，接合墊部20配置在基板18的頂部表面之上，且不會被基板18封裝。
在一實施例中，接合墊部20的頂部寬度a等於或約等於接合墊部20的底部寬度b。在一實施例中，接合墊部20的底部寬度b大於或等於約10μm且小於或等於約25μm。在一實施例中，接合墊部20的高度hs(亦稱厚度)，大於或等於約1μm且小於或等於約20μm。在一實施例中，導電柱12的高度hw大於或等於約20μm且小於約50μm。
焊接部24(例如：焊點)電耦合導電柱12至金屬導線22的接合墊部20，在一實施例中，焊接部24為焊球、焊膏、或其他導電組件適合將裝置電耦合在一起。在一實施例中，焊接部24由可被迴焊以將裝置電連接在一起的材料所形成。
現在參考第2圖，在一實施例中，接合墊部20的底部寬度b大於接合墊部20的頂部寬度a，在此構型中， 接合墊部20具有階梯形狀，換句話說，接合墊部20的直徑從底部至頂部逐漸變小(換言之，越遠離接合墊部20突出的基板18，接合墊部20的圓周變小)。
在一實施例中，接合墊部20當滿足公式b-a>0.36hs-0.1時，使用第2圖所示的階梯形狀，其中，b為接合墊部的底部寬度，a為接合墊部的頂部寬度，以及hs為接合墊部的高度。
現在參考第3圖，在一實施例中，接合墊部20的頂部寬度a大於接合墊部20的頂部寬度b，在此構型中，接合墊部20具有反向階梯形狀，換句話說，接合墊部20的直徑從頂部至底部逐漸變小(換言之，越遠離接合墊部20突出的基板18，接合墊部20的圓周變大)。
在一實施例中，接合墊部20當滿足公式a-b>0.36hs-0.1時，使用第3圖所示的反向階梯形狀，其中，a為接合墊部的頂部寬度，b為接合墊部的底部寬度，以及hs為接合墊部的高度。
關於第4-5圖，發現導電柱12的高度hw對於ELK的應力有影響，精確來說，當現導電柱12的高度hw減少時，柱的尺寸d會變大。因此，當發生熱膨脹係數不匹配，焊接部24會變形以吸收部分的力，隨著柱的尺寸d越大，在導電柱12的側邊變形的量也隨之減少且在突出的接合墊部20的側邊變形的量也隨之增加，對ELK產生較小的應力。
不幸的，留意上述的導電柱12的高度hw的減少可能減少相隔高度(即為積體電路晶片16和基板18之間的 距離)，當相隔高度減少太多，在此區域中，底部封膠或封膠化合物26的引入會受到負面的影響，舉例來說，因為可能發生小的相隔尺寸空隙，因此，裝置有失敗的可能性以及可信度會下降。
為了解決當導電柱的高度hw減少時所發生的問題，打算使用更長的接合墊部20，以下將徹底的解釋清楚，金屬導線22的更高或更厚的接合墊部20維持足夠的相隔尺寸以確保底部封膠或封膠化合物26有合適和平穩的流動。
如第4-5圖所示，在一實施例中，金屬導線22的接合墊部20的高度hs被增加與導電柱12的高度hw有關，舉例來說，接合墊部20的高度hs可能大於或等於導電柱12的高度。
如第4圖所示，在一實施例中，當接合墊部20的高度hs大於或等於約20μm且小於或等於約40μm，導電柱12的高度hw大於或等於約10μm且小於或等於約30μm。
如第5圖所示，在一實施例中，當接合墊部20的高度hs大於或等於約20μm且小於或等於約40μm，導電柱12的高度hw大於或等於約1μm且小於或等於約10μm。
第6A-6F圖共同地繪示形成第1-3圖的實施例封裝體10的流程，在第6A圖中，使用載體28實施無核建立流程(coreless build-up process)，如圖所示，在無核建立流程中，為了形成每條金屬導線22，引入金屬材料30(例如：銅等等)進入基板18的開口。
如第6B圖所示，一旦金屬材料30在基板18中適當地被形成，突出焊墊結構32將被分開或從載體28釋出，之後。在圖6C中，在金屬材料30之上形成光刻膠34(photo resist,PR)且圖案化光刻膠34，在一實施例中，在光刻過程中，由調控曝光和顯影參數控制光刻膠34的側壁角度(以虛線和箭頭強調)。
在光刻膠34被圖案化後，如第6D圖所示進行金屬電鍍(例如：銅電鍍)步驟，進行電鍍步驟以沉積或引入金屬材料30進入圖案化後的光刻膠34的開口中。一旦光刻膠34如第6E圖所示被移除，進行金屬蝕刻步驟以移除在相鄰金屬導線的接合墊部20之間的金屬材料30部分。
在第6E圖的實施例中，金屬導線22的接合墊部20具有階梯形狀，換句話說，當接合墊部20突出遠離基板18時，接合墊部20的直徑遞減。
如第6F圖所示，在金屬導線22的接合墊部20被用來在封裝體10中形成電連結之前，可能在基板18的一些部份上形成抗焊塗層36。必須承認，在實際的應用中，製作第1-5圖的封裝體10的過程中，可能需要執行一些額外的步驟。
第7A-7F圖共同地繪示形成第4-5圖的實施例封裝體的流程，在第7A圖中，使用載體28實施無核建立流程，如圖所示，在無核建立流程中，為了形成金屬導線22，引入金屬材料30(例如：銅等等)進入基板18的開口。
如圖7B所示，一旦在基板18中適當地形成金屬 材料30，突出焊墊結構32將被分開或從載體28釋出；之後，在圖7C中，在金屬材料30之上形成光刻膠34(photo resist,PR)且圖案化光刻膠34。在一實施例中，舉例來說，在第7C圖中，光刻膠34的厚度更大於第6C圖中的光刻膠34的厚度。此外，在一實施例中，光刻膠34的側壁為垂直方向(換句話說，以金屬材料30的頂部表面做出直角)。
在光刻膠34被圖案化後，如第7D圖所示進行金屬電鍍(例如：銅電鍍)步驟，進行電鍍步驟以沉積或引入金屬材料30進入圖案化後的光刻膠34的開口中。一旦光刻膠34如第7E圖所示被移除，進行金屬蝕刻步驟以移除在相鄰金屬導線22的接合墊部20之間的金屬材料30部分。
在第7E圖的實施例中，金屬導線22的接合墊部20具有矩形形狀。換句話說，當接合墊部從基板18突出遠離時，接合墊部20具有相當固定的直徑。此外，在第7E圖中的接合墊部20基本上比第6E圖描繪的接合墊部20更高(或更厚)，因此，在第7E圖中的接合墊部20可能被稱為長形的接合墊部20。
如第7F圖所示，在金屬導線22的接合墊部20被用來在封裝體10中形成電連結之前，可能在基板18的一些部份上形成抗焊塗層36，必須承認，在實際的應用中，製作第1-5圖的封裝體10的過程中，可能需要執行一些額外的步驟。
從前述的敘述，應該可以理解其中揭露的實施例封裝體提供了一些具有優點的益處和特徵，舉例來說，因 為積體電路晶片16和基板18之間的熱膨脹係數不匹配會使導電柱從晶片的超低介電係數介電層脫層。因此，導電柱12的幾何形狀可以預防或是抑制導電柱12從積體電路晶片16的超低介電係數介電層脫層，此外，金屬導線22的突出的接合墊部20的幾何構型可以預防或是抑制相鄰導線間之焊接部24的不欲產生之橋接、導電柱12和金屬導線22之間的冷接合，以及金屬導線22從基板18剝落。
如第8A圖所示，在傳統的構型中，可能因為鄰近導線之間的微小間距而產生短路(以鄰近導線間的箭頭所示)。如第8B圖所示，在傳統的構型中，除非基板18凹槽的凸塊及導線精確對齊，否則可能發生斷路，相反的，其中導線22交替(例如：一條導線22從基板18突出且相鄰的導線22嵌入基板18)，如圖8C所示，短範圍及開放範圍皆被修正，精確來說，其中跑線(passing line)或導線22被置於凸塊結構之間，利用凸出導線22，使得實施例封裝10的組裝過程被改善。
一種實施例封裝體包括：一導電柱，安裝在積體電路晶片上，此導電柱具有階梯形狀，一金屬導線，部分嵌入一基板中，此金屬導線具有一接合墊部從此基板突出，以及一焊接部，電耦合此導電柱至此金屬導線的此接合墊部。
一種實施例封裝體包括：一導電柱，安裝在一積體電路晶片上，此導電柱具有一階梯形狀且定義一導電柱高度，一金屬導線，部分嵌入一基板中，此金屬導線具有一 接合墊部從此基板突出，此接合墊部定義一接合墊部高度，此接合墊部高度大於或等於此導電柱高度，以及一焊接部，電耦合此導電柱至此金屬導線的此接合墊部。
一種形成一封裝體之實施例方法，包括：安裝具有階梯形狀的一導電柱在一積體電路晶片上，部分嵌入一金屬導線在一基板中，此金屬導線具有一接合墊部從此基板突出，以及電耦合此導電柱至此金屬導線的此接合墊部。
雖然本案發明提供了一些說明實施例，這些敘述並非想要被理解成限制性的意思，對於該領域之習知技藝者而言，說明實施例和除此之外的其它實施例的各種修飾和組合在參考內文敘述後是顯而易知的，因此，意指所附的專利範圍涵蓋任何此類的變型或實施例。
10‧‧‧實施例封裝體
12‧‧‧導電柱
14‧‧‧裝置層
16‧‧‧積體電路晶片
18‧‧‧基板
20‧‧‧接合墊部
22‧‧‧導線
24‧‧‧焊接部
26‧‧‧底部封膠或封膠化合物

Claims (10)

  1. 一種封裝體，包括：一導電柱，安裝在一積體電路晶片上，該導電柱具有一階梯形狀；一第一金屬導線，部分嵌入一基板中，該第一金屬導線具有一接合墊部從該基板突出；一第二金屬導線，嵌入該基板中，且鄰近該第一金屬導線，該第二金屬導線的頂部表面低於該基板的頂部表面；以及一焊接部，電耦合該導電柱至該金屬導線的該接合墊部。
  2. 如請求項1之封裝體，其中該接合墊部具有一階梯形狀。
  3. 如請求項1之封裝體，其中該接合墊部具有一反向階梯形狀。
  4. 如請求項1之封裝體，其中該接合墊部當滿足一公式b-a>0.36hs-0.1時，使用一階梯形狀，其中，b為該接合墊部的一底部寬度，a為該接合墊部的一頂部寬度，以及hs為該接合墊部的一高度。
  5. 如請求項1之封裝體，其中該接合墊部當滿足一公式a-b>0.36hs-0.1時，使用一反向階梯形狀， 其中，a為該接合墊部的一頂部寬度，b為該接合墊部的一底部寬度，以及hs為該接合墊部的一高度。
  6. 一種封裝體，包括：一導電柱，安裝在一積體電路晶片上，該導電柱具有一階梯形狀且定義一導電柱高度；一金屬導線，部分嵌入一基板中，該金屬導線具有一接合墊部從該基板突出，該接合墊部定義一接合墊部高度，該接合墊部高度大於或等於該導電柱高度；一焊接部，電耦合該導電柱至該金屬導線的該接合墊部；以及一鄰近的金屬導線，嵌入在該基板中，且鄰近該金屬導線，該鄰近的金屬導線的頂部表面低於該基板的頂部表面。
  7. 如請求項6之封裝體，其中該積體電路晶片包括具有一超低介電係數介電層鄰接該導電柱的一裝置層。
  8. 一種形成一封裝體之製作方法，包括：安裝具有一階梯形狀的一導電柱在一積體電路晶片上；接收一基板，該基板具有一第一開口；以一第一金屬材料填滿該第一開口，並覆蓋該基板的一上表面； 形成一圖案化光刻膠於該第一金屬材料上，該圖案化光刻膠具有一第二開口，該第二開口暴露出位於該第一開口上的該第一金屬材料；填入一第二金屬材料於該第二開口中；移除該圖案化光刻膠及位於該圖案化光刻膠下的該第一金屬材料，以形成一金屬導線，該金屬導線具有一接合墊部從該基板突出；以及電耦合該導電柱至該金屬導線的該接合墊部。
  9. 如請求項8之方法，進一步包括形成該接合墊部使得該接合墊部具有一階梯形狀。
  10. 如請求項8之方法，進一步包括形成該接合墊部使得該接合墊部具有一反向階梯形狀。
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10011478B2 (en) 2015-05-18 2018-07-03 Innovative Micro Technology Thermocompression bonding with raised feature
KR101672640B1 (ko) * 2015-06-23 2016-11-03 앰코 테크놀로지 코리아 주식회사 반도체 디바이스
JP6755558B2 (ja) * 2016-06-09 2020-09-16 イノベイティブ マイクロ テクノロジーＩｎｎｏｖａｔｉｖｅ Ｍｉｃｒｏ Ｔｅｃｈｎｏｌｏｇｙ 隆起特徴部を有する熱圧着
KR102696423B1 (ko) 2019-08-14 2024-08-20 삼성전자주식회사 반도체 장치

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201208024A (en) * 2010-07-08 2012-02-16 Tessera Inc Microelectronic packages with dual or multiple-etched flip-chip connectors
TW201246466A (en) * 2010-12-22 2012-11-16 Intel Corp Device packaging with substrates having embedded lines and metal defined pads

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3346985B2 (ja) 1996-06-20 2002-11-18 東芝マイクロエレクトロニクス株式会社 半導体装置
US6087251A (en) 1998-10-30 2000-07-11 United Microelectronics Corp. Method of fabricating a dual damascene structure
JP3606769B2 (ja) 1999-07-13 2005-01-05 新光電気工業株式会社 半導体装置
US6352916B1 (en) 1999-11-02 2002-03-05 Micron Technology, Inc. Method of forming plugs in multi-level interconnect structures by partially removing conductive material from a trench
US6350386B1 (en) * 2000-09-20 2002-02-26 Charles W. C. Lin Method of making a support circuit with a tapered through-hole for a semiconductor chip assembly
US6388322B1 (en) * 2001-01-17 2002-05-14 Aralight, Inc. Article comprising a mechanically compliant bump
EP1386353A2 (en) 2001-05-01 2004-02-04 Koninklijke Philips Electronics N.V. Method of manufacturing interconnections in a semiconductor device
US6348398B1 (en) 2001-05-04 2002-02-19 United Microelectronics Corp. Method of forming pad openings and fuse openings
JP3910379B2 (ja) 2001-06-12 2007-04-25 インターナショナル・ビジネス・マシーンズ・コーポレーション ボール・グリッド・アレイ・モジュール用の多層基板の製造方法
TWI221664B (en) 2002-11-07 2004-10-01 Via Tech Inc Structure of chip package and process thereof
US7112524B2 (en) 2003-09-29 2006-09-26 Phoenix Precision Technology Corporation Substrate for pre-soldering material and fabrication method thereof
KR101249555B1 (ko) 2003-11-10 2013-04-01 스태츠 칩팩, 엘티디. 범프-온-리드 플립 칩 인터커넥션
JP3961537B2 (ja) 2004-07-07 2007-08-22 日本電気株式会社 半導体搭載用配線基板の製造方法、及び半導体パッケージの製造方法
JP2008535225A (ja) 2005-03-25 2008-08-28 スタッツ チップパック リミテッド 基板上に狭い配線部分を有するフリップチップ配線
JP5291917B2 (ja) 2007-11-09 2013-09-18 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US8659172B2 (en) 2008-12-31 2014-02-25 Stats Chippac, Ltd. Semiconductor device and method of confining conductive bump material with solder mask patch
US9607936B2 (en) 2009-10-29 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Copper bump joint structures with improved crack resistance
JP5544872B2 (ja) 2009-12-25 2014-07-09 富士通セミコンダクター株式会社 半導体装置及びその製造方法
KR101077304B1 (ko) 2010-03-08 2011-10-26 주식회사 하이닉스반도체 반도체 소자의 제조 방법
US8127979B1 (en) 2010-09-25 2012-03-06 Intel Corporation Electrolytic depositon and via filling in coreless substrate processing
US20120098120A1 (en) 2010-10-21 2012-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Centripetal layout for low stress chip package
US8344493B2 (en) 2011-01-06 2013-01-01 Texas Instruments Incorporated Warpage control features on the bottomside of TSV die lateral to protruding bottomside tips
TWI562295B (en) 2012-07-31 2016-12-11 Mediatek Inc Semiconductor package and method for fabricating base for semiconductor package
US9177899B2 (en) * 2012-07-31 2015-11-03 Mediatek Inc. Semiconductor package and method for fabricating base for semiconductor package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201208024A (en) * 2010-07-08 2012-02-16 Tessera Inc Microelectronic packages with dual or multiple-etched flip-chip connectors
TW201246466A (en) * 2010-12-22 2012-11-16 Intel Corp Device packaging with substrates having embedded lines and metal defined pads

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