TWI453840B - 半導體元件的製造方法 - Google Patents

半導體元件的製造方法 Download PDF

Info

Publication number
TWI453840B
TWI453840B TW97108282A TW97108282A TWI453840B TW I453840 B TWI453840 B TW I453840B TW 97108282 A TW97108282 A TW 97108282A TW 97108282 A TW97108282 A TW 97108282A TW I453840 B TWI453840 B TW I453840B
Authority
TW
Taiwan
Prior art keywords
layer
semiconductor device
semiconductor substrate
electrodes
electrode
Prior art date
Application number
TW97108282A
Other languages
English (en)
Other versions
TW200924090A (en
Inventor
Chung Yu Wang
Chien Hsiun Lee
Pei Haw Tsao
Kuo Chin Chang
Chung Yi Lin
Bill Kiang
Original Assignee
Taiwan Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Publication of TW200924090A publication Critical patent/TW200924090A/zh
Application granted granted Critical
Publication of TWI453840B publication Critical patent/TWI453840B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02313—Subtractive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0235—Shape of the redistribution layers
    • H01L2224/02351—Shape of the redistribution layers comprising interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/1148—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
    • H01L2224/13027—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body the bump connector being offset with respect to the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48647—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

半導體元件的製造方法
本發明係有關於晶圓級晶片尺寸封裝(wafer level chip－scale packaging,WLCSP)，且特別是關於增進WLCSP中之銲球接點(solder ball joints)的可靠度。
在過去幾十年來，電子與半導體封裝技術之進步已衝擊整個半導體工業。導入表面接合技術(surface－mount technology,SMT)與球柵陣列(ball grid array,BGA)封裝對於多種積體電路元件的高產率封裝通常是重要的步驟，且還同時允許印刷電路板上之接墊間距縮小。通常積體電路之封裝結構基本上由晶片上的金屬接墊與散佈自封裝體的電極間之細金線來形成內連線。雙列式封裝(dual inline package,DIP)與四方扁平封裝(quad flat package,QFP)是目前積體電路封裝的基本結構。然而，隨著週邊設計與排列於封裝體之針腳數目(pin count)的增加，使導線間之間距過小而限制電路板之晶片封裝。
晶片尺寸封裝(CSP)及球柵陣列(BGA)封裝為在不大幅增加封裝尺寸情況下，使電極之排列緊密的一種解決方案。CSP提供晶片尺寸之晶圓封裝。CSP之封裝結構一般小於1.2倍的晶粒尺寸，大幅縮小以CSP封裝之元件的尺寸。雖然，這些優點已使電子元件小型化，但一直以來對於更小、更輕、及更薄電子產品之需求，更加小型化封裝結構的追求仍未曾間斷。
為了滿足市場對於更小型化與更多功能化電子產品之需求，近年來導入了晶圓級晶片尺寸封裝(WLCSP)以增加元件密度、增進效能、與節省成本，並同時減小電子封裝工業中之元件的重量與尺寸。在WLCSP封裝中，封裝體通常直接形成於晶粒上，晶粒具有由球柵陣列及凸塊電極(bump electrodes)所提供之接點(contact)。近來之先進電子元件，例如行動電話、筆記型電腦、攝影機、個人數位助理(PDAs)等，利用了密集且輕薄之緊密封裝積體電路。使用WLCSP以較少數目的接腳來封裝較小晶粒尺寸之元件，可於一晶圓上形成更多之晶片，具有更高的成本效益。
現今的WLCSP技術之一缺點是銲球與柱電極(electrode post)間會形成裂痕(cracks)。銲球或凸塊一般直接放置於凸塊電極或柱電極上，靠焊接點(solder joint)來維持結構整體性。形成WLCSP元件之不同材料層之間一般具有不同的熱膨脹係數(CTE)。因此，由不同熱膨脹係數所引起之較大應力會發生在與柱電極及凸塊電極之間的接點，常常在凸塊電極/柱電極與銲球或凸塊間之接合區造成裂縫。此外，銲球一般位於晶圓的材料層上方。銲球接合處之露出使銲球更容易受到物理衝擊的影響，並亦使較脆弱之接點露出。
第1圖顯示典型WLCSP封裝結構10之單一銲球的剖面圖。WLCSP封裝結構直接形成於晶粒100上。在晶粒100上形成有銅墊102。銅墊102作為銲球101之接觸點與接墊。在焊接製程期間，金屬間化合物(intermetallic compounds,IMC)會於銲球101與銅墊102之間的接點自然地形成為一材料層(例如IMC形成層103)。雖然IMC形成層103之存在通常意味著銲料與基底間有良好的焊接，但IMC形成層103通常是焊接點之最脆弱部分。因為在WLCPS封裝中之焊接點非常小，使得裂痕(crack)(例如裂痕104)在應力施加於接點時可能更容易形成，且這樣的裂痕由於整體封裝結構尺寸較小，可能對結構傷害更大。再者，IMC形成層103位於晶粒100之上表面上，因此會將此較脆弱區域曝露於較大的直接應力衝擊。沿著銲球101之一側生成之小裂痕(例如裂痕104)可容易地沿著焊接點橫截面方向傳播而變大。
美國專利US 6,600,234(Kuwabara,et al.)揭露一種可減小上述應力裂痕的方法。此方法係使用多層材料層來形成密封膜(sealing film)，其中部分的凸塊電極自密封膜突出。突出的電極輔助吸收部份由熱膨脹係數不同所造成之應力。密封層之多層材料層之選擇亦可具有逐漸改變的熱膨脹係數，使接近基底之材料層具有與基底相近的熱膨脹係數，而接近電路基底之材料層具有與電路基底相近的熱膨脹係數。此逐漸改變的熱膨脹係數有助於緩和由急遽熱膨脹係數差異所造成之應力。然而，密封層之多層材料層通常仍呈現較低的剪切強度(shear strength)，且無法減輕可能形成於IMC形成層中之裂縫的傳播，因而減低接點的整體可靠度。
美國專利US 6,717,245(Kinsman,et al.)另提出一種增進晶片尺寸封裝的方法。此方法以環氧樹脂(epoxy)或其他相似材料完全封裝第一凸塊層(bumped layer)。接著研磨封裝層以露出包裝於其中之凸塊的頂部。接著將一般的銲球印刷或放置於第一凸塊層之露出部分上。藉著透過第一凸塊層之封裝層而將銲球與電路板隔離，可減小熱膨脹所造成之應力。然而，銲球接點仍容易沿著IMC形成層生成裂縫，因而減低接點的整體可靠度。
美國專利US 6,906,418(Hiatt,et al.)另提出一種增進晶片尺寸封裝的方法。此方法提供兩種不同的CSP封裝實施例。第一實施例將來自晶粒接墊之內連線接點(interconnect contact)的尖端部份(tip)延伸穿過絕緣層。在沉積金屬化材料層於內連線接點的尖端部份後，將銲球放置於每一延伸尖端部份上。金屬化材料層之材質係選用能增進金屬化材料層與銲球間之接合的材料。然而，因為銲球接點位於或高於絕緣層表面，銲球接點仍有不小的剪切應力。第二實施例提供之銲球係直接放置於晶粒接墊上或重分佈層上。接著使用絕緣層將銲球封裝，並留下部分露出區以用於接觸。雖然此實施例增進銲球接點之強度，但將銲球直接放置於晶粒接墊上需複雜的設計程序，會大幅增加CSP封裝的成本。此外，內連線接點的結構亦會受限於晶粒接墊之結構。
本發明提供一種半導體元件的製造方法，包括在半導體基底之第一表面形成至少一柱電極，其中每一柱電極包括兩個以上柱狀物之陣列，柱電極電性連接至半導體基底之線路層，沉積緩衝層於第一表面上，緩衝層密封陣列，移除部份的緩衝層及部分的柱電極，而使柱電極之上表面低於殘餘之緩衝層之上表面，沉積導電覆蓋層於柱電極之上表面上，其中導電覆蓋層低於殘餘之緩衝層之上表面，以及放置銲球於導電覆蓋層上，其中銲球與導電覆蓋層之間的焊接點低於殘餘之緩衝層之上表面。
本發明另提供一種半導體元件的製造方法，包括形成複數個電極於半導體基底之第一表面上，其中電極凸出第一表面，將一材料鍍至電極上；沉積緩衝層於第一表面上，電極延伸穿過緩衝層，選擇性蝕刻緩衝層以使電極之上表面低於殘餘之緩衝層之上表面，以及放置銲球於每一電極上，其中銲球與電極之間的接點低於緩衝層之上表面，及其中銲球透過材料及電極電性連接至半導體基底之線路層。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
第2圖顯示本發明一實施例之WLCSP封裝結構20的剖面圖。晶圓200包括形成於其上之柱電極201。絕緣層202形成於晶圓200之頂部上，且圍繞柱電極201。在製造過程期間，柱電極201之頂部與絕緣層202之頂部同高。接著將柱電極201回蝕刻而使低於絕緣層202之頂部。在較佳實施例中，因為絕緣層202之材質是特別選定，使柱電極201之回蝕刻不會對絕緣層202造成影響，所以不需使用額外的光阻層來進行蝕刻。
沉積覆蓋層203於柱電極201上，覆蓋層203保護柱電極201免於氧化。在一較佳實施例中，柱電極201之材質是銅。因此覆蓋層203可保護銅柱電極201免於氧化。可以各種不同的方法沉積覆蓋層203，包括無電電鍍法(electroless plating)或其相似方法。接著將銲球204焊接、連接、或印刷至晶圓200上。焊接後形成接點(joint)於覆蓋層203的頂部，且接點低於絕緣層202。因此，銲球204部分低於絕緣層202，且部分高於絕緣層202(另一部分)。再者，IMC層205(金屬間化合物層)形成於銲球204與覆蓋層203間之接合處，因此IMC層205受到絕緣層202之保護而免於受到直接物理接觸。藉著配置晶圓200使銲球204部分高於絕緣層202，並部分低於絕緣層202，且使焊接點低於絕緣層202之上表面，以及利用覆蓋層205保護柱電極201免於受到氧化，此結構之焊接點會更可靠且具有較強的剪切與一般強度。
第3A圖顯示本發明一實施例之WLCSP封裝結構30之前段製程步驟剖面圖。晶粒300包括保護層302與高分子絕緣層303。位於晶粒300頂部之線路層301連接至晶粒300中之電路層(未顯示)。沉積重分佈層304於晶粒300之高分子絕緣層303之頂部上。重分佈層304將電性連接延伸至線路層301。
應注意的是高分子絕緣層303可包括多種絕緣材料，例如聚亞醯胺(polyimide)或其他相似的高分子絕緣材料。第3A－3E圖所提供之敘述並非意圖將本發明限定之絕緣層限定為任何特定材料。事實上，在其他實施例中，WLCSP封裝結構可不包括絕緣層(例如高分子絕緣層303)。
請參照第3B圖，沉積柱電極305於晶粒300上。柱電極305可與重分佈層304直接物理接觸而形成與線路層301之間的電性連接。因此，與柱電極305接觸可形成電性連接至晶粒300中之電路層(未顯示)。重分佈層304之材質可選自多種有益的導電材料，例如銅、金、鋁、錫、任何有益的導電材料之結合或合金、或前述之組合。
第3C圖顯示本發明一實施例之WLCSP封裝結構30之下一製程步驟剖面圖。沉積緩衝層306於晶粒300之頂部上以增加對於晶粒300與柱電極305之保護。在一些實施例中，緩衝層306之選用可部分基於材料之熱膨脹係數，以減少WLCSP封裝結構因不同材料層之不同熱膨脹係數所形成的應力。緩衝層306可例如包括環氧樹脂、聚亞醯胺、或其相似物。本發明較佳實施例之緩衝層306的材質選擇基準可亦考量緩衝層306之材質對於可能用以蝕刻柱電極305之蝕刻劑的耐蝕程度。
第3D圖顯示本發明一實施例之WLCSP封裝結構30之下一製程步驟剖面圖。使用不會影響緩衝層306之蝕刻劑將柱電極305回蝕刻而使低於緩衝層306之頂部。在執行此步驟時，可不使用其他光阻層而將柱電極305回蝕刻。在將柱電極305回蝕刻後，沉積覆蓋層307於柱電極305上而覆蓋柱電極305所露出之表面，但仍使覆蓋層307之頂部低於緩衝層306之頂部。藉著覆蓋柱電極305之露出表面，覆蓋層307保護柱電極305免於氧化。覆蓋層307之材質係選用導電材料，因而仍能維持覆蓋層307與線路層301之間的電性連接。例如，覆蓋層307之材質可為鎳、錫、其他相似材料、前述之合金、或前述之組合。
第3E圖顯示本發明一實施例之WLCSP封裝結構30的剖面圖。在沉積覆蓋層307於每一柱電極(例如柱電極305)後，將銲球308印刷或焊接至柱電極305/覆蓋層307上。因此，形成於銲球308與覆蓋層307間之接點會低於緩衝層306之頂部。因此，緩衝層306可提供焊接點一保護屏障。再者，形成於焊接點之IMC層亦受到緩衝層306之保護。所完成的WLCSP封裝結構30具有更強且更可靠之焊接點。
第4A－4E圖顯示本發明一實施例於半導體晶圓40上形成WLCSP封裝結構的一系列製程剖面圖。半導體晶圓40包括基底400、晶粒接墊401(die contact)、保護層402、絕緣層403、及重分佈層404。藉著重分佈層404之使用，封裝設計與積體電路之佈局可更流暢，這是因為封裝結構之位置不會受限於晶粒接墊(例如晶粒接墊401)之位置。
形成多柱狀物柱電極405(multi－column electrode post)於重分佈層404上以提供電性接觸至晶粒接墊401(如第4B圖所示)。多柱狀物柱電極405可使用形成金屬層之任何方法來形成。例如，可放置光阻層或薄片於半導體晶圓40之頂部，光阻層或薄片上具有凹槽以蝕刻其下之金屬層於而形成多柱狀物柱電極405。或者，可於光阻層或薄片之凹槽中填充導電材料來形成多柱狀物柱電極405。多柱狀物柱電極405之材質包括銅、鎳、鋁、鎢、前述之相似物、前述之合金、或前述之組合。
在顯示於第4A－4E圖中之WLCSP封裝結構之實施例中，每一多柱狀物柱電極405之柱狀物可較佳具有介於約10微米至約20微米之間的外徑，且每一柱狀物之間的間距較佳介於約10微米至約20微米之間。接著沉積封裝材料(例如應力緩衝層)於具有上述較佳尺寸柱狀物之封裝結構上。
第4C圖顯示沉積於半導體晶圓40之頂部上的緩衝層406。緩衝層406將每一多柱狀物柱電極405之柱狀物密封於其中。緩衝層406之密封增強多柱狀物柱電極405之強度。如第4D圖所示，將緩衝層406回蝕刻而露出多柱狀物柱電極405，並於其上沉積低反應層407(low reactive layer)。低反應層407之材質較佳包括能增強與銲球或凸塊間之接合的材料，且亦具有較小IMC缺陷成長速度。低反應層407之材質例如包括鎳、錫、其相似物、或前述之組合。
一旦沉積了低反應層407於多柱狀物柱電極405，可將銲球408印刷或放置於半導體晶圓40上(如第4E圖所示)。低反應層407被放置於緩衝層406之表面下方，因此銲球408與低反應層407間之銲球接點低於緩衝層406之表面。此設計提供一些防護以抵抗產生在銲球408上之剪切應力，又緩衝層406之材質係選用具有特定熱膨脹係數之材料，亦可減低銲球接點上之熱膨脹應力。
第4A－4E圖所敘述之多柱狀物柱電極的實施例較單柱柱電極之實施例有較佳的封裝應力抵抗力。首先，因為與銲球之接點分散在每一柱狀物上，裂痕將無法輕易地沿著整個接點傳播。因為裂痕會沿著破裂線(fracture line)傳播，所以裂痕僅會往單一柱狀物內部傳播，而不再沿著整個接點的橫截面方向傳播。再者，埋在各柱狀物間之應力緩衝層可進一步增強裂縫抵抗力(因為具有金屬柱狀物/緩衝層複合結構)。緩衝層之材料特性(例如有機應力緩衝材料)可增進具有金屬柱狀物/緩衝層複合結構之多柱狀物柱電極結構對於裂縫的抵抗力。
第5A－5E圖顯示本發明一實施例於半導體晶圓50上形成WLCSP封裝結構的一系列製程剖面圖。第5A圖顯示半導體晶圓50，包括積體電路層500、接墊501、金屬電鍍晶種層502、重分佈層503、及光阻層504。凹槽506已藉著蝕刻進入光阻層504而形成，且凹槽506之內壁還覆蓋有電鍍金屬層505。如第5B圖所示，接著形成導電柱507於凹槽506中。形成導電柱507之前可選擇性地移除凹槽506外之電鍍金屬層505。
應注意的是電鍍金屬層505與導電柱507較佳選用不同的導電材料。例如，電鍍金屬層505可包括鎳、錫、銅、其相似物、或前述之組合，而導電柱507可包括銅、銲錫、錫、鎳、其相似物、或前述之組合。當電鍍金屬層505之材質包括鎳時，銲料/銅之IMC層的成長會減低。當電鍍金屬層505之材質包括鎳而導電柱507之材質包括銲錫時，此柱狀結構較使用材質較硬的銅柱狀結構更具韌性。因此，當封裝結構受到熱應力時，柱狀結構可承受較大的變形而可減低銲球接點上的應力程度。
在第5C圖中，將光阻層504移除，且將金屬電鍍晶種層502回蝕刻使與重分佈層503對齊。接著如第5D圖所示，沉積緩衝層508於半導體晶圓50上以封裝各元件，包括電鍍金屬層505及導電柱507。如第5E圖所示，研磨緩衝層508降低其上表面，並進一步蝕刻導電柱507使低於緩衝層508之表面。接著如第5F圖所示，將銲球509印刷或放置於半導體晶圓50上，使銲球接點低於緩衝層508之表面。藉著將銲球接點放置於緩衝層508之表面下，可有效地使銲球接點遠離高應力區域，因此銲球接點會受到較小的剪切應力。
第6圖顯示本發明一實施例之製程流程圖。在步驟600中，形成至少一柱電極於半導體基底之第一表面上，其中每一柱電極由兩個以上柱狀物之陣列形成，且電性連接至半導體基底之線路層。在步驟601中，沉積緩衝層於第一表面上以封裝柱電極之柱狀物陣列。在步驟602中，移除部份柱電極而使柱電極之上表面低於緩衝層之上表面。在步驟603中，沉積導電覆蓋層於露出的多柱狀物柱電極之上表面上，其中導電覆蓋層亦低於緩衝層之上表面。在步驟604中，將銲球放置於每一導電覆蓋層上，其中銲球與導電覆蓋層間之接點低於緩衝層之頂部。
第7圖顯示本發明另一實施例之製程流程圖。在步驟700中，形成複數個電極於半導體基底之第一表面，其中電極突出第一表面。在步驟701中，將電鍍材料電鍍於電極。在步驟702中，沉積緩衝層於第一表面而完全覆蓋電極之延伸。在步驟703中，選擇性蝕刻緩衝層而使電極之上表面露出並低於緩衝層之頂部。在步驟704中，將銲球放置於每一電極上，其中銲球與每一電極間之接點低於緩衝層之頂部，且銲球透過電鍍材料與電極而電性連接至半導體基底之導線層。
第8圖顯示本發明又一實施例之製程流程圖。在步驟800中，形成複數個柱電極於半導體基底之第一表面，其中每一柱電極是由兩個以上之柱狀物陣列所形成。在步驟801中，將一電鍍材料電鍍至多柱狀物柱電極上。在步驟802中，沉積緩衝層於第一表面上，其中多柱狀物柱電極延伸穿過緩衝層。在步驟803中，選擇性蝕刻緩衝層而使多柱狀物柱電極之上表面露出並低於緩衝層之頂部。在步驟804中，將銲球放置於每一多柱狀物柱電極上，其中銲球與每一多柱狀物柱電極間之接點低於緩衝層之頂部，且銲球透過電鍍材料與多柱狀物柱電極而電性連接至半導體基底之線路層。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10、20、30．．．WLCSP封裝結構
100、300．．．晶粒
102．．．銅墊
101、204、308、408、509．．．銲球
103．．．IMC形成層
104．．．裂痕
200．．．晶圓
201、305．．．柱電極
202、403．．．絕緣層
203、307．．．覆蓋層
205．．．IMC層
302、402．．．保護層
303．．．高分子絕緣層
301．．．線路層
304、404、503．．．重分佈層
306、406、508．．．緩衝層
40、50．．．半導體晶圓
400．．．基底
401．．．晶粒接墊
405．．．多柱狀物柱電極
407．．．低反應層
500．．．積體電路層
501．．．接墊
502．．．金屬電鍍晶種層
504．．．光阻層
505．．．電鍍金屬層
507．．．導電柱
600、601、602、603、604、700、701、702、703、704、800、801、802、803、804．．．步驟
第1圖顯示典型WLCSP封裝結構之單一銲球的剖面圖。
第2圖顯示本發明一實施例之WLCSP封裝結構的剖面圖。
第3A－3E圖顯示本發明另一實施例之WLCSP封裝結構的一系列製程剖面圖。
第4A－4E圖顯示本發明又一實施例之於半導體晶圓上形成WLCSP封裝結構的一系列製程剖面圖。
第5A－5F圖顯示本發明再一實施例之於半導體晶圓上形成WLCSP封裝結構的一系列製程剖面圖。
第6圖顯示本發明一實施例之製程流程圖。
第7圖顯示本發明另一實施例之製程流程圖。
第8圖顯示本發明又一實施例之製程流程圖。
20．．．WLCSP封裝結構
204．．．銲球
200．．．晶圓
201．．．柱電極
202．．．絕緣層
203．．．覆蓋層
205．．．IMC層

Claims (19)

  1. 一種半導體元件的製造方法，包括：在一半導體基底之第一表面形成至少一柱電極，其中每一柱電極包括一兩個以上柱狀物之陣列，該柱電極電性連接至該半導體基底之線路層；沉積一緩衝層於該第一表面上，該緩衝層密封該陣列；移除部份的該緩衝層，而使該柱電極之上表面低於殘餘之該緩衝層之上表面；沉積一導電覆蓋層於該柱電極之上表面上，其中該導電覆蓋層低於殘餘之該緩衝層之上表面；以及放置一銲球於該導電覆蓋層上，其中該銲球與該導電覆蓋層之間的焊接點低於殘餘之該緩衝層之上表面，且該銲球係設置於該至少一柱電極之間的一區域之外。
  2. 如申請專利範圍第1項所述之半導體元件的製造方法，更包括沉積至少一重分佈層於該半導體基底之該第一表面上，其中該重分佈層提供該柱電極與該線路層之間的電性連接。
  3. 如申請專利範圍第1項所述之半導體元件的製造方法，其中該半導體基底包括：一保護層，沉積於一半導體基底層上，其中該保護層之上表面包括該第一表面；以及一電路層，位於該半導體基底層之主動區中，其中該電路層電性連接至該線路層。
  4. 如申請專利範圍第3項所述之半導體元件的製造方法，其中該半導體基底更包括一高分子絕緣層，沉積於該保護層上，其中該高分子絕緣層之上側成為該半導體基底之該第一表面。
  5. 如申請專利範圍第4項所述之半導體元件的製造方法，其中該高分子絕緣層之材質的選擇是根據該材質之熱膨脹係數。
  6. 如申請專利範圍第4項所述之半導體元件的製造方法，其中該高分子絕緣層之材質包括環氧樹脂、聚亞醯胺、或前述之組合。
  7. 如申請專利範圍第1項所述之半導體元件的製造方法，其中該移除步驟包括移除部份的該緩衝層及部分的該柱電極，其中部分的該柱電極之移除包括蝕刻該柱電極以及研磨該柱電極。
  8. 如申請專利範圍第1項所述之半導體元件的製造方法，其中該移除步驟不使用一光阻層。
  9. 如申請專利範圍第1項所述之半導體元件的製造方法，其中該導電覆蓋層之沉積包括透過無電電鍍。
  10. 如申請專利範圍第1項所述之半導體元件的製造方法，其中該導電覆蓋層之材質包括鎳、錫、或前述之組合。
  11. 一種半導體元件的製造方法，包括：形成複數個電極於一半導體基底之第一表面上，其中該些電極凸出該第一表面； 將一材料鍍至該些電極上；沉積一緩衝層於該第一表面上，該些電極延伸穿過該緩衝層；選擇性蝕刻該緩衝層以使該些電極之上表面低於殘餘之該緩衝層之上表面；以及放置一銲球於每一電極上，其中該銲球與該些電極之間的接點低於該緩衝層之該上表面，及其中該銲球透過該材料及該些電極電性連接至該半導體基底之線路層，且該銲球係設置於該些電極之間的一區域之外。
  12. 如申請專利範圍第11項所述之半導體元件的製造方法，更包括沉積至少一重分佈層於該半導體基底之該第一表面上，其中該重分佈層提供該些電極與該線路層之間的電性連接。
  13. 如申請專利範圍第11項所述之半導體元件的製造方法，其中該半導體基底包括：一保護層，沉積於一半導體基底層上，其中該保護層之上表面包括該第一表面；以及一電路層，位於該半導體基底層之主動區中，其中該電路層電性連接至該線路層。
  14. 如申請專利範圍第13項所述之半導體元件的製造方法，其中該半導體基底更包括一高分子絕緣層，沉積於該保護層上，其中該高分子絕緣層之上側成為該半導體基底之該第一表面。
  15. 如申請專利範圍第14項所述之半導體元件的製 造方法，其中該高分子絕緣層之材質包括環氧樹脂、聚亞醯胺、或前述之組合。
  16. 如申請專利範圍第11項所述之半導體元件的製造方法，其中該選擇性蝕刻步驟不使用一光阻層。
  17. 如申請專利範圍第11項所述之半導體元件的製造方法，其中該些電極之形成包括形成一兩個以上柱狀物之陣列於該些電極上，並連接至該導線層之第一端。
  18. 如申請專利範圍第11項所述之半導體元件的製造方法，其中該材料包括銅、鎳、錫、或前述之組合。
  19. 如申請專利範圍第11項所述之半導體元件的製造方法，其中該些電極之材質包括銅、銲錫、鎳、錫、或前述之組合。
TW97108282A 2007-11-16 2008-03-10 半導體元件的製造方法 TWI453840B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/941,429 US8492263B2 (en) 2007-11-16 2007-11-16 Protected solder ball joints in wafer level chip-scale packaging

Publications (2)

Publication Number Publication Date
TW200924090A TW200924090A (en) 2009-06-01
TWI453840B true TWI453840B (zh) 2014-09-21

Family

ID=40642416

Family Applications (1)

Application Number Title Priority Date Filing Date
TW97108282A TWI453840B (zh) 2007-11-16 2008-03-10 半導體元件的製造方法

Country Status (3)

Country Link
US (2) US8492263B2 (zh)
CN (1) CN101436559A (zh)
TW (1) TWI453840B (zh)

Families Citing this family (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7820543B2 (en) * 2007-05-29 2010-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced copper posts for wafer level chip scale packaging
US8492263B2 (en) 2007-11-16 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Protected solder ball joints in wafer level chip-scale packaging
US8183095B2 (en) 2010-03-12 2012-05-22 Stats Chippac, Ltd. Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation
US8456002B2 (en) 2007-12-14 2013-06-04 Stats Chippac Ltd. Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief
US9318441B2 (en) 2007-12-14 2016-04-19 Stats Chippac, Ltd. Semiconductor device and method of forming sacrificial adhesive over contact pads of semiconductor die
JP2009164442A (ja) * 2008-01-09 2009-07-23 Nec Electronics Corp 半導体装置
US9524945B2 (en) * 2010-05-18 2016-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with L-shaped non-metal sidewall protection structure
US8841766B2 (en) 2009-07-30 2014-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US8377816B2 (en) 2009-07-30 2013-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming electrical connections
US8324738B2 (en) 2009-09-01 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned protection layer for copper post structure
US8847387B2 (en) * 2009-10-29 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Robust joint structure for flip-chip bonding
US9607936B2 (en) * 2009-10-29 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Copper bump joint structures with improved crack resistance
US8659155B2 (en) * 2009-11-05 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps
US8299616B2 (en) * 2010-01-29 2012-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. T-shaped post for semiconductor devices
US8610270B2 (en) 2010-02-09 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and semiconductor assembly with lead-free solder
US8803319B2 (en) 2010-02-11 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar structure having a non-planar surface for semiconductor devices
US8318596B2 (en) 2010-02-11 2012-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar structure having a non-planar surface for semiconductor devices
US8264089B2 (en) 2010-03-17 2012-09-11 Maxim Integrated Products, Inc. Enhanced WLP for superior temp cycling, drop test and high current applications
US8441124B2 (en) 2010-04-29 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
FR2959868A1 (fr) * 2010-05-06 2011-11-11 St Microelectronics Crolles 2 Dispositif semi-conducteur a plots de connexion munis d'inserts
KR101119839B1 (ko) * 2010-05-23 2012-02-28 주식회사 네패스 범프 구조물 및 그 제조 방법
US9018758B2 (en) 2010-06-02 2015-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall spacer and metal top cap
US8241963B2 (en) 2010-07-13 2012-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Recessed pillar structure
US9048135B2 (en) * 2010-07-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Copper pillar bump with cobalt-containing sidewall protection
US8546254B2 (en) 2010-08-19 2013-10-01 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps using patterned anodes
CN102455373B (zh) * 2010-10-19 2014-04-23 群成科技股份有限公司 探针卡结构
JP5559023B2 (ja) * 2010-12-15 2014-07-23 日本特殊陶業株式会社 配線基板及びその製造方法
FR2970118B1 (fr) * 2010-12-30 2013-12-13 St Microelectronics Crolles 2 Puce de circuits integres et procede de fabrication.
FR2970119B1 (fr) 2010-12-30 2013-12-13 St Microelectronics Crolles 2 Sas Puce de circuits integres et procede de fabrication.
US9324659B2 (en) * 2011-08-01 2016-04-26 Stats Chippac, Ltd. Semiconductor device and method of forming POP with stacked semiconductor die and bumps formed directly on the lower die
US9368398B2 (en) 2012-01-12 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method of fabricating same
US9257333B2 (en) 2013-03-11 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming same
US9401308B2 (en) 2013-03-12 2016-07-26 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices, methods of manufacture thereof, and packaging methods
US9607921B2 (en) * 2012-01-12 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package interconnect structure
US9589862B2 (en) 2013-03-11 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming same
US9437564B2 (en) 2013-07-09 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method of fabricating same
US10015888B2 (en) 2013-02-15 2018-07-03 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect joint protective layer apparatus and method
US9263839B2 (en) 2012-12-28 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for an improved fine pitch joint
US9230932B2 (en) 2012-02-09 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect crack arrestor structure and methods
US8766441B2 (en) * 2012-03-14 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for solder on slot connections in package on package structures
US9289841B2 (en) * 2012-04-16 2016-03-22 Tanigurogumi Corporation Soldering device, soldering method, and substrate and electronic component produced by the soldering device or the soldering method
US9515036B2 (en) 2012-04-20 2016-12-06 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for solder connections
US9082776B2 (en) 2012-08-24 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having protective layer with curved surface and method of manufacturing same
US9589815B2 (en) * 2012-11-08 2017-03-07 Nantong Fujitsu Microelectronics Co., Ltd. Semiconductor IC packaging methods and structures
US9620468B2 (en) * 2012-11-08 2017-04-11 Tongfu Microelectronics Co., Ltd. Semiconductor packaging structure and method for forming the same
WO2014071814A1 (zh) * 2012-11-08 2014-05-15 南通富士通微电子股份有限公司 芯片封装结构和封装方法
WO2014071815A1 (zh) 2012-11-08 2014-05-15 南通富士通微电子股份有限公司 半导体器件及其形成方法
CN102931097B (zh) * 2012-11-08 2016-11-23 南通富士通微电子股份有限公司 半导体封装结构的形成方法
CN102931158B (zh) * 2012-11-08 2015-12-09 南通富士通微电子股份有限公司 芯片封装结构
CN102915986B (zh) 2012-11-08 2015-04-01 南通富士通微电子股份有限公司 芯片封装结构
US9379077B2 (en) 2012-11-08 2016-06-28 Nantong Fujitsu Microelectronics Co., Ltd. Metal contact for semiconductor device
US9806047B2 (en) * 2014-03-31 2017-10-31 Maxim Integrated Products, Inc. Wafer level device and method with cantilever pillar structure
US9520370B2 (en) 2014-05-20 2016-12-13 Micron Technology, Inc. Methods of forming semiconductor device assemblies and interconnect structures, and related semiconductor device assemblies and interconnect structures
US9412686B2 (en) * 2014-08-26 2016-08-09 United Microelectronics Corp. Interposer structure and manufacturing method thereof
CN104979318A (zh) * 2015-05-19 2015-10-14 南通富士通微电子股份有限公司 晶圆级芯片封装结构及其封装方法
US9892962B2 (en) 2015-11-30 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale package interconnects and methods of manufacture thereof
US9640497B1 (en) * 2016-06-30 2017-05-02 Semiconductor Components Industries, Llc Semiconductor backmetal (BM) and over pad metallization (OPM) structures and related methods
US10068865B1 (en) * 2017-05-10 2018-09-04 Nanya Technology Corporation Combing bump structure and manufacturing method thereof
DE102017210654B4 (de) * 2017-06-23 2022-06-09 Infineon Technologies Ag Elektronische Vorrichtung, die ein einen Hohlraum umfassendes Umverdrahtungsschicht-Pad umfasst
US10699948B2 (en) * 2017-11-13 2020-06-30 Analog Devices Global Unlimited Company Plated metallization structures
US10297561B1 (en) 2017-12-22 2019-05-21 Micron Technology, Inc. Interconnect structures for preventing solder bridging, and associated systems and methods
KR20210016119A (ko) * 2019-07-31 2021-02-15 삼성전자주식회사 반도체 패키지
KR20210084736A (ko) * 2019-12-27 2021-07-08 삼성전자주식회사 반도체 패키지
US20220231067A1 (en) * 2021-01-18 2022-07-21 Taiwan Semiconductor Manufacturing Co., Ltd. Stilted pad structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200522236A (en) * 2003-10-15 2005-07-01 Casio Computer Co Ltd Semiconductor device manufacturing method cross-reference to related applications
US20060113681A1 (en) * 2003-01-10 2006-06-01 Jeong Se-Young Reinforced solder bump structure and method for forming a reinforced solder bump

Family Cites Families (93)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4811082A (en) 1986-11-12 1989-03-07 International Business Machines Corporation High performance integrated circuit packaging structure
US5075253A (en) 1989-04-12 1991-12-24 Advanced Micro Devices, Inc. Method of coplanar integration of semiconductor IC devices
US4990462A (en) 1989-04-12 1991-02-05 Advanced Micro Devices, Inc. Method for coplanar integration of semiconductor ic devices
US5380681A (en) 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
US5466635A (en) 1994-06-02 1995-11-14 Lsi Logic Corporation Process for making an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating
JPH0997791A (ja) 1995-09-27 1997-04-08 Internatl Business Mach Corp <Ibm> バンプ構造、バンプの形成方法、実装接続体
US6002177A (en) 1995-12-27 1999-12-14 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
US5736456A (en) 1996-03-07 1998-04-07 Micron Technology, Inc. Method of forming conductive bumps on die for flip chip applications
US5759910A (en) 1996-12-23 1998-06-02 Motorola, Inc. Process for fabricating a solder bump for a flip chip integrated circuit
US5962921A (en) 1997-03-31 1999-10-05 Micron Technology, Inc. Interconnect having recessed contact members with penetrating blades for testing semiconductor dice and packages with contact bumps
US6175161B1 (en) 1998-05-22 2001-01-16 Alpine Microsystems, Inc. System and method for packaging integrated circuits
US6107180A (en) 1998-01-30 2000-08-22 Motorola, Inc. Method for forming interconnect bumps on a semiconductor die
US6213376B1 (en) 1998-06-17 2001-04-10 International Business Machines Corp. Stacked chip process carrier
JP3516592B2 (ja) 1998-08-18 2004-04-05 沖電気工業株式会社 半導体装置およびその製造方法
US6281042B1 (en) 1998-08-31 2001-08-28 Micron Technology, Inc. Structure and method for a high performance electronic packaging assembly
US6271059B1 (en) 1999-01-04 2001-08-07 International Business Machines Corporation Chip interconnection structure using stub terminals
US6461895B1 (en) 1999-01-05 2002-10-08 Intel Corporation Process for making active interposer for high performance packaging applications
US6229216B1 (en) 1999-01-11 2001-05-08 Intel Corporation Silicon interposer and multi-chip-module (MCM) with through substrate vias
TW442873B (en) * 1999-01-14 2001-06-23 United Microelectronics Corp Three-dimension stack-type chip structure and its manufacturing method
JP3346320B2 (ja) 1999-02-03 2002-11-18 カシオ計算機株式会社 半導体装置及びその製造方法
US6243272B1 (en) 1999-06-18 2001-06-05 Intel Corporation Method and apparatus for interconnecting multiple devices on a circuit board
JP3239335B2 (ja) 1999-08-18 2001-12-17 インターナショナル・ビジネス・マシーンズ・コーポレーション 電気的接続用構造体の形成方法およびはんだ転写用基板
GB0005088D0 (en) 2000-03-01 2000-04-26 Unilever Plc Composition and method for bleaching laundry fabrics
US6717245B1 (en) 2000-06-02 2004-04-06 Micron Technology, Inc. Chip scale packages performed by wafer level processing
US6355501B1 (en) 2000-09-21 2002-03-12 International Business Machines Corporation Three-dimensional chip stacking assembly
US7129575B1 (en) 2000-10-13 2006-10-31 Bridge Semiconductor Corporation Semiconductor chip assembly with bumped metal pillar
US6562665B1 (en) 2000-10-16 2003-05-13 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology
KR100364635B1 (ko) 2001-02-09 2002-12-16 삼성전자 주식회사 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법
JP3767398B2 (ja) 2001-03-19 2006-04-19 カシオ計算機株式会社 半導体装置およびその製造方法
KR100394808B1 (ko) 2001-07-19 2003-08-14 삼성전자주식회사 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법
US20030107137A1 (en) * 2001-09-24 2003-06-12 Stierman Roger J. Micromechanical device contact terminals free of particle generation
KR100435813B1 (ko) 2001-12-06 2004-06-12 삼성전자주식회사 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법
DE10200399B4 (de) 2002-01-08 2008-03-27 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Erzeugung einer dreidimensional integrierten Halbleitervorrichtung und dreidimensional integrierte Halbleitervorrichtung
US6756294B1 (en) 2002-01-30 2004-06-29 Taiwan Semiconductor Manufacturing Company Method for improving bump reliability for flip chip devices
US6887769B2 (en) 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6975016B2 (en) 2002-02-06 2005-12-13 Intel Corporation Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof
US6661085B2 (en) 2002-02-06 2003-12-09 Intel Corporation Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
DE50308874D1 (de) * 2002-03-28 2008-02-07 Infineon Technologies Ag Method for producing a semiconductor wafer
US6803303B1 (en) 2002-07-11 2004-10-12 Micron Technology, Inc. Method of fabricating semiconductor component having encapsulated, bonded, interconnect contacts
US6600222B1 (en) 2002-07-17 2003-07-29 Intel Corporation Stacked microelectronic packages
US6987031B2 (en) * 2002-08-27 2006-01-17 Micron Technology, Inc. Multiple chip semiconductor package and method of fabricating same
US7285867B2 (en) 2002-11-08 2007-10-23 Casio Computer Co., Ltd. Wiring structure on semiconductor substrate and method of fabricating the same
US6790748B2 (en) 2002-12-19 2004-09-14 Intel Corporation Thinning techniques for wafer-to-wafer vertical stacks
US6908565B2 (en) 2002-12-24 2005-06-21 Intel Corporation Etch thinning techniques for wafer-to-wafer vertical stacks
US6924551B2 (en) 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US6946384B2 (en) 2003-06-06 2005-09-20 Intel Corporation Stacked device underfill and a method of fabrication
US7320928B2 (en) 2003-06-20 2008-01-22 Intel Corporation Method of forming a stacked device filler
US20050026416A1 (en) 2003-07-31 2005-02-03 International Business Machines Corporation Encapsulated pin structure for improved reliability of wafer
KR100537892B1 (ko) 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
US7345350B2 (en) 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
KR100621992B1 (ko) 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
JP3929966B2 (ja) 2003-11-25 2007-06-13 新光電気工業株式会社 半導体装置及びその製造方法
KR100570514B1 (ko) 2004-06-18 2006-04-13 삼성전자주식회사 웨이퍼 레벨 칩 스택 패키지 제조 방법
KR100618837B1 (ko) 2004-06-22 2006-09-01 삼성전자주식회사 웨이퍼 레벨 패키지를 위한 얇은 웨이퍼들의 스택을형성하는 방법
US7307005B2 (en) 2004-06-30 2007-12-11 Intel Corporation Wafer bonding with highly compliant plate having filler material enclosed hollow core
US7452803B2 (en) 2004-08-12 2008-11-18 Megica Corporation Method for fabricating chip structure
US7087538B2 (en) 2004-08-16 2006-08-08 Intel Corporation Method to fill the gap between coupled wafers
US20060055032A1 (en) 2004-09-14 2006-03-16 Kuo-Chin Chang Packaging with metal studs formed on solder pads
TWI252546B (en) * 2004-11-03 2006-04-01 Advanced Semiconductor Eng Bumping process and structure thereof
JP4843214B2 (ja) * 2004-11-16 2011-12-21 株式会社東芝 モジュール基板およびディスク装置
TWI263856B (en) 2004-11-22 2006-10-11 Au Optronics Corp IC chip, IC assembly and flat display
JP2006228837A (ja) * 2005-02-15 2006-08-31 Sharp Corp 半導体装置及びその製造方法
JP4526983B2 (ja) * 2005-03-15 2010-08-18 新光電気工業株式会社 配線基板の製造方法
US20060211233A1 (en) * 2005-03-21 2006-09-21 Skyworks Solutions, Inc. Method for fabricating a wafer level package having through wafer vias for external package connectivity and related structure
JP2006287048A (ja) 2005-04-01 2006-10-19 Rohm Co Ltd 半導体装置
US7317256B2 (en) 2005-06-01 2008-01-08 Intel Corporation Electronic packaging including die with through silicon via
US7557597B2 (en) 2005-06-03 2009-07-07 International Business Machines Corporation Stacked chip security
US7402515B2 (en) 2005-06-28 2008-07-22 Intel Corporation Method of forming through-silicon vias with stress buffer collars and resulting devices
JP4889974B2 (ja) * 2005-08-01 2012-03-07 新光電気工業株式会社 電子部品実装構造体及びその製造方法
TWI273667B (en) 2005-08-30 2007-02-11 Via Tech Inc Chip package and bump connecting structure thereof
US7432592B2 (en) 2005-10-13 2008-10-07 Intel Corporation Integrated micro-channels for 3D through silicon architectures
US7528494B2 (en) 2005-11-03 2009-05-05 International Business Machines Corporation Accessible chip stack and process of manufacturing thereof
US7410884B2 (en) 2005-11-21 2008-08-12 Intel Corporation 3D integrated circuits using thick metal for backside connections and offset bumps
KR100660893B1 (ko) 2005-11-22 2006-12-26 삼성전자주식회사 정렬 마크막을 구비하는 반도체 소자 및 그 제조 방법
JP4458029B2 (ja) * 2005-11-30 2010-04-28 カシオ計算機株式会社 半導体装置の製造方法
JP4251458B2 (ja) 2005-12-21 2009-04-08 Ｔｄｋ株式会社 チップ部品の実装方法及び回路基板
US7402442B2 (en) 2005-12-21 2008-07-22 International Business Machines Corporation Physically highly secure multi-chip assembly
US7279795B2 (en) 2005-12-29 2007-10-09 Intel Corporation Stacked die semiconductor package
TW200820406A (en) 2006-10-19 2008-05-01 Novatek Microelectronics Corp Chip structure and wafer structure
JP4922891B2 (ja) 2006-11-08 2012-04-25 株式会社テラミクロス 半導体装置およびその製造方法
US20090197114A1 (en) 2007-01-30 2009-08-06 Da-Yuan Shih Modification of pb-free solder alloy compositions to improve interlayer dielectric delamination in silicon devices and electromigration resistance in solder joints
US7576435B2 (en) 2007-04-27 2009-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Low-cost and ultra-fine integrated circuit packaging technique
US7820543B2 (en) 2007-05-29 2010-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced copper posts for wafer level chip scale packaging
US20090020869A1 (en) 2007-07-17 2009-01-22 Qing Xue Interconnect joint
KR101213175B1 (ko) 2007-08-20 2012-12-18 삼성전자주식회사 로직 칩에 층층이 쌓인 메모리장치들을 구비하는반도체패키지
US8269345B2 (en) 2007-10-11 2012-09-18 Maxim Integrated Products, Inc. Bump I/O contact for semiconductor device
US8492263B2 (en) 2007-11-16 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Protected solder ball joints in wafer level chip-scale packaging
US8299616B2 (en) 2010-01-29 2012-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. T-shaped post for semiconductor devices
US8803319B2 (en) 2010-02-11 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar structure having a non-planar surface for semiconductor devices
US8318596B2 (en) 2010-02-11 2012-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar structure having a non-planar surface for semiconductor devices
US20110227216A1 (en) 2010-03-16 2011-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Under-Bump Metallization Structure for Semiconductor Devices
US8241963B2 (en) 2010-07-13 2012-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Recessed pillar structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060113681A1 (en) * 2003-01-10 2006-06-01 Jeong Se-Young Reinforced solder bump structure and method for forming a reinforced solder bump
TW200522236A (en) * 2003-10-15 2005-07-01 Casio Computer Co Ltd Semiconductor device manufacturing method cross-reference to related applications

Also Published As

Publication number Publication date
US20130299984A1 (en) 2013-11-14
US9136211B2 (en) 2015-09-15
US8492263B2 (en) 2013-07-23
TW200924090A (en) 2009-06-01
US20090130840A1 (en) 2009-05-21
CN101436559A (zh) 2009-05-20

Similar Documents

Publication Publication Date Title
TWI453840B (zh) 半導體元件的製造方法
US7932601B2 (en) Enhanced copper posts for wafer level chip scale packaging
TWI483357B (zh) 封裝結構
JP4850392B2 (ja) 半導体装置の製造方法
US7125745B2 (en) Multi-chip package substrate for flip-chip and wire bonding
US20070254406A1 (en) Method for manufacturing stacked package structure
US20070200251A1 (en) Method of fabricating ultra thin flip-chip package
CN1326225A (zh) 芯片倒装型半导体器件及其制造方法
TW200917441A (en) Inter-connecting structure for semiconductor package and method of the same
KR100723497B1 (ko) 솔더볼 랜드에 두 종류 이상의 표면처리부를 갖는인쇄회로기판 및 이를 포함하는 반도체 패키지
US8431478B2 (en) Solder cap bump in semiconductor package and method of manufacturing the same
US6841884B2 (en) Semiconductor device
US20090096093A1 (en) Inter-connecting structure for semiconductor package and method of the same
US7575994B2 (en) Semiconductor device and manufacturing method of the same
TWI574364B (zh) 封裝體及其製作方法
JP2010161419A (ja) 半導体装置の製造方法
KR101211724B1 (ko) 반도체 패키지 및 그 제조방법
US9024439B2 (en) Substrates having bumps with holes, semiconductor chips having bumps with holes, semiconductor packages formed using the same, and methods of fabricating the same
KR20080045017A (ko) 금속 범프를 갖는 반도체 칩 패키지 및 그 제조방법
KR100761863B1 (ko) 솔더볼 랜드에 두 종류 이상의 표면처리부를 갖는인쇄회로기판 및 이를 포함하는 반도체 패키지
US20100102457A1 (en) Hybrid Semiconductor Chip Package
JP2004228200A (ja) 半導体装置およびその製造方法
JP2009135529A (ja) 半導体装置
JP2004179292A (ja) 半導体装置、半導体装置実装体、及びこれらの製造方法
JP2008160142A (ja) 半導体装置及びその製造方法