TWI453840B - 半導體元件的製造方法 - Google Patents

半導體元件的製造方法 Download PDF

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Publication number
TWI453840B
TWI453840B TW97108282A TW97108282A TWI453840B TW I453840 B TWI453840 B TW I453840B TW 97108282 A TW97108282 A TW 97108282A TW 97108282 A TW97108282 A TW 97108282A TW I453840 B TWI453840 B TW I453840B
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Taiwan
Prior art keywords
layer
semiconductor device
semiconductor substrate
electrodes
electrode
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TW97108282A
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English (en)
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TW200924090A (en
Inventor
Chung Yu Wang
Chien Hsiun Lee
Pei Haw Tsao
Kuo Chin Chang
Chung Yi Lin
Bill Kiang
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Taiwan Semiconductor Mfg
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Publication of TW200924090A publication Critical patent/TW200924090A/zh
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Publication of TWI453840B publication Critical patent/TWI453840B/zh

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Description

半導體元件的製造方法
本發明係有關於晶圓級晶片尺寸封裝(wafer level chip－scale packaging,WLCSP)，且特別是關於增進WLCSP中之銲球接點(solder ball joints)的可靠度。
在過去幾十年來，電子與半導體封裝技術之進步已衝擊整個半導體工業。導入表面接合技術(surface－mount technology,SMT)與球柵陣列(ball grid array,BGA)封裝對於多種積體電路元件的高產率封裝通常是重要的步驟，且還同時允許印刷電路板上之接墊間距縮小。通常積體電路之封裝結構基本上由晶片上的金屬接墊與散佈自封裝體的電極間之細金線來形成內連線。雙列式封裝(dual inline package,DIP)與四方扁平封裝(quad flat package,QFP)是目前積體電路封裝的基本結構。然而，隨著週邊設計與排列於封裝體之針腳數目(pin count)的增加，使導線間之間距過小而限制電路板之晶片封裝。
晶片尺寸封裝(CSP)及球柵陣列(BGA)封裝為在不大幅增加封裝尺寸情況下，使電極之排列緊密的一種解決方案。CSP提供晶片尺寸之晶圓封裝。CSP之封裝結構一般小於1.2倍的晶粒尺寸，大幅縮小以CSP封裝之元件的尺寸。雖然，這些優點已使電子元件小型化，但一直以來對於更小、更輕、及更薄電子產品之需求，更加小型化封裝結構的追求仍未曾間斷。
為了滿足市場對於更小型化與更多功能化電子產品之需求，近年來導入了晶圓級晶片尺寸封裝(WLCSP)以增加元件密度、增進效能、與節省成本，並同時減小電子封裝工業中之元件的重量與尺寸。在WLCSP封裝中，封裝體通常直接形成於晶粒上，晶粒具有由球柵陣列及凸塊電極(bump electrodes)所提供之接點(contact)。近來之先進電子元件，例如行動電話、筆記型電腦、攝影機、個人數位助理(PDAs)等，利用了密集且輕薄之緊密封裝積體電路。使用WLCSP以較少數目的接腳來封裝較小晶粒尺寸之元件，可於一晶圓上形成更多之晶片，具有更高的成本效益。
現今的WLCSP技術之一缺點是銲球與柱電極(electrode post)間會形成裂痕(cracks)。銲球或凸塊一般直接放置於凸塊電極或柱電極上，靠焊接點(solder joint)來維持結構整體性。形成WLCSP元件之不同材料層之間一般具有不同的熱膨脹係數(CTE)。因此，由不同熱膨脹係數所引起之較大應力會發生在與柱電極及凸塊電極之間的接點，常常在凸塊電極/柱電極與銲球或凸塊間之接合區造成裂縫。此外，銲球一般位於晶圓的材料層上方。銲球接合處之露出使銲球更容易受到物理衝擊的影響，並亦使較脆弱之接點露出。
第1圖顯示典型WLCSP封裝結構10之單一銲球的剖面圖。WLCSP封裝結構直接形成於晶粒100上。在晶粒100上形成有銅墊102。銅墊102作為銲球101之接觸點與接墊。在焊接製程期間，金屬間化合物(intermetallic compounds,IMC)會於銲球101與銅墊102之間的接點自然地形成為一材料層(例如IMC形成層103)。雖然IMC形成層103之存在通常意味著銲料與基底間有良好的焊接，但IMC形成層103通常是焊接點之最脆弱部分。因為在WLCPS封裝中之焊接點非常小，使得裂痕(crack)(例如裂痕104)在應力施加於接點時可能更容易形成，且這樣的裂痕由於整體封裝結構尺寸較小，可能對結構傷害更大。再者，IMC形成層103位於晶粒100之上表面上，因此會將此較脆弱區域曝露於較大的直接應力衝擊。沿著銲球101之一側生成之小裂痕(例如裂痕104)可容易地沿著焊接點橫截面方向傳播而變大。
美國專利US 6,600,234(Kuwabara,et al.)揭露一種可減小上述應力裂痕的方法。此方法係使用多層材料層來形成密封膜(sealing film)，其中部分的凸塊電極自密封膜突出。突出的電極輔助吸收部份由熱膨脹係數不同所造成之應力。密封層之多層材料層之選擇亦可具有逐漸改變的熱膨脹係數，使接近基底之材料層具有與基底相近的熱膨脹係數，而接近電路基底之材料層具有與電路基底相近的熱膨脹係數。此逐漸改變的熱膨脹係數有助於緩和由急遽熱膨脹係數差異所造成之應力。然而，密封層之多層材料層通常仍呈現較低的剪切強度(shear strength)，且無法減輕可能形成於IMC形成層中之裂縫的傳播，因而減低接點的整體可靠度。
美國專利US 6,717,245(Kinsman,et al.)另提出一種增進晶片尺寸封裝的方法。此方法以環氧樹脂(epoxy)或其他相似材料完全封裝第一凸塊層(bumped layer)。接著研磨封裝層以露出包裝於其中之凸塊的頂部。接著將一般的銲球印刷或放置於第一凸塊層之露出部分上。藉著透過第一凸塊層之封裝層而將銲球與電路板隔離，可減小熱膨脹所造成之應力。然而，銲球接點仍容易沿著IMC形成層生成裂縫，因而減低接點的整體可靠度。
美國專利US 6,906,418(Hiatt,et al.)另提出一種增進晶片尺寸封裝的方法。此方法提供兩種不同的CSP封裝實施例。第一實施例將來自晶粒接墊之內連線接點(interconnect contact)的尖端部份(tip)延伸穿過絕緣層。在沉積金屬化材料層於內連線接點的尖端部份後，將銲球放置於每一延伸尖端部份上。金屬化材料層之材質係選用能增進金屬化材料層與銲球間之接合的材料。然而，因為銲球接點位於或高於絕緣層表面，銲球接點仍有不小的剪切應力。第二實施例提供之銲球係直接放置於晶粒接墊上或重分佈層上。接著使用絕緣層將銲球封裝，並留下部分露出區以用於接觸。雖然此實施例增進銲球接點之強度，但將銲球直接放置於晶粒接墊上需複雜的設計程序，會大幅增加CSP封裝的成本。此外，內連線接點的結構亦會受限於晶粒接墊之結構。
本發明提供一種半導體元件的製造方法，包括在半導體基底之第一表面形成至少一柱電極，其中每一柱電極包括兩個以上柱狀物之陣列，柱電極電性連接至半導體基底之線路層，沉積緩衝層於第一表面上，緩衝層密封陣列，移除部份的緩衝層及部分的柱電極，而使柱電極之上表面低於殘餘之緩衝層之上表面，沉積導電覆蓋層於柱電極之上表面上，其中導電覆蓋層低於殘餘之緩衝層之上表面，以及放置銲球於導電覆蓋層上，其中銲球與導電覆蓋層之間的焊接點低於殘餘之緩衝層之上表面。
本發明另提供一種半導體元件的製造方法，包括形成複數個電極於半導體基底之第一表面上，其中電極凸出第一表面，將一材料鍍至電極上；沉積緩衝層於第一表面上，電極延伸穿過緩衝層，選擇性蝕刻緩衝層以使電極之上表面低於殘餘之緩衝層之上表面，以及放置銲球於每一電極上，其中銲球與電極之間的接點低於緩衝層之上表面，及其中銲球透過材料及電極電性連接至半導體基底之線路層。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
第2圖顯示本發明一實施例之WLCSP封裝結構20的剖面圖。晶圓200包括形成於其上之柱電極201。絕緣層202形成於晶圓200之頂部上，且圍繞柱電極201。在製造過程期間，柱電極201之頂部與絕緣層202之頂部同高。接著將柱電極201回蝕刻而使低於絕緣層202之頂部。在較佳實施例中，因為絕緣層202之材質是特別選定，使柱電極201之回蝕刻不會對絕緣層202造成影響，所以不需使用額外的光阻層來進行蝕刻。
沉積覆蓋層203於柱電極201上，覆蓋層203保護柱電極201免於氧化。在一較佳實施例中，柱電極201之材質是銅。因此覆蓋層203可保護銅柱電極201免於氧化。可以各種不同的方法沉積覆蓋層203，包括無電電鍍法(electroless plating)或其相似方法。接著將銲球204焊接、連接、或印刷至晶圓200上。焊接後形成接點(joint)於覆蓋層203的頂部，且接點低於絕緣層202。因此，銲球204部分低於絕緣層202，且部分高於絕緣層202(另一部分)。再者，IMC層205(金屬間化合物層)形成於銲球204與覆蓋層203間之接合處，因此IMC層205受到絕緣層202之保護而免於受到直接物理接觸。藉著配置晶圓200使銲球204部分高於絕緣層202，並部分低於絕緣層202，且使焊接點低於絕緣層202之上表面，以及利用覆蓋層205保護柱電極201免於受到氧化，此結構之焊接點會更可靠且具有較強的剪切與一般強度。
第3A圖顯示本發明一實施例之WLCSP封裝結構30之前段製程步驟剖面圖。晶粒300包括保護層302與高分子絕緣層303。位於晶粒300頂部之線路層301連接至晶粒300中之電路層(未顯示)。沉積重分佈層304於晶粒300之高分子絕緣層303之頂部上。重分佈層304將電性連接延伸至線路層301。
應注意的是高分子絕緣層303可包括多種絕緣材料，例如聚亞醯胺(polyimide)或其他相似的高分子絕緣材料。第3A－3E圖所提供之敘述並非意圖將本發明限定之絕緣層限定為任何特定材料。事實上，在其他實施例中，WLCSP封裝結構可不包括絕緣層(例如高分子絕緣層303)。
請參照第3B圖，沉積柱電極305於晶粒300上。柱電極305可與重分佈層304直接物理接觸而形成與線路層301之間的電性連接。因此，與柱電極305接觸可形成電性連接至晶粒300中之電路層(未顯示)。重分佈層304之材質可選自多種有益的導電材料，例如銅、金、鋁、錫、任何有益的導電材料之結合或合金、或前述之組合。
第3C圖顯示本發明一實施例之WLCSP封裝結構30之下一製程步驟剖面圖。沉積緩衝層306於晶粒300之頂部上以增加對於晶粒300與柱電極305之保護。在一些實施例中，緩衝層306之選用可部分基於材料之熱膨脹係數，以減少WLCSP封裝結構因不同材料層之不同熱膨脹係數所形成的應力。緩衝層306可例如包括環氧樹脂、聚亞醯胺、或其相似物。本發明較佳實施例之緩衝層306的材質選擇基準可亦考量緩衝層306之材質對於可能用以蝕刻柱電極305之蝕刻劑的耐蝕程度。
第3D圖顯示本發明一實施例之WLCSP封裝結構30之下一製程步驟剖面圖。使用不會影響緩衝層306之蝕刻劑將柱電極305回蝕刻而使低於緩衝層306之頂部。在執行此步驟時，可不使用其他光阻層而將柱電極305回蝕刻。在將柱電極305回蝕刻後，沉積覆蓋層307於柱電極305上而覆蓋柱電極305所露出之表面，但仍使覆蓋層307之頂部低於緩衝層306之頂部。藉著覆蓋柱電極305之露出表面，覆蓋層307保護柱電極305免於氧化。覆蓋層307之材質係選用導電材料，因而仍能維持覆蓋層307與線路層301之間的電性連接。例如，覆蓋層307之材質可為鎳、錫、其他相似材料、前述之合金、或前述之組合。
第3E圖顯示本發明一實施例之WLCSP封裝結構30的剖面圖。在沉積覆蓋層307於每一柱電極(例如柱電極305)後，將銲球308印刷或焊接至柱電極305/覆蓋層307上。因此，形成於銲球308與覆蓋層307間之接點會低於緩衝層306之頂部。因此，緩衝層306可提供焊接點一保護屏障。再者，形成於焊接點之IMC層亦受到緩衝層306之保護。所完成的WLCSP封裝結構30具有更強且更可靠之焊接點。
第4A－4E圖顯示本發明一實施例於半導體晶圓40上形成WLCSP封裝結構的一系列製程剖面圖。半導體晶圓40包括基底400、晶粒接墊401(die contact)、保護層402、絕緣層403、及重分佈層404。藉著重分佈層404之使用，封裝設計與積體電路之佈局可更流暢，這是因為封裝結構之位置不會受限於晶粒接墊(例如晶粒接墊401)之位置。
形成多柱狀物柱電極405(multi－column electrode post)於重分佈層404上以提供電性接觸至晶粒接墊401(如第4B圖所示)。多柱狀物柱電極405可使用形成金屬層之任何方法來形成。例如，可放置光阻層或薄片於半導體晶圓40之頂部，光阻層或薄片上具有凹槽以蝕刻其下之金屬層於而形成多柱狀物柱電極405。或者，可於光阻層或薄片之凹槽中填充導電材料來形成多柱狀物柱電極405。多柱狀物柱電極405之材質包括銅、鎳、鋁、鎢、前述之相似物、前述之合金、或前述之組合。
在顯示於第4A－4E圖中之WLCSP封裝結構之實施例中，每一多柱狀物柱電極405之柱狀物可較佳具有介於約10微米至約20微米之間的外徑，且每一柱狀物之間的間距較佳介於約10微米至約20微米之間。接著沉積封裝材料(例如應力緩衝層)於具有上述較佳尺寸柱狀物之封裝結構上。
第4C圖顯示沉積於半導體晶圓40之頂部上的緩衝層406。緩衝層406將每一多柱狀物柱電極405之柱狀物密封於其中。緩衝層406之密封增強多柱狀物柱電極405之強度。如第4D圖所示，將緩衝層406回蝕刻而露出多柱狀物柱電極405，並於其上沉積低反應層407(low reactive layer)。低反應層407之材質較佳包括能增強與銲球或凸塊間之接合的材料，且亦具有較小IMC缺陷成長速度。低反應層407之材質例如包括鎳、錫、其相似物、或前述之組合。
一旦沉積了低反應層407於多柱狀物柱電極405，可將銲球408印刷或放置於半導體晶圓40上(如第4E圖所示)。低反應層407被放置於緩衝層406之表面下方，因此銲球408與低反應層407間之銲球接點低於緩衝層406之表面。此設計提供一些防護以抵抗產生在銲球408上之剪切應力，又緩衝層406之材質係選用具有特定熱膨脹係數之材料，亦可減低銲球接點上之熱膨脹應力。
第4A－4E圖所敘述之多柱狀物柱電極的實施例較單柱柱電極之實施例有較佳的封裝應力抵抗力。首先，因為與銲球之接點分散在每一柱狀物上，裂痕將無法輕易地沿著整個接點傳播。因為裂痕會沿著破裂線(fracture line)傳播，所以裂痕僅會往單一柱狀物內部傳播，而不再沿著整個接點的橫截面方向傳播。再者，埋在各柱狀物間之應力緩衝層可進一步增強裂縫抵抗力(因為具有金屬柱狀物/緩衝層複合結構)。緩衝層之材料特性(例如有機應力緩衝材料)可增進具有金屬柱狀物/緩衝層複合結構之多柱狀物柱電極結構對於裂縫的抵抗力。
第5A－5E圖顯示本發明一實施例於半導體晶圓50上形成WLCSP封裝結構的一系列製程剖面圖。第5A圖顯示半導體晶圓50，包括積體電路層500、接墊501、金屬電鍍晶種層502、重分佈層503、及光阻層504。凹槽506已藉著蝕刻進入光阻層504而形成，且凹槽506之內壁還覆蓋有電鍍金屬層505。如第5B圖所示，接著形成導電柱507於凹槽506中。形成導電柱507之前可選擇性地移除凹槽506外之電鍍金屬層505。
應注意的是電鍍金屬層505與導電柱507較佳選用不同的導電材料。例如，電鍍金屬層505可包括鎳、錫、銅、其相似物、或前述之組合，而導電柱507可包括銅、銲錫、錫、鎳、其相似物、或前述之組合。當電鍍金屬層505之材質包括鎳時，銲料/銅之IMC層的成長會減低。當電鍍金屬層505之材質包括鎳而導電柱507之材質包括銲錫時，此柱狀結構較使用材質較硬的銅柱狀結構更具韌性。因此，當封裝結構受到熱應力時，柱狀結構可承受較大的變形而可減低銲球接點上的應力程度。
在第5C圖中，將光阻層504移除，且將金屬電鍍晶種層502回蝕刻使與重分佈層503對齊。接著如第5D圖所示，沉積緩衝層508於半導體晶圓50上以封裝各元件，包括電鍍金屬層505及導電柱507。如第5E圖所示，研磨緩衝層508降低其上表面，並進一步蝕刻導電柱507使低於緩衝層508之表面。接著如第5F圖所示，將銲球509印刷或放置於半導體晶圓50上，使銲球接點低於緩衝層508之表面。藉著將銲球接點放置於緩衝層508之表面下，可有效地使銲球接點遠離高應力區域，因此銲球接點會受到較小的剪切應力。
第6圖顯示本發明一實施例之製程流程圖。在步驟600中，形成至少一柱電極於半導體基底之第一表面上，其中每一柱電極由兩個以上柱狀物之陣列形成，且電性連接至半導體基底之線路層。在步驟601中，沉積緩衝層於第一表面上以封裝柱電極之柱狀物陣列。在步驟602中，移除部份柱電極而使柱電極之上表面低於緩衝層之上表面。在步驟603中，沉積導電覆蓋層於露出的多柱狀物柱電極之上表面上，其中導電覆蓋層亦低於緩衝層之上表面。在步驟604中，將銲球放置於每一導電覆蓋層上，其中銲球與導電覆蓋層間之接點低於緩衝層之頂部。
第7圖顯示本發明另一實施例之製程流程圖。在步驟700中，形成複數個電極於半導體基底之第一表面，其中電極突出第一表面。在步驟701中，將電鍍材料電鍍於電極。在步驟702中，沉積緩衝層於第一表面而完全覆蓋電極之延伸。在步驟703中，選擇性蝕刻緩衝層而使電極之上表面露出並低於緩衝層之頂部。在步驟704中，將銲球放置於每一電極上，其中銲球與每一電極間之接點低於緩衝層之頂部，且銲球透過電鍍材料與電極而電性連接至半導體基底之導線層。
第8圖顯示本發明又一實施例之製程流程圖。在步驟800中，形成複數個柱電極於半導體基底之第一表面，其中每一柱電極是由兩個以上之柱狀物陣列所形成。在步驟801中，將一電鍍材料電鍍至多柱狀物柱電極上。在步驟802中，沉積緩衝層於第一表面上，其中多柱狀物柱電極延伸穿過緩衝層。在步驟803中，選擇性蝕刻緩衝層而使多柱狀物柱電極之上表面露出並低於緩衝層之頂部。在步驟804中，將銲球放置於每一多柱狀物柱電極上，其中銲球與每一多柱狀物柱電極間之接點低於緩衝層之頂部，且銲球透過電鍍材料與多柱狀物柱電極而電性連接至半導體基底之線路層。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10、20、30．．．WLCSP封裝結構
100、300．．．晶粒
102．．．銅墊
101、204、308、408、509．．．銲球
103．．．IMC形成層
104．．．裂痕
200．．．晶圓
201、305．．．柱電極
202、403．．．絕緣層
203、307．．．覆蓋層
205．．．IMC層
302、402．．．保護層
303．．．高分子絕緣層
301．．．線路層
304、404、503．．．重分佈層
306、406、508．．．緩衝層
40、50．．．半導體晶圓
400．．．基底
401．．．晶粒接墊
405．．．多柱狀物柱電極
407．．．低反應層
500．．．積體電路層
501．．．接墊
502．．．金屬電鍍晶種層
504．．．光阻層
505．．．電鍍金屬層
507．．．導電柱
600、601、602、603、604、700、701、702、703、704、800、801、802、803、804．．．步驟
第1圖顯示典型WLCSP封裝結構之單一銲球的剖面圖。
第2圖顯示本發明一實施例之WLCSP封裝結構的剖面圖。
第3A－3E圖顯示本發明另一實施例之WLCSP封裝結構的一系列製程剖面圖。
第4A－4E圖顯示本發明又一實施例之於半導體晶圓上形成WLCSP封裝結構的一系列製程剖面圖。
第5A－5F圖顯示本發明再一實施例之於半導體晶圓上形成WLCSP封裝結構的一系列製程剖面圖。
第6圖顯示本發明一實施例之製程流程圖。
第7圖顯示本發明另一實施例之製程流程圖。
第8圖顯示本發明又一實施例之製程流程圖。
20．．．WLCSP封裝結構
204．．．銲球
200．．．晶圓
201．．．柱電極
202．．．絕緣層
203．．．覆蓋層
205．．．IMC層

Claims (19)

  1. 一種半導體元件的製造方法，包括：在一半導體基底之第一表面形成至少一柱電極，其中每一柱電極包括一兩個以上柱狀物之陣列，該柱電極電性連接至該半導體基底之線路層；沉積一緩衝層於該第一表面上，該緩衝層密封該陣列；移除部份的該緩衝層，而使該柱電極之上表面低於殘餘之該緩衝層之上表面；沉積一導電覆蓋層於該柱電極之上表面上，其中該導電覆蓋層低於殘餘之該緩衝層之上表面；以及放置一銲球於該導電覆蓋層上，其中該銲球與該導電覆蓋層之間的焊接點低於殘餘之該緩衝層之上表面，且該銲球係設置於該至少一柱電極之間的一區域之外。
  2. 如申請專利範圍第1項所述之半導體元件的製造方法，更包括沉積至少一重分佈層於該半導體基底之該第一表面上，其中該重分佈層提供該柱電極與該線路層之間的電性連接。
  3. 如申請專利範圍第1項所述之半導體元件的製造方法，其中該半導體基底包括：一保護層，沉積於一半導體基底層上，其中該保護層之上表面包括該第一表面；以及一電路層，位於該半導體基底層之主動區中，其中該電路層電性連接至該線路層。
  4. 如申請專利範圍第3項所述之半導體元件的製造方法，其中該半導體基底更包括一高分子絕緣層，沉積於該保護層上，其中該高分子絕緣層之上側成為該半導體基底之該第一表面。
  5. 如申請專利範圍第4項所述之半導體元件的製造方法，其中該高分子絕緣層之材質的選擇是根據該材質之熱膨脹係數。
  6. 如申請專利範圍第4項所述之半導體元件的製造方法，其中該高分子絕緣層之材質包括環氧樹脂、聚亞醯胺、或前述之組合。
  7. 如申請專利範圍第1項所述之半導體元件的製造方法，其中該移除步驟包括移除部份的該緩衝層及部分的該柱電極，其中部分的該柱電極之移除包括蝕刻該柱電極以及研磨該柱電極。
  8. 如申請專利範圍第1項所述之半導體元件的製造方法，其中該移除步驟不使用一光阻層。
  9. 如申請專利範圍第1項所述之半導體元件的製造方法，其中該導電覆蓋層之沉積包括透過無電電鍍。
  10. 如申請專利範圍第1項所述之半導體元件的製造方法，其中該導電覆蓋層之材質包括鎳、錫、或前述之組合。
  11. 一種半導體元件的製造方法，包括：形成複數個電極於一半導體基底之第一表面上，其中該些電極凸出該第一表面； 將一材料鍍至該些電極上；沉積一緩衝層於該第一表面上，該些電極延伸穿過該緩衝層；選擇性蝕刻該緩衝層以使該些電極之上表面低於殘餘之該緩衝層之上表面；以及放置一銲球於每一電極上，其中該銲球與該些電極之間的接點低於該緩衝層之該上表面，及其中該銲球透過該材料及該些電極電性連接至該半導體基底之線路層，且該銲球係設置於該些電極之間的一區域之外。
  12. 如申請專利範圍第11項所述之半導體元件的製造方法，更包括沉積至少一重分佈層於該半導體基底之該第一表面上，其中該重分佈層提供該些電極與該線路層之間的電性連接。
  13. 如申請專利範圍第11項所述之半導體元件的製造方法，其中該半導體基底包括：一保護層，沉積於一半導體基底層上，其中該保護層之上表面包括該第一表面；以及一電路層，位於該半導體基底層之主動區中，其中該電路層電性連接至該線路層。
  14. 如申請專利範圍第13項所述之半導體元件的製造方法，其中該半導體基底更包括一高分子絕緣層，沉積於該保護層上，其中該高分子絕緣層之上側成為該半導體基底之該第一表面。
  15. 如申請專利範圍第14項所述之半導體元件的製 造方法，其中該高分子絕緣層之材質包括環氧樹脂、聚亞醯胺、或前述之組合。
  16. 如申請專利範圍第11項所述之半導體元件的製造方法，其中該選擇性蝕刻步驟不使用一光阻層。
  17. 如申請專利範圍第11項所述之半導體元件的製造方法，其中該些電極之形成包括形成一兩個以上柱狀物之陣列於該些電極上，並連接至該導線層之第一端。
  18. 如申請專利範圍第11項所述之半導體元件的製造方法，其中該材料包括銅、鎳、錫、或前述之組合。
  19. 如申請專利範圍第11項所述之半導體元件的製造方法，其中該些電極之材質包括銅、銲錫、鎳、錫、或前述之組合。
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