CN101436559A - 半导体元件的制造方法 - Google Patents

半导体元件的制造方法 Download PDF

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Publication number
CN101436559A
CN101436559A CNA2008100863034A CN200810086303A CN101436559A CN 101436559 A CN101436559 A CN 101436559A CN A2008100863034 A CNA2008100863034 A CN A2008100863034A CN 200810086303 A CN200810086303 A CN 200810086303A CN 101436559 A CN101436559 A CN 101436559A
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China
Prior art keywords
layer
semiconductor substrate
resilient coating
electrode
manufacture method
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CNA2008100863034A
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English (en)
Inventor
王忠裕
李建勋
曹佩华
张国钦
林忠毅
江浩然
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN101436559A publication Critical patent/CN101436559A/zh
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Abstract

本发明提供一种半导体元件的制造方法，包括在半导体衬底的第一表面形成至少一柱电极，其中每一柱电极包括两个以上柱状物的阵列，柱电极电连接至半导体衬底的线路层，沉积缓冲层于第一表面上，缓冲层密封阵列，移除部分的缓冲层及部分的柱电极，而使柱电极的上表面低于残余的缓冲层的上表面，沉积导电覆盖层于柱电极的上表面上，其中导电覆盖层低于残余的缓冲层的上表面，以及放置焊球于导电覆盖层上，其中焊球与导电覆盖层之间的焊接点低于残余的缓冲层的上表面。本发明能够增进WLCSP中的焊球接点的可靠度。

Description

半导体元件的制造方法
技术领域
本发明涉及晶圆级晶片尺寸封装(wafer level chip-scale packaging，WLCSP)，且特别涉及增进WLCSP中的焊球接点(solder ball joints)的可靠度。
背景技术
在过去几十年来，电子与半导体封装技术的进步已冲击整个半导体工业。导入表面接合技术(surface-mount technology，SMT)与球栅阵列(ball gridarray，BGA)封装对于多种集成电路元件的高产率封装通常是重要的步骤，且还同时允许印刷电路板上的接垫间距缩小。通常集成电路的封装结构基本上由晶片上的金属接垫与散布自封装体的电极间的细金线来形成内连线。双列式封装(dual inline package，DIP)与四方扁平封装(quad flat package，QFP)是目前集成电路封装的基本结构。然而，随着周边设计与排列于封装体的针脚数目(pin count)的增加，使导线间之间距过小而限制电路板的晶片封装。
晶片尺寸封装(CSP)及球栅阵列(BGA)封装为在不大幅增加封装尺寸情况下，使电极的排列紧密的一种解决方案。CSP提供晶片尺寸的晶圆封装。CSP的封装结构一般小于1.2倍的裸片尺寸，大幅缩小以CSP封装的元件的尺寸。虽然，这些优点已使电子元件小型化，但一直以来对于更小、更轻、及更薄电子产品的需求，更加小型化封装结构的追求仍未曾间断。
为了满足市场对于更小型化与更多功能化电子产品的需求，近年来导入了晶圆级晶片尺寸封装(WLCSP)以增加元件密度、增进效能、与节省成本，并同时减小电子封装工业中的元件的重量与尺寸。在WLCSP封装中，封装体通常直接形成于裸片上，裸片具有由球栅阵列及凸块电极(bump electrodes)所提供的接点(contact)。近来的先进电子元件，例如行动电话、笔记型电脑、摄影机、个人数字助理(PDA)等，利用了密集且轻薄的紧密封装集成电路。使用WLCSP以较少数目的接脚来封装较小裸片尺寸的元件，可于一晶圆上形成更多的晶片，具有更高的成本效益。
现今的WLCSP技术的缺点是焊球与柱电极(electrode post)间会形成裂痕(cracks)。焊球或凸块一般直接放置于凸块电极或柱电极上，靠焊接点(solderjoint)来维持结构整体性。形成WLCSP元件的不同材料层之间一般具有不同的热膨胀系数(CTE)。因此，由不同热膨胀系数所引起的较大应力会发生在与柱电极及凸块电极之间的接点，常常在凸块电极/柱电极与焊球或凸块间的接合区造成裂缝。此外，焊球一般位于晶圆的材料层上方。焊球接合处的露出使焊球更容易受到物理冲击的影响，并亦使较脆弱的接点露出。
图1显示典型WLCSP封装结构10的单一焊球的剖面图。WLCSP封装结构直接形成于裸片100上。在裸片100上形成有铜垫102。铜垫102作为焊球101的接触点与接垫。在焊接工艺期间，金属间化合物(intermetalliccompounds，IMC)会于焊球101与铜垫102之间的接点自然地形成为一材料层(例如IMC形成层103)。虽然IMC形成层103的存在通常意味着焊料与衬底间有良好的焊接，但IMC形成层103通常是焊接点的最脆弱部分。因为在WLCPS封装中的焊接点非常小，使得裂痕(crack)(例如裂痕104)在应力施加于接点时可能更容易形成，且这样的裂痕由于整体封装结构尺寸较小，可能对结构伤害更大。再者，IMC形成层103位于裸片100的上表面上，因此会将此较脆弱区域曝露于较大的直接应力冲击。沿着焊球101的一侧生成的小裂痕(例如裂痕104)可容易地沿着焊接点横截面方向传播而变大。
美国专利US 6,600,234(Kuwabara，et al.)公开一种可减小上述应力裂痕的方法。此方法使用多层材料层来形成密封膜(sealing film)，其中部分的凸块电极自密封膜突出。突出的电极辅助吸收部分由热膨胀系数不同所造成的应力。密封层的多层材料层的选择亦可具有逐渐改变的热膨胀系数，使接近衬底的材料层具有与衬底相近的热膨胀系数，而接近电路衬底的材料层具有与电路衬底相近的热膨胀系数。此逐渐改变的热膨胀系数有助于缓和由急遽热膨胀系数差异所造成的应力。然而，密封层的多层材料层通常仍呈现较低的剪切强度(shear strength)，且无法减轻可能形成于IMC形成层中的裂缝的传播，因而减低接点的整体可靠度。
美国专利US 6,717,245(Kinsman，et al.)另提出一种增进晶片尺寸封装的方法。此方法以环氧树脂(epoxy)或其他相似材料完全封装第一凸块层(bumped layer)。接着研磨封装层以露出包装于其中的凸块的顶部。接着将一般的焊球印刷或放置于第一凸块层的露出部分上。借着通过第一凸块层的封装层而将焊球与电路板隔离，可减小热膨胀所造成的应力。然而，焊球接点仍容易沿着IMC形成层生成裂缝，因而减低接点的整体可靠度。
美国专利US 6,906,418(Hiatt，et al.)另提出一种增进晶片尺寸封装的方法。此方法提供两种不同的CSP封装实施例。第一实施例将来自裸片接垫的内连线接点(interconnect contact)的尖端部分(tip)延伸穿过绝缘层。在沉积金属化材料层于内连线接点的尖端部分后，将焊球放置于每一延伸尖端部分上。金属化材料层的材质选用能增进金属化材料层与焊球间的接合的材料。然而，因为焊球接点位于或高于绝缘层表面，焊球接点仍有不小的剪切应力。第二实施例提供的焊球直接放置于裸片接垫上或重分布层上。接着使用绝缘层将焊球封装，并留下部分露出区以用于接触。虽然此实施例增进焊球接点的强度，但将焊球直接放置于裸片接垫上需复杂的设计程序，会大幅增加CSP封装的成本。此外，内连线接点的结构亦会受限于裸片接垫的结构。
发明内容
鉴于以上问题，本发明提供一种半导体元件的制造方法，包括在半导体衬底的第一表面形成至少一个柱电极，其中每一柱电极包括两个以上柱状物的阵列，柱电极电连接至半导体衬底的线路层，沉积缓冲层于第一表面上，缓冲层密封阵列，移除部分的缓冲层及部分的柱电极，而使柱电极的上表面低于残余的缓冲层的上表面，沉积导电覆盖层于柱电极的上表面上，其中导电覆盖层低于残余的缓冲层的上表面，以及放置焊球于导电覆盖层上，其中焊球与导电覆盖层之间的焊接点低于残余的缓冲层的上表面。
根据本发明的半导体元件的制造方法，还包括沉积至少一个重分布层于所述半导体衬底的所述第一表面上，其中所述重分布层提供所述柱电极与所述线路层之间的电连接。
根据本发明的半导体元件的制造方法，其中所述半导体衬底包括：保护层，沉积于半导体衬底层上，其中所述保护层的上表面包括所述第一表面；以及电路层，位于所述半导体衬底层的有源区中，其中所述电路层电连接至所述线路层。
根据本发明的半导体元件的制造方法，其中所述半导体衬底还包括高分子绝缘层，沉积于所述保护层上，其中所述高分子绝缘层的上侧成为所述半导体衬底的所述第一表面。
根据本发明的半导体元件的制造方法，其中所述移除步骤包括移除部分的所述缓冲层及部分的所述柱电极，其中部分的所述柱电极的移除包括蚀刻所述柱电极以及研磨所述柱电极。
根据本发明的半导体元件的制造方法，其中所述移除步骤不使用光致抗蚀剂层。
根据本发明的半导体元件的制造方法，其中所述导电覆盖层的沉积包括通过无电电镀。
本发明另提供一种半导体元件的制造方法，包括形成多个电极于半导体衬底的第一表面上，其中电极凸出第一表面，将材料镀至电极上；沉积缓冲层于第一表面上，电极延伸穿过缓冲层，选择性蚀刻缓冲层以使电极的上表面低于残余的缓冲层的上表面，以及放置焊球于每一电极上，其中焊球与电极之间的接点低于缓冲层的上表面，及其中焊球通过材料及电极电连接至半导体衬底的线路层。
根据本发明的半导体元件的制造方法，还包括沉积至少一个重分布层于所述半导体衬底的所述第一表面上，其中所述重分布层提供所述多个电极与所述线路层之间的电连接。
根据本发明的半导体元件的制造方法，其中所述半导体衬底包括：保护层，沉积于半导体衬底层上，其中所述保护层的上表面包括所述第一表面；以及电路层，位于所述半导体衬底层的有源区中，其中所述电路层电连接至所述线路层。
根据本发明的半导体元件的制造方法，其中所述半导体衬底还包括高分子绝缘层，沉积于所述保护层上，其中所述高分子绝缘层的上侧成为所述半导体衬底的所述第一表面。
根据本发明的半导体元件的制造方法，其中所述选择性蚀刻步骤不使用光致抗蚀剂层。
根据本发明的半导体元件的制造方法，其中所述多个电极的形成包括形成两个以上柱状物的阵列于所述多个电极上，并连接至所述导线层的第一端。
本发明能够增进WLCSP中的焊球接点的可靠度。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出较佳实施例，并配合附图，作详细说明如下：
附图说明
图1显示典型WLCSP封装结构的单一焊球的剖面图。
图2显示本发明一个实施例的WLCSP封装结构的剖面图。
图3A-图3E显示本发明另一实施例的WLCSP封装结构的一系列工艺剖面图。
图4A-图4E显示本发明又一实施例的于半导体晶圆上形成WLCSP封装结构的一系列工艺剖面图。
图5A-图5F显示本发明再一实施例的于半导体晶圆上形成WLCSP封装结构的一系列工艺剖面图。
图6显示本发明一个实施例的工艺流程图。
图7显示本发明另一实施例的工艺流程图。
图8显示本发明又一实施例的工艺流程图。
其中，附图标记说明如下：
10、20、30～WLCSP封装结构；100、300～裸片；102～铜垫；101、204、308、408、509～焊球；103～IMC形成层；104～裂痕；200～晶圆；201、305～柱电极；202、403～绝缘层；203、307～覆盖层；205～IMC层；302、402～保护层；303～高分子绝缘层；301～线路层；304、404、503～重分布层；306、406、508～缓冲层；40、50～半导体晶圆；400～衬底；401～裸片接垫；405～多柱状物柱电极；407～低反应层；500～集成电路层；501～接垫；502～金属电镀晶种层；504～光致抗蚀剂层；505～电镀金属层；507～导电柱；600、601、602、603、604、700、701、702、703、704、800、801、802、803、804～步骤。
具体实施方式
图2显示本发明一个实施例的WLCSP封装结构20的剖面图。晶圆200包括形成于其上的柱电极201。绝缘层202形成于晶圆200的顶部上，且围绕柱电极201。在制造过程期间，柱电极201的顶部与绝缘层202的顶部同高。接着将柱电极201回蚀刻而使低于绝缘层202的顶部。在较佳实施例中，因为绝缘层202的材质是特别选定，使柱电极201的回蚀刻不会对绝缘层202造成影响，所以不需使用额外的光致抗蚀剂层来进行蚀刻。
沉积覆盖层203于柱电极201上，覆盖层203保护柱电极201免于氧化。在一个较佳实施例中，柱电极201的材质是铜。因此覆盖层203可保护铜柱电极201免于氧化。可以各种不同的方法沉积覆盖层203，包括无电电镀法(electroless plating)或其相似方法。接着将焊球204焊接、连接、或印刷至晶圆200上。焊接后形成接点(joint)于覆盖层203的顶部，且接点低于绝缘层202。因此，焊球204部分低于绝缘层202，且部分高于绝缘层202(另一部分)。再者，IMC层205(金属间化合物层)形成于焊球204与覆盖层203间的接合处，因此IMC层205受到绝缘层202的保护而免于受到直接物理接触。借着配置晶圆200使焊球204部分高于绝缘层202，并部分低于绝缘层202，且使焊接点低于绝缘层202的上表面，以及利用覆盖层205保护柱电极201免于受到氧化，此结构的焊接点会更可靠且具有较强的剪切与一般强度。
图3A显示本发明一个实施例的WLCSP封装结构30的前段工艺步骤剖面图。裸片300包括保护层302与高分子绝缘层303。位于裸片300顶部的线路层301连接至裸片300中的电路层(未显示)。沉积重分布层304于裸片300的高分子绝缘层303的顶部上。重分布层304将电连接延伸至线路层301。
应注意的是高分子绝缘层303可包括多种绝缘材料，例如聚亚酰胺(polyimide)或其他相似的高分子绝缘材料。第3A-3E图所提供的叙述并非意图将本发明限定的绝缘层限定为任何特定材料。事实上，在其他实施例中，WLCSP封装结构可不包括绝缘层(例如高分子绝缘层303)。
请参照图3B，沉积柱电极305于裸片300上。柱电极305可与重分布层304直接物理接触而形成与线路层301之间的电连接。因此，与柱电极305接触可形成电连接至裸片300中的电路层(未显示)。重分布层304的材质可选自多种有益的导电材料，例如铜、金、铝、锡、任何有益的导电材料的结合或合金、或前述的组合。
图3C显示本发明一个实施例的WLCSP封装结构30的下一工艺步骤剖面图。沉积缓冲层306于裸片300的顶部上以增加对于裸片300与柱电极305的保护。在一些实施例中，缓冲层306的选用可部分基于材料的热膨胀系数，以减少WLCSP封装结构因不同材料层的不同热膨胀系数所形成的应力。缓冲层306可例如包括环氧树脂、聚亚酰胺、或其相似物。本发明较佳实施例的缓冲层306的材质选择基准可亦考虑缓冲层306的材质对于可能用以蚀刻柱电极305的蚀刻剂的耐蚀程度。
图3D显示本发明一个实施例的WLCSP封装结构30的下一工艺步骤剖面图。使用不会影响缓冲层306的蚀刻剂将柱电极305回蚀刻而使低于缓冲层306的顶部。在执行此步骤时，可不使用其他光致抗蚀剂层而将柱电极305回蚀刻。在将柱电极305回蚀刻后，沉积覆盖层307于柱电极305上而覆盖柱电极305所露出的表面，但仍使覆盖层307的顶部低于缓冲层306的顶部。借着覆盖柱电极305的露出表面，覆盖层307保护柱电极305免于氧化。覆盖层307的材质选用导电材料，因而仍能维持覆盖层307与线路层301之间的电连接。例如，覆盖层307的材质可为镍、锡、其他相似材料、前述的合金、或前述的组合。
图3E显示本发明一个实施例的WLCSP封装结构30的剖面图。在沉积覆盖层307于每一柱电极(例如柱电极305)后，将焊球308印刷或焊接至柱电极305/覆盖层307上。因此，形成于焊球308与覆盖层307间的接点会低于缓冲层306的顶部。因此，缓冲层306可提供焊接点保护屏障。再者，形成于焊接点的IMC层亦受到缓冲层306的保护。所完成的WLCSP封装结构30具有更强且更可靠的焊接点。
图4A-图4E显示本发明一实施例于半导体晶圆40上形成WLCSP封装结构的一系列工艺剖面图。半导体晶圆40包括衬底400、裸片接垫401(diecontact)、保护层402、绝缘层403、及重分布层404。借着重分布层404的使用，封装设计与集成电路的布局可更流畅，这是因为封装结构的位置不会受限于裸片接垫(例如裸片接垫401)的位置。
形成多柱状物柱电极405(multi-column electrode post)于重分布层404上以提供电性接触至裸片接垫401(如第4B图所示)。多柱状物柱电极405可使用形成金属层的任何方法来形成。例如，可放置光致抗蚀剂层或薄片于半导体晶圆40的顶部，光致抗蚀剂层或薄片上具有凹槽以蚀刻其下的金属层于而形成多柱状物柱电极405。或者，可于光致抗蚀剂层或薄片的凹槽中填充导电材料来形成多柱状物柱电极405。多柱状物柱电极405的材质包括铜、镍、铝、钨、前述的相似物、前述的合金、或前述的组合。
在显示于图4A-图4E中的WLCSP封装结构的实施例中，每一多柱状物柱电极405的柱状物可较佳具有介于约10微米至约20微米之间的外径，且每一柱状物之间的间距较佳介于约10微米至约20微米之间。接着沉积封装材料(例如应力缓冲层)于具有上述较佳尺寸柱状物的封装结构上。
图4C显示沉积于半导体晶圆40的顶部上的缓冲层406。缓冲层406将每一多柱状物柱电极405的柱状物密封于其中。缓冲层406的密封增强多柱状物柱电极405的强度。如第4D图所示，将缓冲层406回蚀刻而露出多柱状物柱电极405，并于其上沉积低反应层407(low reactive layer)。低反应层407的材质较佳包括能增强与焊球或凸块间的接合的材料，且亦具有较小IMC缺陷成长速度。低反应层407的材质例如包括镍、锡、其相似物、或前述的组合。
一旦沉积了低反应层407于多柱状物柱电极405，可将焊球408印刷或放置于半导体晶圆40上(如第4E图所示)。低反应层407被放置于缓冲层406的表面下方，因此焊球408与低反应层407间的焊球接点低于缓冲层406的表面。此设计提供一些防护以抵抗产生在焊球408上的剪切应力，又缓冲层406的材质选用具有特定热膨胀系数的材料，亦可减低焊球接点上的热膨胀应力。
图4A-图4E所叙述的多柱状物柱电极的实施例较单柱柱电极的实施例有较佳的封装应力抵抗力。首先，因为与焊球的接点分散在每一柱状物上，裂痕将无法轻易地沿着整个接点传播。因为裂痕会沿着破裂线(fracture line)传播，所以裂痕仅会往单一柱状物内部传播，而不再沿着整个接点的横截面方向传播。再者，埋在各柱状物间的应力缓冲层可进一步增强裂缝抵抗力(因为具有金属柱状物/缓冲层复合结构)。缓冲层的材料特性(例如有机应力缓冲材料)可增进具有金属柱状物/缓冲层复合结构的多柱状物柱电极结构对于裂缝的抵抗力。
图5A-图5E显示本发明一个实施例于半导体晶圆50上形成WLCSP封装结构的一系列工艺剖面图。图5A显示半导体晶圆50，包括集成电路层500、接垫501、金属电镀晶种层502、重分布层503、及光致抗蚀剂层504。凹槽506已借着蚀刻进入光致抗蚀剂层504而形成，且凹槽506的内壁还覆盖有电镀金属层505。如图5B所示，接着形成导电柱507于凹槽506中。形成导电柱507之前可选择性地移除凹槽506外的电镀金属层505。
应注意的是电镀金属层505与导电柱507较佳选用不同的导电材料。例如，电镀金属层505可包括镍、锡、铜、其相似物、或前述的组合，而导电柱507可包括铜、焊锡、锡、镍、其相似物、或前述的组合。当电镀金属层505的材质包括镍时，焊料/铜的IMC层的成长会减低。当电镀金属层505的材质包括镍而导电柱507的材质包括焊锡时，此柱状结构较使用材质较硬的铜柱状结构更具韧性。因此，当封装结构受到热应力时，柱状结构可承受较大的变形而可减低焊球接点上的应力程度。
在图5C中，将光致抗蚀剂层504移除，且将金属电镀晶种层502回蚀刻使与重分布层503对齐。接着如图5D所示，沉积缓冲层508于半导体晶圆50上以封装各元件，包括电镀金属层505及导电柱507。如图5E所示，研磨缓冲层508降低其上表面，并进一步蚀刻导电柱507使低于缓冲层508的表面。接着如图5F所示，将焊球509印刷或放置于半导体晶圆50上，使焊球接点低于缓冲层508的表面。借着将焊球接点放置于缓冲层508的表面下，可有效地使焊球接点远离高应力区域，因此焊球接点会受到较小的剪切应力。
图6显示本发明一个实施例的工艺流程图。在步骤600中，形成至少一柱电极于半导体衬底的第一表面上，其中每一柱电极由两个以上柱状物的阵列形成，且电连接至半导体衬底的线路层。在步骤601中，沉积缓冲层于第一表面上以封装柱电极的柱状物阵列。在步骤602中，移除部分柱电极而使柱电极的上表面低于缓冲层的上表面。在步骤603中，沉积导电覆盖层于露出的多柱状物柱电极的上表面上，其中导电覆盖层亦低于缓冲层的上表面。在步骤604中，将焊球放置于每一导电覆盖层上，其中焊球与导电覆盖层间的接点低于缓冲层的顶部。
图7显示本发明另一实施例的工艺流程图。在步骤700中，形成多个电极于半导体衬底的第一表面，其中电极突出第一表面。在步骤701中，将电镀材料电镀于电极。在步骤702中，沉积缓冲层于第一表面而完全覆盖电极的延伸。在步骤703中，选择性蚀刻缓冲层而使电极的上表面露出并低于缓冲层的顶部。在步骤704中，将焊球放置于每一电极上，其中焊球与每一电极间的接点低于缓冲层的顶部，且焊球通过电镀材料与电极而电连接至半导体衬底的导线层。
图8显示本发明又一实施例的工艺流程图。在步骤800中，形成多个柱电极于半导体衬底的第一表面，其中每一柱电极是由两个以上的柱状物阵列所形成。在步骤801中，将一电镀材料电镀至多柱状物柱电极上。在步骤802中，沉积缓冲层于第一表面上，其中多柱状物柱电极延伸穿过缓冲层。在步骤803中，选择性蚀刻缓冲层而使多柱状物柱电极的上表面露出并低于缓冲层的顶部。在步骤804中，将焊球放置于每一多柱状物柱电极上，其中焊球与每一多柱状物柱电极间的接点低于缓冲层的顶部，且焊球通过电镀材料与多柱状物柱电极而电连接至半导体衬底的线路层。
虽然本发明已以数个较佳实施例公开如上，然其并非用以限定本发明，本领域技术人员在不脱离本发明的精神和范围内，当可作任意的变化与修改，因此本发明的保护范围当视后附的权利要求所界定者为准。

Claims (13)

1.一种半导体元件的制造方法，包括：
在半导体衬底的第一表面形成至少一柱电极，其中每一柱电极包括两个以上柱状物的阵列，该柱电极电连接至所述半导体衬底的线路层；
沉积缓冲层于所述第一表面上，所述缓冲层密封所述阵列；
移除部分的所述缓冲层，而使所述柱电极的上表面低于残余的所述缓冲层的上表面；
沉积导电覆盖层于所述柱电极的上表面上，其中所述导电覆盖层低于残余的所述缓冲层的上表面；以及
放置焊球于所述导电覆盖层上，其中所述焊球与所述导电覆盖层之间的焊接点低于残余的所述缓冲层的上表面。
2.如权利要求1所述的半导体元件的制造方法，还包括沉积至少一个重分布层于所述半导体衬底的所述第一表面上，其中所述重分布层提供所述柱电极与所述线路层之间的电连接。
3.如权利要求1所述的半导体元件的制造方法，其中所述半导体衬底包括：
保护层，沉积于半导体衬底层上，其中所述保护层的上表面包括所述第一表面；以及
电路层，位于所述半导体衬底层的有源区中，其中所述电路层电连接至所述线路层。
4.如权利要求3所述的半导体元件的制造方法，其中所述半导体衬底还包括高分子绝缘层，沉积于所述保护层上，其中所述高分子绝缘层的上侧成为所述半导体衬底的所述第一表面。
5.如权利要求1所述的半导体元件的制造方法，其中所述移除步骤包括移除部分的所述缓冲层及部分的所述柱电极，其中部分的所述柱电极的移除包括蚀刻所述柱电极以及研磨所述柱电极。
6.如权利要求1所述的半导体元件的制造方法，其中所述移除步骤不使用光致抗蚀剂层。
7.如权利要求1所述的半导体元件的制造方法，其中所述导电覆盖层的沉积包括通过无电电镀。
8.一种半导体元件的制造方法，包括：
形成多个电极于半导体衬底的第一表面上，其中所述多个电极凸出所述第一表面；
将材料镀至所述多个电极上；
沉积缓冲层于所述第一表面上，所述多个电极延伸穿过所述缓冲层；
选择性蚀刻所述缓冲层以使所述多个电极的上表面低于残余的所述缓冲层的上表面；以及
放置焊球于每一电极上，其中所述焊球与所述多个电极之间的接点低于所述缓冲层的所述上表面，及其中所述焊球通过所述材料及所述多个电极电连接至所述半导体衬底的线路层。
9.如权利要求8所述的半导体元件的制造方法，还包括沉积至少一个重分布层于所述半导体衬底的所述第一表面上，其中所述重分布层提供所述多个电极与所述线路层之间的电连接。
10.如权利要求8所述的半导体元件的制造方法，其中所述半导体衬底包括：
保护层，沉积于半导体衬底层上，其中所述保护层的上表面包括所述第一表面；以及
电路层，位于所述半导体衬底层的有源区中，其中所述电路层电连接至所述线路层。
11.如权利要求10所述的半导体元件的制造方法，其中所述半导体衬底还包括高分子绝缘层，沉积于所述保护层上，其中所述高分子绝缘层的上侧成为所述半导体衬底的所述第一表面。
12.如权利要求8所述的半导体元件的制造方法，其中所述选择性蚀刻步骤不使用光致抗蚀剂层。
13.如权利要求8所述的半导体元件的制造方法，其中所述多个电极的形成包括形成两个以上柱状物的阵列于所述多个电极上，并连接至所述导线层的第一端。
CNA2008100863034A 2007-11-16 2008-03-25 半导体元件的制造方法 Pending CN101436559A (zh)

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US20090130840A1 (en) 2009-05-21
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US9136211B2 (en) 2015-09-15
US8492263B2 (en) 2013-07-23

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