JP3516592B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法Info
- Publication number
- JP3516592B2 JP3516592B2 JP23189498A JP23189498A JP3516592B2 JP 3516592 B2 JP3516592 B2 JP 3516592B2 JP 23189498 A JP23189498 A JP 23189498A JP 23189498 A JP23189498 A JP 23189498A JP 3516592 B2 JP3516592 B2 JP 3516592B2
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- Prior art keywords
- wafer
- resin
- manufacturing
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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Description
装置およびその製造方法、特に、ウエハ状態で封止をお
こなう半導体装置とその製造方法に関するものである。
伴ってその中に搭載される樹脂封止型半導体装置も薄
型、小型、軽量のものが要求されるようになっており、
これらに対応するために数多くのものが提案されてい
る。そのような技術として、半導体チップと同等のサイ
ズに形成されたチップ・サイズ・パッケージ(以下CS
Pという)が開発されている。CSP形成方法の一例と
しては、まず、ウエハ状態で個々の素子領域の電極パッ
ド上に突起電極を形成する。次に、この突起電極が形成
されたウエハ全面上を樹脂で封止し、樹脂が硬化後、こ
の樹脂を突起電極が露出するまで研磨する。その後、個
々のチップに分割するという工程で形成する方法があ
る。このような技術を開示してる文献の例としては、特
開平10−50772号公報に開示される技術がある。
CSPの形成方法では、個片に分割する際に、ダイシン
グラインが樹脂にて覆われているため、ダイシングの位
置が認識しにくいという問題点がある。
が形成されているウエハの、チップ領域上に突起電極を
形成し、この複数のチップ領域の境界領域に溝を形成す
る。その後、この溝の形成された前記ウエハの表面を樹
脂で覆い、ウエハの裏面を研磨し、この裏面に溝を露出
させる。次に、この露出した溝部分でウエハを個片に分
割する。
施例を詳細に説明する。まず、図1を用いて、本願発明
により得られる半導体装置の構造を説明する。図1にお
いて、半導体チップ1上にはアルミ電極2が形成されて
いる。このアルミ電極2は、導電層、例えば銅の配線3
により、導電性の突起電極、例えば銅のポスト4と接続
されている。また、このアルミ電極2は、半導体チップ
1上に形成された図示しない集積回路と接続されてい
る。このアルミ電極は、図示しない保護膜である例えば
窒化膜などの素子領域を保護する保護膜に形成された開
口部から露出している。配線3およびポスト4は、この
保護膜上に形成されている。ポスト4の表面にはそれぞ
れはんだボールなどの金属電極5が形成されている。
法について説明する。まず、図2(a)〜(d)を用い
て、ウエハ10上にポスト4を形成する工程を説明す
る。図2(a)に示すように、電極2およびパッシベー
ション膜11の形成されたウエハ10上に、この電極2
上に開口部12を有する、例えばポリイミドなどからな
る層間膜13を形成する。次に、図2(b)に示すよう
に、ウエハ全面上にメッキ電極14を形成する。メッキ
電極としては、例えばチタン14a、銅14bを順次ス
パッタ形成する。このメッキ電極14上にレジスト15
を形成し、レジスト15の配線3に対応する領域を除去
する。図2(c)に示すようにレジストの除去された領
域に厚さ5μm程度の銅からなる配線3を電解メッキに
より形成する。配線3は5μm程度の幅で形成する。こ
のレジストを除去した後に、この配線3の形成されたウ
エハ10全面上に、厚さ100μm程度のフィルム状の
レジスト16を貼付け、再配線3と接続する位置に開口
部を形成する。図2(d)に示すように、この開口部に
電解メッキにより直径200〜250μm程度、厚さ1
00〜150μm程度の銅のポスト4を形成する。ポス
ト4を形成後、フィルム状のレジスト16を取り除く。
(c)を用いて、ポスト4の形成されたウエハを樹脂封
止し、個片に分割するまでの工程を説明する。図3
(a)は、図2(d)における工程の後、フィルム状の
レジスト16を除去したものである。この図3(a)で
は、図2(d)におけるパッシベーション膜11、保護
膜13、メッキ電極14は図面から省略し、電極2、配
線3、ポスト4のみを開示している。このようなポスト
4の形成されたウエハ10を、図3(b)に示すよう
に、各半導体素子間を例えばダイヤモンドブレードなど
の刃21で削り、溝22を形成する。刃21の厚さは3
5μm程度のものを用い、溝22の幅を例えば35μm程
度とする。この溝22の深さとしては、ウエハ10の厚
さの半分より深く、好ましくはウエハ10の深さの2/
3程度の深さとする。深くしすぎると、この状態で個片
に分割されてしまい、また、深さが足りないと、樹脂封
止時の樹脂収縮により溝部にクラックが入ってしまうお
それがある。例えば、ウエハ10の厚さが600μmと
すれば、溝の深さは400μm程度とすることが好まし
い。
にてウエハ10表面を封止する。この樹脂23は、ポス
ト4を50μm程度覆う厚さ、例えば、150μm程度の
厚さに形成する。
の樹脂23を硬化させた後、図3(d)に示すように、
研磨刃24を用いて樹脂23の表面を研磨し、ポスト4
を露出させる。ポスト4上には、樹脂が50μm程度形
成されており、ポスト4を完全に露出させるためには、
樹脂を60〜70μm程度研磨するとよい。
25を用いてウエハ10の裏面を研磨する。この際に、
完成デバイスのチップの厚さを200〜300μmとす
るために、研磨する厚さは300〜400μm程度とす
る。これにより溝22がウエハ10の裏面から完全に露
出する。この状態で、露出しているポスト4の表面には
んだボールなどの金属電極5を形成する。
目印にして、ダイヤモンドブレードなどの刃26を用い
てウエハ10を裏面から切断する。この刃26は、図3
(b)に示される工程で用いた刃21よりも薄く、例え
ば25μm程度のものを用いる。これにより、図4
(c)に示すような個々のチップ1の側面が樹脂で封止
された半導体装置を得ることができる。
に樹脂23を充填させたが、この樹脂として、例えば粘
度の高い樹脂を使用し、溝22内に樹脂が残らないよう
にウエハ10の表面を封止してもよい。さらに、この樹
脂が硬化した後にウエハ10の裏面を研磨し、溝22を
露出させると、各チップはその表面が樹脂に接している
状態で個片に分割される。この場合は、溝内に樹脂が充
填されないため、樹脂の収縮による樹脂封止後のウエハ
の反りが低減される。このように、溝22内に樹脂が充
填されないように樹脂封止した後に個片に分割した場
合、図5に示すようにチップ1の側面が露出している半
導体装置が得られる。
5をポスト4上に形成せずにウエハ10を個片に分割し
てもよい。この場合は、図6に示すように、ポスト4の
露出している表面の腐食を防止するために、ポスト4上
にニッケルと金の積層膜13を無電解メッキにより形成
することにより、金属電極のないタイプの半導体装置が
得られる。このようなタイプの半導体装置は、実装され
る基板上に形成されたはんだなどの上にポスト4をあわ
せることにより、基板上に実装することが可能である。
(d)および図4(a)に示されるように、ウエハ10
の表面上に形成した樹脂23を研磨してポスト4を露出
させた後にウエハ10の裏面を研磨し、溝22をウエハ
10の裏面から露出させたが、この順番を変えてもよ
い。すなわち、先にウエハ10の裏面を研磨し、溝22
をウエハ10の裏面から露出させ、その後、樹脂23を
研磨してポスト4を露出させてもよい。このようにする
と、樹脂23を研磨する時には、既にウエハ10は個片
のチップに分割された状態であるため、ウエハと樹脂と
の収縮応力の差によるウエハの反りを低減することが可
能である。
ハに溝を形成した後に、このウエハ表面を樹脂で覆い、
ウエハ裏面から溝が露出するまで研磨するようにしたの
で、ウエハを個片に分割する際に、裏面から露出してい
る溝を目印とすることができ、確実に個片に分割するこ
とが可能となる。
明する図である。
明する図である。
明する図である。
る。
る。
Claims (10)
- 【請求項1】 表面に複数のチップ領域を有するウエハ
の、電極及び該電極と接続された配線が設けられた前記
チップ領域各々の上に、前記配線と接続される突起電極
を形成する工程と、 前記複数のチップ領域の境界領域に溝を形成する工程
と、 前記溝内に樹脂が充填されるように、前記ウエハの表面
を樹脂で覆う工程と、 前記樹脂と前記ウエハの裏面をそれぞれ研磨すること
で、研磨したウエハの表面からは前記突起電極の表面を
露出させ、該裏面からは前記溝に充填された樹脂を露出
させる工程と、 個片に分割された半導体チップの側面に樹脂が残るよう
に、前記ウエハを前記境界領域にて、該ウエハの裏面が
露出した状態で、分割する工程と、 を有することを特徴とする半導体装置の製造方法。 - 【請求項2】 前記溝は、前記ウエハの厚さの半分より
も深く形成されることを特徴とする請求項1記載の半導
体装置の製造方法。 - 【請求項3】 前記溝は、前記ウエハの表面から形成す
ることを特徴とする請求項1または請求項2記載の半導
体装置の製造方法。 - 【請求項4】 前記ウエハを前記境界領域で分割する工
程は、このウエハの裏面よりおこなうことを特徴とする
請求項1〜3のいずれか1つに記載の半導体装置の製造
方法。 - 【請求項5】 前記突起電極の表面を露出させ、前記ウ
エハの裏面から前記溝に充填された樹脂を露出させる工
程と前記ウエハを前記境界領域で分割する工程との間
に、該露出した突起電極の表面上に金属電極を設ける工
程を有することを特徴とする請求項1〜4のいずれか1
つに記載の半導体装置の製造方法。 - 【請求項6】 前記金属電極ははんだボールであること
を特徴とする請求項5記載の半導体装置の製造方法。 - 【請求項7】 前記金属電極はメッキ層であることを特
徴とする請求項5記載の半導体装置の製造方法。 - 【請求項8】 前記配線は、銅により形成されることを
特徴とする請求項1〜7のいずれか1つに記載の半導体
装置の製造方法。 - 【請求項9】 前記突起電極は、銅により形成されるこ
とを特徴とする請求項1〜8のいずれか1つに記載の半
導体装置の製造方法。 - 【請求項10】 請求項1〜9記載の半導体装置の製造
方法を用いて製造され、前記半導体チップの側面が前記
樹脂で封止され、該半導体チップの裏面は露出している
ことを特徴とする半導体装置。
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US09/184,836 US6107164A (en) | 1998-08-18 | 1998-11-03 | Using grooves as alignment marks when dicing an encapsulated semiconductor wafer |
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Families Citing this family (139)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3346320B2 (ja) * | 1999-02-03 | 2002-11-18 | カシオ計算機株式会社 | 半導体装置及びその製造方法 |
JP3423245B2 (ja) | 1999-04-09 | 2003-07-07 | 沖電気工業株式会社 | 半導体装置及びその実装方法 |
US6579748B1 (en) * | 1999-05-18 | 2003-06-17 | Sanyu Rec Co., Ltd. | Fabrication method of an electronic component |
JP2001085361A (ja) * | 1999-09-10 | 2001-03-30 | Oki Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP3548061B2 (ja) * | 1999-10-13 | 2004-07-28 | 三洋電機株式会社 | 半導体装置の製造方法 |
JP3455762B2 (ja) * | 1999-11-11 | 2003-10-14 | カシオ計算機株式会社 | 半導体装置およびその製造方法 |
JP3784597B2 (ja) * | 1999-12-27 | 2006-06-14 | 沖電気工業株式会社 | 封止樹脂及び樹脂封止型半導体装置 |
JP3573048B2 (ja) * | 2000-02-14 | 2004-10-06 | 松下電器産業株式会社 | 半導体装置の製造方法 |
JP4626008B2 (ja) * | 2000-04-04 | 2011-02-02 | 日本テキサス・インスツルメンツ株式会社 | 半導体装置 |
JP4403631B2 (ja) * | 2000-04-24 | 2010-01-27 | ソニー株式会社 | チップ状電子部品の製造方法、並びにその製造に用いる擬似ウエーハの製造方法 |
US6403449B1 (en) * | 2000-04-28 | 2002-06-11 | Micron Technology, Inc. | Method of relieving surface tension on a semiconductor wafer |
JP2001313350A (ja) * | 2000-04-28 | 2001-11-09 | Sony Corp | チップ状電子部品及びその製造方法、並びにその製造に用いる疑似ウエーハ及びその製造方法 |
JP3631956B2 (ja) * | 2000-05-12 | 2005-03-23 | 富士通株式会社 | 半導体チップの実装方法 |
US6717245B1 (en) * | 2000-06-02 | 2004-04-06 | Micron Technology, Inc. | Chip scale packages performed by wafer level processing |
US6528393B2 (en) | 2000-06-13 | 2003-03-04 | Advanced Semiconductor Engineering, Inc. | Method of making a semiconductor package by dicing a wafer from the backside surface thereof |
JP2002050670A (ja) * | 2000-08-04 | 2002-02-15 | Toshiba Corp | ピックアップ装置及びピックアップ方法 |
JP3405456B2 (ja) * | 2000-09-11 | 2003-05-12 | 沖電気工業株式会社 | 半導体装置,半導体装置の製造方法,スタック型半導体装置及びスタック型半導体装置の製造方法 |
JP4508396B2 (ja) * | 2000-10-30 | 2010-07-21 | パナソニック株式会社 | チップ型半導体装置及びその製造方法 |
US6506681B2 (en) * | 2000-12-06 | 2003-01-14 | Micron Technology, Inc. | Thin flip—chip method |
JP4780844B2 (ja) * | 2001-03-05 | 2011-09-28 | Okiセミコンダクタ株式会社 | 半導体装置 |
US6798931B2 (en) * | 2001-03-06 | 2004-09-28 | Digital Optics Corp. | Separating of optical integrated modules and structures formed thereby |
JP3609737B2 (ja) * | 2001-03-22 | 2005-01-12 | 三洋電機株式会社 | 回路装置の製造方法 |
KR20020091327A (ko) * | 2001-05-31 | 2002-12-06 | 삼성전자 주식회사 | 측면 몸체부가 형성되어 있는 웨이퍼 레벨 패키지 및 그제조 방법 |
JP4529319B2 (ja) * | 2001-06-27 | 2010-08-25 | 日亜化学工業株式会社 | 半導体チップとその製造方法 |
US6794751B2 (en) * | 2001-06-29 | 2004-09-21 | Intel Corporation | Multi-purpose planarizing/back-grind/pre-underfill arrangements for bumped wafers and dies |
JP3530158B2 (ja) * | 2001-08-21 | 2004-05-24 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
JP2003100666A (ja) * | 2001-09-26 | 2003-04-04 | Toshiba Corp | 半導体装置の製造方法 |
DE10149689A1 (de) | 2001-10-09 | 2003-04-10 | Philips Corp Intellectual Pty | Elektrisches oder elektronische Bauteil und Verfahren zum Herstellen desselben |
US6573156B1 (en) | 2001-12-13 | 2003-06-03 | Omm, Inc. | Low defect method for die singulation and for structural support for handling thin film devices |
DE10202881B4 (de) * | 2002-01-25 | 2007-09-20 | Infineon Technologies Ag | Verfahren zur Herstellung von Halbleiterchips mit einer Chipkantenschutzschicht, insondere für Wafer Level Packaging Chips |
JP3829325B2 (ja) | 2002-02-07 | 2006-10-04 | 日本電気株式会社 | 半導体素子およびその製造方法並びに半導体装置の製造方法 |
US6908784B1 (en) | 2002-03-06 | 2005-06-21 | Micron Technology, Inc. | Method for fabricating encapsulated semiconductor components |
JP2003273279A (ja) * | 2002-03-18 | 2003-09-26 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US6903442B2 (en) * | 2002-08-29 | 2005-06-07 | Micron Technology, Inc. | Semiconductor component having backside pin contacts |
US6649445B1 (en) * | 2002-09-11 | 2003-11-18 | Motorola, Inc. | Wafer coating and singulation method |
AU2003291199A1 (en) * | 2002-12-09 | 2004-06-30 | Advanced Interconnect Technologies Limited | Package having exposed integrated circuit device |
JP2004288816A (ja) * | 2003-03-20 | 2004-10-14 | Seiko Epson Corp | 半導体ウエハ、半導体装置及びその製造方法、回路基板並びに電子機器 |
JP3574450B1 (ja) * | 2003-05-16 | 2004-10-06 | 沖電気工業株式会社 | 半導体装置、及び半導体装置の製造方法 |
US20040235272A1 (en) * | 2003-05-23 | 2004-11-25 | Howard Gregory E. | Scribe street width reduction by deep trench and shallow saw cut |
US20050147489A1 (en) * | 2003-12-24 | 2005-07-07 | Tian-An Chen | Wafer supporting system for semiconductor wafers |
JP2005209861A (ja) * | 2004-01-22 | 2005-08-04 | Nippon Steel Corp | ウェハレベルパッケージ及びその製造方法 |
US7281535B2 (en) * | 2004-02-23 | 2007-10-16 | Towa Intercon Technology, Inc. | Saw singulation |
TWI245350B (en) * | 2004-03-25 | 2005-12-11 | Siliconware Precision Industries Co Ltd | Wafer level semiconductor package with build-up layer |
US7705432B2 (en) * | 2004-04-13 | 2010-04-27 | Vertical Circuits, Inc. | Three dimensional six surface conformal die coating |
US7215018B2 (en) * | 2004-04-13 | 2007-05-08 | Vertical Circuits, Inc. | Stacked die BGA or LGA component assembly |
US7141487B2 (en) * | 2004-07-01 | 2006-11-28 | Agency For Science Technology And Research | Method for ultra thinning bumped wafers for flip chip |
JP2006032598A (ja) * | 2004-07-15 | 2006-02-02 | Renesas Technology Corp | 半導体装置の製造方法および半導体装置 |
WO2006008795A1 (ja) | 2004-07-16 | 2006-01-26 | Shinko Electric Industries Co., Ltd. | 半導体装置の製造方法 |
US7199449B2 (en) * | 2004-08-24 | 2007-04-03 | Micron Technology, Inc. | Wafer backside removal to complete through-holes and provide wafer singulation during the formation of a semiconductor device |
JP2006196701A (ja) * | 2005-01-13 | 2006-07-27 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
JP2006203079A (ja) * | 2005-01-21 | 2006-08-03 | Sharp Corp | 半導体装置および半導体装置の製造方法 |
JP4667094B2 (ja) * | 2005-03-18 | 2011-04-06 | 富士通株式会社 | 電子装置の製造方法 |
US7364945B2 (en) | 2005-03-31 | 2008-04-29 | Stats Chippac Ltd. | Method of mounting an integrated circuit package in an encapsulant cavity |
KR100700395B1 (ko) * | 2005-04-25 | 2007-03-28 | 신꼬오덴기 고교 가부시키가이샤 | 반도체 장치의 제조 방법 |
US7354800B2 (en) | 2005-04-29 | 2008-04-08 | Stats Chippac Ltd. | Method of fabricating a stacked integrated circuit package system |
TWI284949B (en) * | 2005-09-09 | 2007-08-01 | Chipmos Technologies Inc | Bumped structure and its forming method |
US8153464B2 (en) * | 2005-10-18 | 2012-04-10 | International Rectifier Corporation | Wafer singulation process |
US7432133B2 (en) * | 2005-10-24 | 2008-10-07 | Freescale Semiconductor, Inc. | Plastic packaged device with die interface layer |
TWI303870B (en) * | 2005-12-30 | 2008-12-01 | Advanced Semiconductor Eng | Structure and mtehod for packaging a chip |
US7768125B2 (en) * | 2006-01-04 | 2010-08-03 | Stats Chippac Ltd. | Multi-chip package system |
US7456088B2 (en) | 2006-01-04 | 2008-11-25 | Stats Chippac Ltd. | Integrated circuit package system including stacked die |
US7750482B2 (en) * | 2006-02-09 | 2010-07-06 | Stats Chippac Ltd. | Integrated circuit package system including zero fillet resin |
US8704349B2 (en) * | 2006-02-14 | 2014-04-22 | Stats Chippac Ltd. | Integrated circuit package system with exposed interconnects |
US7385299B2 (en) * | 2006-02-25 | 2008-06-10 | Stats Chippac Ltd. | Stackable integrated circuit package system with multiple interconnect interface |
TWI364793B (en) * | 2007-05-08 | 2012-05-21 | Mutual Pak Technology Co Ltd | Package structure for integrated circuit device and method of the same |
US7820543B2 (en) * | 2007-05-29 | 2010-10-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Enhanced copper posts for wafer level chip scale packaging |
US8723332B2 (en) | 2007-06-11 | 2014-05-13 | Invensas Corporation | Electrically interconnected stacked die assemblies |
TWI473183B (zh) * | 2007-06-19 | 2015-02-11 | Invensas Corp | 可堆疊的積體電路晶片的晶圓水平表面鈍化 |
TW200917391A (en) * | 2007-06-20 | 2009-04-16 | Vertical Circuits Inc | Three-dimensional circuitry formed on integrated circuit device using two-dimensional fabrication |
US7838424B2 (en) * | 2007-07-03 | 2010-11-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Enhanced reliability of wafer-level chip-scale packaging (WLCSP) die separation using dry etching |
US8759964B2 (en) | 2007-07-17 | 2014-06-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer level package structure and fabrication methods |
WO2009028538A1 (ja) * | 2007-08-27 | 2009-03-05 | Nec Corporation | 半導体素子及びその製造方法 |
US8704379B2 (en) | 2007-09-10 | 2014-04-22 | Invensas Corporation | Semiconductor die mount by conformal die coating |
US8492263B2 (en) * | 2007-11-16 | 2013-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protected solder ball joints in wafer level chip-scale packaging |
US7824962B2 (en) * | 2008-01-29 | 2010-11-02 | Infineon Technologies Ag | Method of integrated circuit fabrication |
JP2008147697A (ja) * | 2008-02-04 | 2008-06-26 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法 |
KR101554761B1 (ko) | 2008-03-12 | 2015-09-21 | 인벤사스 코포레이션 | 지지부에 실장되는 전기적으로 인터커넥트된 다이 조립체 |
JPWO2009122867A1 (ja) * | 2008-03-31 | 2011-07-28 | 日本電気株式会社 | 半導体装置、複合回路装置及びそれらの製造方法 |
US7517726B1 (en) * | 2008-04-25 | 2009-04-14 | Shanghai Kaihong Technology Co., Ltd | Wire bonded chip scale package fabrication methods |
US7863159B2 (en) * | 2008-06-19 | 2011-01-04 | Vertical Circuits, Inc. | Semiconductor die separation method |
US9153517B2 (en) | 2008-05-20 | 2015-10-06 | Invensas Corporation | Electrical connector between die pad and z-interconnect for stacked die assemblies |
JP5963671B2 (ja) * | 2009-06-26 | 2016-08-03 | インヴェンサス・コーポレーション | ジグザクの構成でスタックされたダイに関する電気的相互接続 |
JP2011014603A (ja) * | 2009-06-30 | 2011-01-20 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
TW201113962A (en) * | 2009-10-14 | 2011-04-16 | Advanced Semiconductor Eng | Chip having metal pillar structure |
TWI445147B (zh) * | 2009-10-14 | 2014-07-11 | Advanced Semiconductor Eng | 半導體元件 |
WO2011056668A2 (en) | 2009-10-27 | 2011-05-12 | Vertical Circuits, Inc. | Selective die electrical insulation additive process |
TWI544604B (zh) | 2009-11-04 | 2016-08-01 | 英維瑟斯公司 | 具有降低應力電互連的堆疊晶粒總成 |
US8299616B2 (en) * | 2010-01-29 | 2012-10-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | T-shaped post for semiconductor devices |
US8318596B2 (en) * | 2010-02-11 | 2012-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pillar structure having a non-planar surface for semiconductor devices |
US8803319B2 (en) | 2010-02-11 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pillar structure having a non-planar surface for semiconductor devices |
US8236613B2 (en) * | 2010-05-24 | 2012-08-07 | Alpha & Omega Semiconductor Inc. | Wafer level chip scale package method using clip array |
US20110291264A1 (en) * | 2010-06-01 | 2011-12-01 | Daesik Choi | Integrated circuit packaging system with posts and method of manufacture thereof |
US8241963B2 (en) | 2010-07-13 | 2012-08-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Recessed pillar structure |
US9224647B2 (en) | 2010-09-24 | 2015-12-29 | Stats Chippac, Ltd. | Semiconductor device and method of forming TSV interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer |
TWI478303B (zh) | 2010-09-27 | 2015-03-21 | Advanced Semiconductor Eng | 具有金屬柱之晶片及具有金屬柱之晶片之封裝結構 |
US8993377B2 (en) | 2010-09-29 | 2015-03-31 | Stats Chippac, Ltd. | Semiconductor device and method of bonding different size semiconductor die at the wafer level |
TWI451546B (zh) | 2010-10-29 | 2014-09-01 | Advanced Semiconductor Eng | 堆疊式封裝結構、其封裝結構及封裝結構之製造方法 |
CN102543767B (zh) * | 2010-12-07 | 2015-04-08 | 万国半导体(开曼)股份有限公司 | 一种在晶圆级封装的塑封工序中避免晶圆破损的方法 |
TWI447798B (zh) * | 2010-12-07 | 2014-08-01 | Alpha & Omega Semiconductor Cayman Ltd | 一種在晶圓級封裝的模封程序中避免晶圓破損的方法 |
US8168474B1 (en) | 2011-01-10 | 2012-05-01 | International Business Machines Corporation | Self-dicing chips using through silicon vias |
US8853003B2 (en) | 2011-08-09 | 2014-10-07 | Alpha & Omega Semiconductor, Inc. | Wafer level chip scale package with thick bottom metal exposed and preparation method thereof |
US9230932B2 (en) | 2012-02-09 | 2016-01-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect crack arrestor structure and methods |
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US9515036B2 (en) | 2012-04-20 | 2016-12-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for solder connections |
JP2014007228A (ja) * | 2012-06-22 | 2014-01-16 | Ps4 Luxco S A R L | 半導体装置及びその製造方法 |
US8884443B2 (en) | 2012-07-05 | 2014-11-11 | Advanced Semiconductor Engineering, Inc. | Substrate for semiconductor package and process for manufacturing |
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US9406632B2 (en) | 2012-08-14 | 2016-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package including a substrate with a stepped sidewall structure |
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US8686568B2 (en) | 2012-09-27 | 2014-04-01 | Advanced Semiconductor Engineering, Inc. | Semiconductor package substrates having layered circuit segments, and related methods |
US9318386B2 (en) * | 2013-07-17 | 2016-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer alignment methods in die sawing process |
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US9508623B2 (en) | 2014-06-08 | 2016-11-29 | UTAC Headquarters Pte. Ltd. | Semiconductor packages and methods of packaging semiconductor devices |
JP2016058655A (ja) * | 2014-09-11 | 2016-04-21 | 株式会社ジェイデバイス | 半導体装置の製造方法 |
US9871019B2 (en) | 2015-07-17 | 2018-01-16 | Invensas Corporation | Flipped die stack assemblies with leadframe interconnects |
US9825002B2 (en) | 2015-07-17 | 2017-11-21 | Invensas Corporation | Flipped die stack |
US9490195B1 (en) | 2015-07-17 | 2016-11-08 | Invensas Corporation | Wafer-level flipped die stacks with leadframes or metal foil interconnects |
US9508691B1 (en) | 2015-12-16 | 2016-11-29 | Invensas Corporation | Flipped die stacks with multiple rows of leadframe interconnects |
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KR102072994B1 (ko) | 2017-12-06 | 2020-02-04 | 엘비세미콘 주식회사 | 사이드 몰딩을 이용한 반도체 패키지의 제조방법 |
CN108364917A (zh) * | 2018-02-02 | 2018-08-03 | 华天科技(昆山)电子有限公司 | 半导体封装结构及其封装方法 |
CN111354701A (zh) * | 2018-12-20 | 2020-06-30 | 矽品精密工业股份有限公司 | 电子封装件及其制法 |
US11367657B2 (en) * | 2019-08-01 | 2022-06-21 | Semiconductor Components Industries, Llc | Process of forming an electronic device including a polymer support layer |
JP7430515B2 (ja) * | 2019-11-06 | 2024-02-13 | 株式会社ディスコ | ウエーハの処理方法 |
US12027469B2 (en) | 2021-10-13 | 2024-07-02 | Advanced Semiconductor Engineering, Inc. | Electronic device package and method of manufacturing the same |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS5445570A (en) * | 1977-09-19 | 1979-04-10 | Matsushita Electric Ind Co Ltd | Manufacture for semiconductor element |
JPH0732242B2 (ja) * | 1984-12-24 | 1995-04-10 | 株式会社日立製作所 | 固体撮像装置の製造方法 |
US4904610A (en) * | 1988-01-27 | 1990-02-27 | General Instrument Corporation | Wafer level process for fabricating passivated semiconductor devices |
US5393706A (en) * | 1993-01-07 | 1995-02-28 | Texas Instruments Incorporated | Integrated partial sawing process |
US5445559A (en) * | 1993-06-24 | 1995-08-29 | Texas Instruments Incorporated | Wafer-like processing after sawing DMDs |
US5516728A (en) * | 1994-03-31 | 1996-05-14 | At&T Corp. | Process for fabircating an integrated circuit |
JP3688065B2 (ja) * | 1996-07-26 | 2005-08-24 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
JPH10223571A (ja) * | 1997-02-05 | 1998-08-21 | Matsushita Electron Corp | 半導体装置の製造方法 |
JPH1140520A (ja) * | 1997-07-23 | 1999-02-12 | Toshiba Corp | ウェーハの分割方法及び半導体装置の製造方法 |
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