JP2016058655A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP2016058655A JP2016058655A JP2014185708A JP2014185708A JP2016058655A JP 2016058655 A JP2016058655 A JP 2016058655A JP 2014185708 A JP2014185708 A JP 2014185708A JP 2014185708 A JP2014185708 A JP 2014185708A JP 2016058655 A JP2016058655 A JP 2016058655A
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Abstract
【解決手段】電極が形成された半導体ウエハ101を準備し、半導体チップ105に形成された第一の半導体素子103と半導体ウエハの電極とをバンプ109を介して電気的に接続し、半導体ウエハと半導体チップとの間隙に第一の絶縁樹脂層111を形成し、半導体ウエハ上に、半導体チップが埋まる厚さまで第二の絶縁樹脂層113を形成し、半導体チップが所定の厚みになるまで第二の絶縁樹脂層と半導体チップとを研削し、その上に第一の絶縁層114を形成し、電極104を露出させる開口部を絶縁樹脂層に形成し、導電性の材料で配線117と端子121を形成し、半導体ウエハを所定の厚さに研削した後、素子領域の境界線に沿って個片化する。
【選択図】図8
Description
本発明の第1の実施形態に係る半導体装置の製造方法の概要について図1乃至図8を参照しながら説明する。
本発明の第2の実施形態に係る半導体装置の製造方法の概要について図9乃至図14を参照しながら説明する。第2の実施形態に係る半導体装置の製造方法では、第1の実施形態に係る半導体装置の製造方法とは異なり、半導体ウエハの素子領域毎に形成された第一の半導体素子と、半導体チップに形成された第二の半導体素子とを互いに対向させて、バンプを介して接合する前に、半導体ウエハに形成された複数の素子領域の各々の境界線に沿って、第一の半導体素子が形成されていない半導体ウエハの裏面にダイシング幅よりも広い溝を形成する工程を含む。尚、以下に説明する第2の実施形態に係る半導体装置の製造方法において、第1の実施形態に係る半導体装置の製造方法と重複する説明は省略又は簡略化する。
本発明の第3の実施形態に係る半導体装置の製造方法の概要について図15乃至図18を参照して説明する。第3の実施形態に係る半導体装置の製造方法では、第1及び第2の実施形態に係る半導体装置の製造方法とは異なり、半導体ウエハの素子領域毎に形成された第一の半導体素子と、半導体チップに形成された第二の半導体素子とを半導体ウエハの素子領域毎にバンプを介して電気的に接続する際、半導体ウエハの一つ素子領域に対して複数の半導体チップをバンプ接合する。尚、以下に説明する第3の実施形態に係る半導体装置の製造方法において、第1及び第2の実施形態に係る半導体装置の製造方法と重複する説明は省略又は簡略化する。
本発明の第4の実施形態に係る半導体装置の製造方法の概要について図19乃至図25を参照して説明する。第4の実施形態に係る半導体装置の製造方法では、第1及び第2の実施形態に係る半導体装置の製造方法とは異なり、半導体ウエハの素子領域毎に形成された第一の半導体素子と、半導体チップに形成された第二の半導体素子とをTSV(Through-Silicon Via;シリコン貫通電極)が形成された別の半導体チップを介して接合する。以下に説明する第4の実施形態に係る半導体装置の製造方法において、第1及び第2の実施形態に係る半導体装置の製造方法と重複する説明は省略又は簡略化する。
本発明の第5の実施形態に係る半導体装置の製造方法の概要について図27乃至図33を参照して説明する。第5の実施形態に係る半導体装置の製造方法では、第1乃至第4の実施形態に係る半導体装置の製造方法とは異なり、半導体ウエハとして、第一の半導体素子と第一の半導体素子に一端部が接続しているTSVとが各素子領域に形成されている半導体ウエハを用いる。以下に説明する本発明の第5の実施形態に係る半導体装置の製造方法においては、上述した第2の実施形態に係る半導体装置の製造方法で用いた半導体ウエハにTSVが形成された半導体ウエハを適用した一例を説明する。ここでは、第2の実施形態に係る半導体装置の製造方法と重複する説明は省略又は簡略化する。
101:半導体ウエハ
103:第一の半導体素子
105:半導体チップ
106:第二の半導体素子
107:電極
109:バンプ
111:第一の絶縁樹脂層
113:第二の絶縁樹脂層
114:第一の絶縁層
115:開口部
117:配線
119:配線
121:端子
123:外部端子
Claims (15)
- 電極が形成された半導体ウエハを準備し、半導体チップに形成された第一の半導体素子と前記半導体ウエハの前記電極とをバンプを介して電気的に接続し、
前記半導体ウエハと前記半導体チップとの接続前又は接続後に、互いに対向する前記半導体ウエハと前記半導体チップとの間隙に第一の絶縁樹脂層を形成し、
前記半導体ウエハ上に、前記半導体チップが埋まる厚さまで第二の絶縁樹脂層を形成し、
前記半導体チップが所定の厚みになるまで前記第二の絶縁樹脂層と前記半導体チップとを研削し、
前記第二の絶縁樹脂層上及び前記半導体チップ上に第一の絶縁層を形成し、前記電極を露出させる開口部を前記第一の絶縁層及び前記第二の絶縁樹脂層に形成し、
前記開口部を導電性の材料で埋め、
前記第一の絶縁層上に、前記開口部を埋めた導電性の材料と接続する配線を形成し、
前記配線に電気的に接続する第一の端子を形成し、
前記半導体ウエハを所定の厚さに研削すること、
を含む、半導体装置の製造方法。 - 前記半導体ウエハは、第二の半導体素子が形成された複数の素子領域を有することを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記複数の素子領域の一つに対して、複数の前記半導体チップを接続することを特徴とする請求項2に記載の半導体装置の製造方法。
- 前記半導体ウエハを所定の厚さに研削することは、前記半導体ウエハを仕上がり厚みに達するまで研削することであることを特徴とする請求項1乃至3の何れか一項に記載の半導体装置の製造方法。
- 前記半導体ウエハには、一端部が前記第二の半導体素子に電気的に接続された埋め込み電極が形成されており、
前記第一の端子を形成した後に、前記半導体ウエハを前記埋め込み電極の他端部の手前まで研削し、
前記埋め込み電極の他端部を露出させ、
前記露出させた前記埋め込み電極の他端部に電気的に接続する第二の端子を形成すること、
をさらに含む請求項2乃至4の何れか一項に記載の半導体装置の製造方法。 - 前記電極と前記第一の半導体素子とをバンプ接続する前に、前記素子領域の境界線に沿って、ダイシング幅よりも広い溝を前記半導体ウエハ上に形成すること、
及び、前記半導体ウエハを前記仕上がり厚みに達するまで研削した後に、前記半導体ウエハを個片化すること、
をさらに含み、
前記個片化することは、前記半導体ウエハに形成した前記溝に沿って、前記溝よりも狭いダイシング幅で前記半導体ウエハを個片化することであることを特徴とする請求項4又は5に記載の半導体装置の製造方法。 - 前記溝の深さは、前記仕上がり厚み以上の深さであることを特徴とする請求項6に記載の半導体装置の製造方法。
- 電極が形成された半導体ウエハを準備し、第一の半導体素子が形成され、前記第一の半導体素子と電気的に接続された第一の埋め込み電極を有する第一の半導体チップを準備し、
前記第一の半導体チップの前記第一の半導体素子と前記半導体ウエハの前記電極とを第一のバンプを介して電気的に接続し、
前記半導体ウエハと前記第一の半導体チップとの接続前又は接続後に、互いに対向する前記半導体ウエハと前記第一の半導体チップとの間隙に第一の絶縁樹脂層を形成し、
前記半導体ウエハ上に、前記第一の半導体チップが埋まる厚さまで第二の絶縁樹脂層を形成し、
前記第一の埋め込み電極の他端部の手前まで前記第二の絶縁樹脂層と前記第一の半導体チップとを研削し、
前記第一の埋め込み電極の前記他端部を露出させ、
前記第一の半導体チップ上に前記第一の埋め込み電極の前記他端部を覆う第一の絶縁層を形成し、
前記第一の絶縁層上に前記第一の埋め込み電極の前記他端部とコンタクトホールを介して接続する端子を形成し、
前記端子と第二の半導体チップに形成された第二の半導体素子とを第二のバンプを介して電気的に接続し、
前記端子と前記第二の半導体チップとの接続前又は接続後に、互いに対向する前記端子及び前記第一の絶縁層と前記第二の半導体チップとの間隙に第三の絶縁樹脂層を形成し、
前記第一の絶縁層上に、前記第二の半導体チップが埋まる厚さまで第四の絶縁樹脂層を形成し、
前記第二の半導体チップが所定の厚みになるまで前記第四の絶縁樹脂層と前記第二の半導体チップとを研削し、
前記第四の絶縁樹脂層上及び前記第二の半導体チップ上に第二の絶縁層を形成し、
前記半導体ウエハに形成された前記電極を露出させる開口部を前記第二の絶縁層、前記第四の絶縁樹脂層、前記第一の絶縁層及び前記第二の絶縁樹脂層に形成し、
前記開口部を導電性の材料で埋め、
前記第二の絶縁層上に、前記開口部を埋めた導電性の材料と接続する配線を形成し、
前記配線と電気的に接続する第一の端子を形成し、
前記半導体ウエハを所定の厚さに研削すること、
を含む、半導体装置の製造方法。 - 前記半導体ウエハは、第三の半導体素子が形成された複数の素子領域を有することを特徴とする請求項8に記載の半導体装置の製造方法。
- 前記複数の素子領域の一つに対して、複数の前記第一の半導体チップを接続することを特徴とする請求項9に記載の半導体装置の製造方法。
- 前記半導体ウエハの一つの素子領域に形成された前記電極と少なくとも一つの第三の半導体チップに形成された第四の半導体素子とを前記第一のバンプを介して電気的に接続すること、をさらに含む請求項10に記載の半導体装置の製造方法。
- 前記半導体ウエハを所定の厚さに研削することは、前記半導体ウエハを仕上がり厚みに達するまで研削することであることを特徴とする請求項8乃至11のいずれか一項に記載の半導体装置の製造方法。
- 前記半導体ウエハには、一端部が前記第三の半導体素子に電気的に接続された第二の埋め込み電極が形成されており、
前記第一の端子を形成した後に、前記半導体ウエハを前記第二の埋め込み電極の他端部の手前まで研削し、
前記第二の埋め込み電極の他端部を露出させ、
前記露出させた前記第二の埋め込み電極の他端部に電気的に接続する第二の端子を形成すること、
をさらに含む請求項9乃至12のいずれか一項に記載の半導体装置の製造方法。 - 前記電極と前記第一の埋め込み電極の一端部とをバンプ接続する前に、前記素子領域の境界線に沿って、ダイシング幅よりも広い溝を前記半導体ウエハ上に形成すること、
及び、前記半導体ウエハを前記仕上がり厚みに達するまで研削した後に、前記半導体ウエハを個片化すること、
をさらに含み、
前記個片化することは、前記半導体ウエハに形成した前記溝に沿って、前記溝よりも狭いダイシング幅で前記半導体ウエハを個片化することであることを特徴とする請求項12又は13に記載の半導体装置の製造方法。 - 前記溝の深さは、前記仕上がり厚み以上の深さであることを特徴とする請求項14に記載の半導体装置の製造方法。
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US9368474B2 (en) | 2016-06-14 |
US20160079204A1 (en) | 2016-03-17 |
CN110517964B (zh) | 2024-04-30 |
TW201611186A (zh) | 2016-03-16 |
TW202425105A (zh) | 2024-06-16 |
CN105428265A (zh) | 2016-03-23 |
KR20160030861A (ko) | 2016-03-21 |
TWI694548B (zh) | 2020-05-21 |
TW202213677A (zh) | 2022-04-01 |
TWI751530B (zh) | 2022-01-01 |
KR102620629B1 (ko) | 2024-01-02 |
TW202029412A (zh) | 2020-08-01 |
KR102450822B1 (ko) | 2022-10-05 |
CN110517964A (zh) | 2019-11-29 |
CN105428265B (zh) | 2019-09-06 |
TWI836302B (zh) | 2024-03-21 |
KR20220137853A (ko) | 2022-10-12 |
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