JP2021048205A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP2021048205A
JP2021048205A JP2019168888A JP2019168888A JP2021048205A JP 2021048205 A JP2021048205 A JP 2021048205A JP 2019168888 A JP2019168888 A JP 2019168888A JP 2019168888 A JP2019168888 A JP 2019168888A JP 2021048205 A JP2021048205 A JP 2021048205A
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Prior art keywords
resin film
conductive resin
groove
semiconductor
semiconductor device
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JP2019168888A
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English (en)
Inventor
章 友野
Akira Tomono
章 友野
圭介 徳渕
Keisuke Tokubuchi
圭介 徳渕
天頌 大野
Takanobu Ono
天頌 大野
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Kioxia Corp
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Kioxia Corp
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Priority to JP2019168888A priority Critical patent/JP2021048205A/ja
Priority to CN202010042238.6A priority patent/CN112530816B/zh
Priority to TW109101376A priority patent/TWI740350B/zh
Priority to US16/809,649 priority patent/US11309219B2/en
Publication of JP2021048205A publication Critical patent/JP2021048205A/ja
Pending legal-status Critical Current

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Abstract

【課題】ＮＣＦを用いた半導体チップの実装方法において、半導体チップの実装強度を向上させることを可能にした半導体装置の製造方法を提供する。【解決手段】実施形態の半導体装置の製造方法は、柱状電極２を有する複数のチップ領域とダイシング領域とを備える半導体ウェハ１にダイシングテープ４を貼り付ける工程と、ダイシング領域に沿って第１の溝５を形成し、ダイシングテープ４でウェハ形状を維持しつつ、複数のチップ領域を個片化する工程と、複数の半導体チップ７上に非導電性樹脂フィルム８を貼り付けると共に、非導電性樹脂フィルム８の一部を第１の溝５内に充填する工程と、第１の溝５内に充填された非導電性樹脂フィルム８に第１の溝５の幅より狭い幅を有する第２の溝９を形成する工程と、非導電性樹脂フィルム８を有する複数の半導体チップ７をピックアップして基板１３に実装する工程とを具備する。【選択図】図２

Description

本発明の実施形態は、半導体装置の製造方法に関する。
半導体チップを回路基板等の基板に実装する方法としては、例えば熱可塑性の非導電性樹脂フィルム（Ｎｏｎ Ｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ：ＮＣＦ）を用いた実装方法が知られている。従来のＮＣＦを用いた実装方法では、まず個片化された複数の半導体チップの電極形成面上にＮＣＦを貼り付けた後、ＮＦＣを個片化された複数の半導体チップに対応させて切断する。次いで、個片化されたＮＦＣを有する半導体チップを基板上にＮＦＣを介して接合し、半導体チップの電極と基板の電極とを接続する。このような従来のＮＣＦを用いた実装方法では、十分な半導体チップの接合強度が得られないおそれがあり、例えば熱が印加された際の基板の収縮により半導体チップの剥がれが生じやすい。
特開２０１１−１２９７７９号公報 特許第５４７４６３０号公報
本発明が解決しようとする課題は、ＮＣＦを用いた半導体チップの実装方法において、半導体チップの実装強度を向上させることを可能にした半導体装置の製造方法を提供することにある。
実施形態の半導体装置の製造方法は、柱状電極をそれぞれ有する複数のチップ領域と、前記複数のチップ領域を区画するダイシング領域とを備える半導体ウェハの、前記柱状電極を有する第１の表面とは反対側の第２の表面に、ダイシングテープを貼り付ける工程と、前記半導体ウェハの前記第１の表面側から前記ダイシング領域に沿って第１の溝を形成し、前記ダイシングテープで前記半導体ウェハのウェハ形状を維持しつつ、前記複数のチップ領域を個片化して複数の半導体チップを形成する工程と、前記個片化された複数の半導体チップ上に、前記半導体ウェハの第１の表面側から非導電性樹脂フィルムを貼り付けると共に、前記非導電性樹脂フィルムの一部を前記第１の溝内に充填する工程と、前記第１の溝内に充填された前記非導電性樹脂フィルムに、前記非導電性樹脂フィルムを前記個片化された半導体チップの側面に残しつつ、前記第１の溝の幅より狭い幅を有する第２の溝を形成することにより、前記非導電性樹脂フィルムを前記複数の半導体チップに応じて分割する工程と、前記分割された非導電性樹脂フィルムを有する前記複数の半導体チップをピックアップし、前記ピックアップされた前記半導体チップの前記柱状電極を基板の電極に接合しつつ、前記非導電性樹脂フィルムを介して前記半導体チップを前記基板に実装する工程とを具備する。
実施形態による半導体装置の製造方法を示す断面図である。 実施形態による半導体装置の製造方法を示す断面図である。 図１に示す半導体装置の製造方法における非導電性フィルムの貼り付け工程及び充填工程を示す断面図である。 図２に示す半導体装置の製造方法における非導電性フィルムの分割工程の第１の例を示す断面図である。 図２に示す半導体装置の製造方法における非導電性フィルムの分割工程の第２の例を示す断面図である。 図２に示す半導体装置の製造方法における非導電性フィルムの分割工程の第３の例を示す断面図である。 実施形態の半導体装置の製造方法により得られる半導体装置の第１の例を示す断面図である。 実施形態の半導体装置の製造方法により得られる半導体装置の第２の例を示す断面図である。 実施形態の半導体装置の製造方法により得られる半導体装置の第３の例を示す断面図である。 実施形態の半導体装置の製造方法により得られる半導体装置を使用した半導体記憶装置を示す断面図である。
以下、実施形態の半導体装置の製造方法について、図面を参照して説明する。図１及び図２は実施形態による半導体装置の製造方法を示す図であって、図１は半導体ウェハの準備工程から非導電性フィルムの貼り付け及び充填工程までを示す断面図、図２は非導電性フィルムの分割工程から半導体装置の実装工程までを示す断面図である。なお、各実施形態において、実質的に同一の構成部位には同一の符号を付し、その説明を一部省略する場合がある。図面は模式的なものであり、厚さと平面寸法との関係、各部の厚さの比率等は現実のものとは異なる場合がある。説明中の上下等の方向を示す用語は、特に明記が無い場合には後述する半導体ウェハの柱状電極の形成面を上とした場合の相対的な方向を示し、重力加速度方向を基準とした現実の方向とは異なる場合がある。
まず、図１（ａ）に示すように、半導体ウェハ１を用意する。半導体ウェハ１は、それぞれ柱状電極（バンプ電極）２を有する複数のチップ領域Ｘと、これら複数のチップ領域Ｘを区画するダイシング領域Ｄとを有している。このような半導体ウェハ１の柱状電極２を有する第１の表面１ａ上に表面保護テープ３を貼り付ける。次いで、半導体ウェハ１の第１の表面１ａとは反対側の第２の表面１ｂを、製造する半導体チップに応じた厚さまで研削した後、表面保護テープ３を剥離する（図１（ｂ））。なお、表面保護テープ３の剥離工程は、下記に示すダイシングテープ４の貼り付け工程後に実施される場合もある。
次に、図１（ｃ）に示すように、半導体ウェハ１の研削された第２の表面１ｂに、ダイシングテープ４を貼り付ける。図示を省略したが、ダイシングテープ４の外周部はウェハリングにより支持されている。次いで、図１（ｄ）に示すように、半導体ウェハ１に第１の表面１ａ側からダイシング領域Ｄに沿って第１の溝５を形成する。第１の溝５は、例えばダイヤモンドブレードのようなダイシングブレード６を用いたダイシング工程により形成される。この際、ダイシング工程は半導体ウェハ１を切断すると共に、ダイシングテープ４の厚さ方向の一部のみを切断するハーフカット状態となるように実施する。これによって、複数のチップ領域Ｘを個片化して複数の半導体チップ７を形成しつつ、半導体ウェハ１の全体形状をダイシングテープ４により維持する。第１の溝５は複数のチップ領域Ｘがそれぞれ所望の半導体チップの形状となる第１の幅で形成される。
次に、図１（ｅ）に示すように、個片化された複数の半導体チップ７上に、半導体ウェハ１の第１の表面１ａ側から熱可塑性の非導電性樹脂フィルム（ＮＣＦ）８を貼り付ける。この際、ＮＣＦ８の一部を第１の溝５内に充填する。ＮＣＦ８の第１の溝５内への充填工程には、各種の方法を適用することができる。例えば、図３に示す減圧下での貼付け工程と大気圧下での充填工程を適用することができる。すなわち、図３（ａ）に示すように、減圧下において複数の半導体チップ７上に６００℃程度の加熱条件下でＮＣＦ８を貼り付ける。次いで、図３（ｂ）に示すように、減圧下で貼り付けたＮＣＦ８を大気開放することによって、ＮＣＦ８の一部を第１の溝５内に充填する。
この際、ＮＣＦ８の大気開放に加えて、ＮＣＦ８の加熱、例えば第１の溝５に相当する部分への部分加熱を併用してもよい。部分加熱は、例えば熱風やレーザ等を用いて実施される。部分加熱は、第１の溝５内に空孔等が残存しないように、中心から外側に向けて実施することが好ましい。また、ヒータやオーブン等を用いて、ＮＣＦ８全体を加熱するようにしてもよい。全体加熱を適用する場合、加圧しつつ加熱することも有効である。ＮＣＦ８の加熱を併用することによって、ＮＣＦ８の第１の溝５内への充填性を高めることができる。さらに、ＮＣＦ８の材質等によっては、ＮＣＦ８の減圧下での貼付け工程を適用することなく、ＮＣＦ８の加熱（部分加熱又は全体加熱）のみによって、ＮＣＦ８を第１の溝５内に充填することができる場合もある。
次に、図２（ａ）に示すように、第１の溝５内に充填されたＮＣＦ８に第２の溝９を形成し、ＮＣＦ８を複数の半導体チップ７に応じて分割する。この際、第２の溝９はその幅が第１の溝５の幅より狭くなるように形成する。これによって、第１の溝５を介して配置された２つの半導体チップ７の側面には、それぞれＮＣＦ８が残存することになる。半導体チップ７の側面に残存させたＮＣＦ８は、後述するように半導体チップ７を基板に実装した際にフィレットの形成に寄与し、これにより半導体チップ７の実装強度を高めることが可能になる。第２の溝９の幅は、２つの半導体チップ７の側面にそれぞれ５μｍ以上のＮＣＦ８が残存するように調整することが好ましい。例えば、第１の溝５の幅が３５〜４０μｍ程度とした場合、２つの半導体チップ７の側面にそれぞれ５μｍ以上のＮＣＦ８が残存するように、第２の溝９の幅は２５〜３０μｍ程度とすることが好ましく、また２つの半導体チップ７の側面に１０μｍ程度のＮＣＦ８を残存させる場合には、第２の溝９の幅は１５〜２０μｍ程度とすることが好ましい。
第２の溝９の形成工程には、各種の方法を適用することができる。例えば、図４に示すように、第１の溝５の形成に用いた第１のダイシングブレード６の幅より狭い幅を有する第２のダイシングブレード１０を用いて、第１の溝５内に充填されたＮＣＦ８を切断する。これによって、第１の溝５内に充填されたＮＣＦ８に第２の溝９を形成することができる。また、図５（ａ）に示すように、第１の溝５に形成されたＮＣＦ８にレーザ１１を照射して切断する。次いで、図５（ｂ）に示すように、複数の半導体チップ７が貼り付けられたダイシングテープ４を、その面方向にエキスパンド（延伸）することにより第２の溝９を形成する。レーザダイシングではＮＣＦ８が部分的に固着している部分が残存するおそれがあるため、ダイシングテープ４のエキスパンド工程を実施することが好ましい。
また、図６に示すように、ダイシングテープ４の材質等によっては、レーザダイシング工程を省き、エキスパンド工程のみで第２の溝９を形成することができる場合もある。その場合、減圧下で貼り付けたＮＣＦ８を大気開放し、ＮＣＦ８の一部を第１の溝５内に充填した後、ダイシングテープ４をその面方向にエキスパンド（延伸）し、第１の溝５内に充填されたＮＣＦ８を分割して第２の溝９を形成する。ただし、エキスパンド工程のみでは第２の溝９の形成位置にばらつきが生じ、半導体チップ７の側面に残存させるＮＣＦ８の厚さがばらつくおそれがあるため、レーザダイシング工程を併用することが好ましい。また、エキスパンド工程はブレードダイシング後に併用してもよい。
第１の溝５内に充填されたＮＣＦ８に第２の溝９を形成し、ＮＣＦ８を複数の半導体チップ７に応じて分割することによって、個片化されたＮＣＦ８を有する半導体チップ７が形成される。このようなＮＣＦ８を有する半導体チップ７を、図２（ｂ）に示すように、ダイシングテープ４からピックアップする。次に、ダイシングテープ４からピックアップされたＮＣＦ８を有する半導体チップ７を、実装工程の途中で上下反転させた後、図２（ｃ）に示すように、電極１２を有する基板１３に実装して半導体装置１５を作製する。半導体チップ７は、その柱状電極２を基板１３の電極１２に接続しつつ、基板１３に実装され、これにより半導体装置１５が作製される。
半導体チップ７の実装は、例えば以下のようにして実施される。まず、半導体チップ７の第２の面１ｂを図示しない実装ツールで保持し、半導体チップ７の柱状電極２が基板１３の電極１２に接触するように、半導体チップ７を基板１３に押し当てる。この状態で、加熱しながら加圧することによって、柱状電極２と電極１２とを接合しつつ、半導体チップ７を基板１３に実装する。ＮＣＦ８は半導体チップ７の基板１３への接着剤として機能すると共に、半導体チップ７と基板１３との間のアンダーフィル材として機能する。ＮＣＦ８は実装時の加熱により軟化し、その後の冷却工程で固化して、接着剤及びアンダーフィル材として機能する。この際、半導体チップ７の側面にもＮＣＦ８が存在しているため、基板１３に実装された半導体チップ７の側面にＮＣＦ８によるフィレット１４が形成される。従って、大型化されたフィレット１４により半導体チップ７の基板１３に対する実装強度や応力緩和効果等を高めることができる。
ここで、半導体チップ７の側面にＮＣＦ８が存在していない場合、半導体チップ７と基板１３との間に余分に存在するＮＣＦ８が、実装時の加圧工程で半導体チップ７の側面を這い上がることによって、半導体チップ７の側面にＮＣＦ８によるフィレットが形成される場合もあるが、その量は僅かであるため、十分なフィレットを形成することはできない。このような点に対して、実施形態の製造方法では半導体チップ７の側面にもＮＣＦ８を存在させているため、この側面のＮＣＦ８が半導体チップ７の側面へのフィレット１４の形成を促進すると共に、フィレット１４の大型化に寄与する。すなわち、基板１３に実装された半導体チップ７の側面に、十分な量のＮＣＦ８で大型のフィレット１４を形成することができる。さらに、半導体チップ７の側面をフィレット１４で保護することができる。フィレット１４は半導体チップ７の基板１３に対する接合強度を向上させると共に、応力緩和効果を高めるため、例えば熱が印加された際に基板１３に収縮が生じたような場合においても、半導体チップ７の剥がれを抑制することができる。従って、信頼性や耐熱性等に優れる半導体装置１を提供することが可能になる。
実施形態の製造方法により得られる半導体装置１５において、半導体チップ７の側面のＮＣＦ８は第１の溝５内にまで存在しているため、ＮＣＦ８により形成されるフィレット１４は図７に示すように、上部が半導体チップ７の上方にまで突出する場合がある。このような形状のフィレット１４であってもよいが、半導体チップ７の実装ツールを工夫することにより各種形状のフィレット１４を有する半導体装置１５を得ることができる。例えば、半導体チップ７の平面形状より大きい実装ツールで半導体チップ７を保持して基板１３に押し付けることによって、図８に示すように、ＮＣＦ８によるフィレット１４の上面を半導体チップ７の裏面と同一面とすることができる。半導体チップ７の上に他の半導体装置等を搭載する場合には、図８に示すような形状のフィレット１４が効果的である。
また、半導体チップ７の平面形状より小さい実装ツールで半導体チップ７を保持して基板１３に押し付けた場合、図９に示すように、半導体チップ７の上方に突出したフィレット１４の上部が実装時の加熱で半導体チップ７の裏面の外周側の一部を覆うような形状とすることができる。図９に示すような形状を有するフィレット１４は、半導体チップ７の基板１３に対する接合強度をより一層向上させるため、半導体装置１の信頼性や耐熱性等をさらに向上させることが可能になる。フィレット１４の形状は、半導体装置１５の使用用途や求められる特性に応じて選択することができる。
上述した実施形態の製造方法により作製した半導体装置１５は、そのままで利用することもできるし、あるいは他の半導体装置の一部として使用することもできる。図１０は半導体装置１５をより機能化した半導体装置、例えば半導体記憶装置の一部として使用した例を示す図である。図１０に示す半導体記憶装置２１は、基板２２上に設けられた半導体装置１５を有している。半導体装置１５において、半導体チップ７の電極２は基板２２の電極２３と接続されており、その状態で基板２２に実装されている。半導体チップ７は、例えばコントローラチップとして機能するものである。半導体装置１５の周囲にはスペーサ２４、例えばシリコンスペーサが配置されている。スペーサ２４はＤＡＦ（Ｄｉｅ Ａｔｔａｃｈ Ｆｉｌｍ）２５により基板２２に接着されている。
半導体チップ７及びスペーサ２４上には、第１のメモリチップ２６及び第２のメモリチップ２７が配置されている。第１のメモリチップ２６はＤＡＦ２５により半導体チップ７及びスペーサ２４に接着されており、第２のメモリチップ２７はＤＡＦ２５により第１のメモリチップ２６に接着されている。第２のメモリチップ２７は、第１のメモリチップ２６の電極２８が露出するように、第１のメモリチップ２６上に階段上に積層されている。第２のメモリチップ２７の電極２９は、第１のメモリチップ２６の電極２８とボンディングワイヤ３０により電気的に接続されており、第１のメモリチップ２６の電極２８は基板２２の電極３１とボンディングワイヤ３０により電気的に接続されている。基板２１上には各構成要素を封止するようにモールド樹脂３２が形成されている。このような半導体記憶装置２１におけるコントローラチップ（７）の実装に、実施形態の半導体装置の製造方法は有効に利用されるものである。
なお、本発明のいくつかの実施形態を説明したが、これらの実施形態は例として提示したものであり、発明の範囲を限定することは意図していない。これら実施形態は、その他の様々な形態で実施し得るものであり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれると同時に、特許請求の範囲に記載された発明とその均等の範囲に含まれる。
１…半導体ウェハ、２…柱状電極、４…ダイシングテープ、５…第１の溝、６…第１のダイシングブレード、７…半導体チップ、８…非導電性樹脂フィルム、９…第２の溝、１０…第２のダイシングブレード、１１…レーザ、１２…電極、１３…基板、１４…フィレット、１５…半導体装置、Ｘ…チップ領域、Ｄ…ダイシング領域。

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  1. 柱状電極をそれぞれ有する複数のチップ領域と、前記複数のチップ領域を区画するダイシング領域とを備える半導体ウェハの、前記柱状電極を有する第１の表面とは反対側の第２の表面に、ダイシングテープを貼り付ける工程と、
    前記半導体ウェハの前記第１の表面側から前記ダイシング領域に沿って第１の溝を形成し、前記ダイシングテープで前記半導体ウェハのウェハ形状を維持しつつ、前記複数のチップ領域を個片化して複数の半導体チップを形成する工程と、
    前記個片化された複数の半導体チップ上に、前記半導体ウェハの第１の表面側から非導電性樹脂フィルムを貼り付けると共に、前記非導電性樹脂フィルムの一部を前記第１の溝内に充填する工程と、
    前記第１の溝内に充填された前記非導電性樹脂フィルムに、前記非導電性樹脂フィルムを前記個片化された半導体チップの側面に残しつつ、前記第１の溝の幅より狭い幅を有する第２の溝を形成することにより、前記非導電性樹脂フィルムを前記複数の半導体チップに応じて分割する工程と、
    前記分割された非導電性樹脂フィルムを有する前記複数の半導体チップをピックアップし、前記ピックアップされた前記半導体チップの前記柱状電極を基板の電極に接合しつつ、前記非導電性樹脂フィルムを介して前記半導体チップを前記基板に実装する工程と
    を具備する半導体装置の製造方法。
  2. 前記非導電性樹脂フィルムの貼り付け及び充填工程は、減圧下で前記非導電性樹脂フィルムを前記複数の半導体チップに貼り付ける工程と、前記非導電性樹脂フィルムが貼り付けられた前記複数の半導体チップを大気開放し、前記非導電性樹脂フィルムの一部を前記第１の溝内に充填する工程とを具備する、請求項１に記載の半導体装置の製造方法。
  3. さらに、前記大気開放された前記非導電性樹脂フィルムの少なくとも前記第１の溝に相当する部分を加熱する工程を具備する、請求項２に記載の半導体装置の製造方法。
  4. 前記非導電性樹脂フィルムの貼り付け及び充填工程は、前記非導電性樹脂フィルムを前記複数の半導体チップに貼り付ける工程と、前記複数の半導体チップに貼り付けられた前記非導電性樹脂フィルムの少なくとも前記第１の溝に相当する部分を加熱し、前記非導電性樹脂フィルムの一部を前記第１の溝内に充填する工程とを具備する、請求項１に記載の半導体装置の製造方法。
  5. 前記非導電性樹脂フィルムの分割工程は、前記第１の溝の幅より狭い幅を有するブレードで前記第１の溝内に充填された前記非導電性樹脂フィルムを切断する工程を具備する、請求項１ないし請求項４のいずれか１項に記載の半導体装置の製造方法。
  6. 前記非導電性樹脂フィルムの分割工程は、さらに前記ブレードで切断された前記非導電性樹脂フィルムを、その面方向に延伸する工程を具備する、請求項５に記載の半導体装置の製造方法。
  7. 前記非導電性樹脂フィルムの分割工程は、前記第１の溝内に充填された前記非導電性樹脂フィルムをレーザで溶断する工程を具備する、請求項１ないし請求項４のいずれか１項に記載の半導体装置の製造方法。
  8. 前記非導電性樹脂フィルムの分割工程は、さらに前記レーザで溶断された前記非導電性樹脂フィルムを、その面方向に延伸する工程を具備する、請求項７に記載の半導体装置の製造方法。
  9. 前記非導電性樹脂フィルムの分割工程は、前記非導電性樹脂フィルムを、その面方向に延伸して前記非導電性樹脂フィルムを分割する工程を具備する、請求項１ないし請求項４のいずれか１項に記載の半導体装置の製造方法。
  10. 前記基板に実装された前記半導体チップの側面に、前記非導電性樹脂フィルムによりフィレットを形成する、請求項１ないし請求項９のいずれか１項に記載の半導体装置の製造方法。
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