TWI740350B - 半導體裝置之製造方法 - Google Patents

半導體裝置之製造方法 Download PDF

Info

Publication number
TWI740350B
TWI740350B TW109101376A TW109101376A TWI740350B TW I740350 B TWI740350 B TW I740350B TW 109101376 A TW109101376 A TW 109101376A TW 109101376 A TW109101376 A TW 109101376A TW I740350 B TWI740350 B TW I740350B
Authority
TW
Taiwan
Prior art keywords
resin film
conductive resin
semiconductor
semiconductor wafer
manufacturing
Prior art date
Application number
TW109101376A
Other languages
English (en)
Other versions
TW202113937A (zh
Inventor
友野章
徳渕圭介
大野天頌
Original Assignee
日商鎧俠股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商鎧俠股份有限公司 filed Critical 日商鎧俠股份有限公司
Publication of TW202113937A publication Critical patent/TW202113937A/zh
Application granted granted Critical
Publication of TWI740350B publication Critical patent/TWI740350B/zh

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836Wafer tapes, e.g. grinding or dicing support tapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/60022Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68336Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding involving stretching of the auxiliary support post dicing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/1308Plural core members being stacked
    • H01L2224/13082Two-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/274Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2743Manufacturing methods by blanket deposition of the material of the layer connector in solid form
    • H01L2224/27436Lamination of a preform, e.g. foil, sheet or layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/278Post-treatment of the layer connector
    • H01L2224/2783Reworking, e.g. shaping
    • H01L2224/2784Reworking, e.g. shaping involving a mechanical process, e.g. planarising the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29005Structure
    • H01L2224/29006Layer connector larger than the underlying bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/2901Shape
    • H01L2224/29016Shape in side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/2901Shape
    • H01L2224/29016Shape in side view
    • H01L2224/29018Shape in side view comprising protrusions or indentations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201Structure
    • H01L2224/32012Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32013Structure relative to the bonding area, e.g. bond pad the layer connector being larger than the bonding area, e.g. bond pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205Shape
    • H01L2224/32057Shape in side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205Shape
    • H01L2224/32057Shape in side view
    • H01L2224/32058Shape in side view being non uniform along the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205Shape
    • H01L2224/32057Shape in side view
    • H01L2224/32059Shape in side view comprising protrusions or indentations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731Location prior to the connecting process
    • H01L2224/73101Location prior to the connecting process on the same surface
    • H01L2224/73103Bump and layer connectors
    • H01L2224/73104Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81191Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/81201Compression bonding
    • H01L2224/81203Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832Applying energy for connecting
    • H01L2224/83201Compression bonding
    • H01L2224/83203Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862Heat curing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06506Wire or wire-like electrical connections between devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/0651Wire or wire-like electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06517Bump or bump-like direct electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06575Auxiliary carrier between devices, the carrier having no electrical connection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161Exposing the passive side of the semiconductor or solid-state body of a flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Laser Beam Processing (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

根據一個實施形態,實施形態之半導體裝置之製造方法具備如下步驟:將具備分別具有柱狀電極之複數個晶片區域及切割區域之半導體晶圓沿著切割區域分割,將複數個晶片區域單片化;於經單片化之複數個半導體晶片上貼附非導電性樹脂膜,並且將非導電性樹脂膜之一部分填充至相鄰之複數個半導體晶片間之間隙;於填充至間隙內之非導電性樹脂膜形成具有較間隙之寬度窄之寬度之槽;以及將具有非導電性樹脂膜之複數個半導體晶片依次拾取並安裝於基板。

Description

半導體裝置之製造方法
此處所揭示之實施形態係關於一種半導體裝置之製造方法。
作為將半導體晶片安裝於電路基板等基板之方法,例如,已知有使用熱塑性之非導電性樹脂膜(Non Conductive Film:NCF)之安裝方法。於使用NCF之安裝方法中,首先,於將NCF貼附於經單片化之複數個半導體晶片之電極形成面上之後,將NFC與經單片化之複數個半導體晶片對應地切斷。接著,將具有經單片化之NFC之半導體晶片隔著NFC而接合於基板上,將半導體晶片之電極與基板之電極連接。於此種使用NCF之安裝方法中,有無法獲得充分之半導體晶片之接合強度之擔心,例如,由於施加熱時之基板之收縮而容易產生半導體晶片之剝離。
實施形態之半導體裝置之製造方法具備如下步驟:將具備分別具有柱狀電極之複數個晶片區域、及劃分上述複數個晶片區域之切割區域之半導體晶圓沿著上述切割區域分割,將上述複數個晶片區域單片化而形成複數個半導體晶片;於上述經單片化之複數個半導體晶片上,自上述半導體晶圓之第1表面側貼附非導電性樹脂膜,並且將上述非導電性樹脂膜之一部分填充至相鄰之上述複數個半導體晶片間之間隙;於填充至上述間隙內之上述非導電性樹脂膜,使上述非導電性樹脂膜殘留於上述經單片化之半導體晶片之側面,且形成具有較上述間隙之寬度窄之寬度之槽,藉此根據上述複數個半導體晶片分割上述非導電性樹脂膜;以及依次拾取具有上述經分割之非導電性樹脂膜之上述複數個半導體晶片,並將上述拾取之上述半導體晶片之上述柱狀電極接合於基板之電極,且隔著上述非導電性樹脂膜而將上述半導體晶片安裝於上述基板。
以下,參照圖式對實施形態之半導體裝置之製造方法進行說明。再者,於各實施形態中,存在對實質上相同之構成部位標註相同之符號,而將其說明省略一部分之情況。圖式係模式性之圖,存在厚度與平面尺寸之關係、各部之厚度之比率等與實物不同之情況。存在表示說明中之上下等方向之用語於無特別明記之情形時表示以下述半導體晶圓之柱狀電極之形成面為上時之相對性之方向,與以重力加速度方向為基準之現實之方向不同之情況。
(第1實施形態) 圖1A至圖1E及圖2A至圖2C係表示第1實施形態之半導體裝置之製造方法之圖。圖1A至圖1E係表示自半導體晶圓之準備步驟至非導電性膜之貼附及填充步驟為止之剖視圖,圖2A至圖2C係表示自非導電性膜之分割步驟至半導體裝置之安裝步驟為止之剖視圖。
首先,如圖1A所示,準備半導體晶圓1。半導體晶圓1具有分別具有柱狀電極(凸塊電極)2之複數個晶片區域X、及劃分該等複數個晶片區域X之切割區域D。又,未圖示之半導體元件設置於形成有柱狀電極2之面。於此種半導體晶圓1之具有柱狀電極2之第1表面1a上貼附表面保護帶3。接著,將半導體晶圓1之與第1表面1a相反側之第2表面1b研削至與所製造之半導體晶片對應之厚度為止之後,將表面保護帶3剝離(圖1B)。亦存在表面保護帶3之剝離步驟於下述所示之切割帶4之貼附步驟後實施之情況。
接下來,如圖1C所示,於半導體晶圓1之被研削之第2表面1b貼附切割帶4。雖然省略了圖示,但切割帶4之外周部由晶圓環支持。接著,如圖1D所示,於半導體晶圓1自第1表面1a側沿著切割區域D形成第1槽5,而將半導體晶圓1分割。第1槽5例如利用使用如金剛石刀片般之切割刀片6之切割步驟來形成。此時,切割步驟以將半導體晶圓1切斷,並且僅將切割帶4之厚度方向之一部分切斷之半切狀態之方式實施。藉由利用第1槽5於相鄰之複數個晶片區域X間形成間隙,來將複數個晶片區域X單片化而形成複數個半導體晶片7。具有經單片化之半導體晶片7之半導體晶圓1之整體形狀由切割帶4來維持。第1槽5由複數個晶片區域X分別成為所期望之半導體晶片之形狀之第1寬度(間隙)形成。
接下來,如圖1E所示,於經單片化之複數個半導體晶片7上,自半導體晶圓1之第1表面1a側貼附熱塑性之非導電性樹脂膜(NCF)8。此時,將NCF8之一部分填充至第1槽5內。NCF8向第1槽5內之填充步驟能夠應用各種方法。例如,能夠應用圖3A及圖3B所示之減壓下之貼附步驟與大氣壓下之填充步驟。即,如圖3A所示,減壓下於複數個半導體晶片7上以60℃左右之加熱條件貼附NCF8。接著,如圖3B所示,藉由將減壓下貼附之NCF8大氣開放,來將NCF8之一部分填充至第1槽5內。
此時,除了NCF8之大氣開放以外,亦可一併使用NCF8之加熱,例如向相當於第1槽5之部分之局部加熱。局部加熱例如使用熱風或雷射等來實施。局部加熱較佳為自中心朝向外側實施以使第1槽5內不會殘存孔隙等。又,亦可使用加熱器或烘箱等,將NCF8整體加熱。於應用整體加熱之情形時,亦有效的是一面加壓一面加熱。藉由一併使用NCF8之加熱,能夠提高NCF8向第1槽5內之填充性。進而,亦存在如下情況:根據NCF8之材質等,不應用NCF8之減壓下之貼附步驟,而僅利用NCF8之加熱(局部加熱或整體加熱)將NCF8填充至第1槽5內。
接下來,如圖2A所示,於填充至第1槽5內之NCF8形成第2槽9,並根據複數個半導體晶片7來分割NCF8。此時,第2槽9以其寬度較第1槽5之寬度窄之方式形成。藉此,於隔著第1槽5而配置之2個半導體晶片7之側面分別殘存NCF8。如下所述,殘存在半導體晶片7之側面之NCF8有助於在將半導體晶片7安裝至基板時覆蓋半導體晶片7之側面之樹脂膜即內圓角(fillet)之形成,藉此能夠提高半導體晶片7之安裝強度。第2槽9之寬度較佳為以於2個半導體晶片7之側面分別殘存5 μm以上之NCF8之方式調整。例如,於第1槽5之寬度為35~40 μm左右之情形時,為了於2個半導體晶片7之側面分別殘存5 μm以上之NCF8,第2槽9之寬度較佳設為25~30 μm左右,又,當使10 μm左右之NCF8殘存在2個半導體晶片7之側面時,第2槽9之寬度較佳設為15~20 μm左右。
第2槽9之形成步驟能夠應用各種方法。例如,如圖4所示,使用具有較第1槽5之形成所使用之第1切割刀片6之寬度窄之寬度之第2切割刀片10,將填充至第1槽5內之NCF8切斷。藉此,能夠於填充至第1槽5內之NCF8形成第2槽9。又,如圖5A所示,對形成於第1槽5之NCF8照射雷射光11而進行切斷。接下來,如圖5B所示,藉由將貼附有複數個半導體晶片7之切割帶4於其面方向擴張(延伸)來形成第2槽9。於雷射切割中有可能會殘存NCF8局部地固著之部分,因此較佳為實施切割帶4之擴張步驟。
如圖6所示,亦存在根據切割帶4之材質等,省去雷射切割步驟,能夠僅利用擴張步驟形成第2槽9之情況。於該情形時,將減壓下貼附之NCF8大氣開放,並將NCF8之一部分填充至第1槽5內之後,切割帶4於其面方向擴張(延伸),將填充至第1槽5內之NCF8分割而形成第2槽9。但是,由於僅利用擴張步驟而有於第2槽9之形成位置產生不均,且殘存在半導體晶片7之側面之NCF8之厚度不均之虞,故而較佳為一併使用雷射切割步驟。擴張步驟亦可於刀片切割後一併使用。
藉由於填充至第1槽5內之NCF8形成第2槽9,並根據複數個半導體晶片7分割NCF8,來形成具有經單片化之NCF8之半導體晶片7。如圖2B所示自切割帶4依次拾取此種具有NCF8之半導體晶片7。接下來,使自切割帶4拾取之具有NCF8之半導體晶片7於安裝步驟之中途上下反轉之後,如圖2C所示,安裝於具有電極12之基板13而製作半導體裝置15。半導體晶片7將其柱狀電極2連接於基板13之電極12,且安裝於基板13,藉此製作半導體裝置15。
半導體晶片7之安裝例如以如下方式實施。首先,利用未圖示之安裝工具保持半導體晶片7之第2面1b,以半導體晶片7之柱狀電極2與基板13之電極12接觸之方式,將半導體晶片7壓抵至基板13。於該狀態下,藉由一面加熱一面加壓,來將柱狀電極2與電極12接合,且將半導體晶片7安裝於基板13。NCF8作為半導體晶片7向基板13之黏著劑發揮功能,並且作為半導體晶片7與基板13之間之底部填充材發揮功能。NCF8利用安裝時之加熱而軟化,於之後之冷卻步驟中固化,作為黏著劑及底部填充材發揮功能。此時,由於在半導體晶片7之側面亦存在NCF8,故而於安裝於基板13之半導體晶片7之側面形成由NCF8形成之內圓角14。因此,利用大型化之內圓角14能夠提高半導體晶片7相對於基板13之安裝強度或應力緩和效果等。
此處,當於半導體晶片7之側面不存在NCF8時,亦存在如下情況:於安裝時之加壓步驟中,半導體晶片7與基板13之間多餘地存在之NCF8爬上半導體晶片7之側面,藉此於半導體晶片7之側面形成由NCF8形成之內圓角。然而,由於其量微小,故而無法形成充分之內圓角。針對該點,於實施形態之製造方法中,由於在半導體晶片7之側面亦存在NCF8,故而該側面之NCF8促進朝半導體晶片7之側面形成內圓角14,並且有助於內圓角14之大型化。即,於安裝於基板13之半導體晶片7之側面,能夠由充分之量之NCF8形成大型之內圓角14。進而,能夠利用內圓角14保護半導體晶片7之側面。內圓角14由於提高半導體晶片7對於基板13之接合強度,並且提高應力緩和效果,故而,例如當施加熱時於基板13產生收縮之情形時,亦能夠抑制半導體晶片7之剝離。因此,能夠提供可靠性或耐熱性等優異之半導體裝置1。
於由實施形態之製造方法獲得之半導體裝置15中,由於半導體晶片7之側面之NCF8存在於第1槽5內,故而如圖7所示,由NCF8形成之內圓角14之上部突出至半導體晶片7之上方。可以係具有此種形狀之內圓角14,但藉由對半導體晶片7之安裝工具進行設計而能夠獲得具有各種形狀之內圓角14之半導體裝置15。例如,藉由利用大於半導體晶片7之平面形狀之安裝工具保持半導體晶片7並壓抵至基板13,如圖8所示,能夠使由NCF8形成之內圓角14之上表面與半導體晶片7之背面為同一面。當於半導體晶片7上搭載其他半導體裝置等之情形時,具有如圖8所示之形狀之內圓角14係有效的。
於利用小於半導體晶片7之平面形狀之安裝工具保持半導體晶片7並壓抵至基板13之情形時,如圖9所示,能夠形成為向半導體晶片7之上方突出之內圓角14之上部因安裝時之加熱而覆蓋半導體晶片7之背面之外周側之一部分之形狀。具有如圖9所示之形狀之內圓角14由於使半導體晶片7相對於基板13之接合強度更進一步提高,故而能夠更加提高半導體裝置1之可靠性或耐熱性等。內圓角14之形狀能夠根據半導體裝置15之使用用途或要求之特性來選擇。
(第2實施形態) 圖10A至圖10C及圖11A至圖11D係表示第2實施形態之半導體裝置之製造方法之圖,且表示了於半導體晶圓之分割步驟應用隱形切割之半導體裝置之製造方法。圖10A至圖10C係表示自半導體晶圓之準備步驟至半導體晶圓之分割步驟之剖視圖,圖11A至圖11D係表示自非導電性膜之貼附及填充步驟至半導體裝置之安裝步驟之剖視圖。
首先,如圖10A所示,準備半導體晶圓1。與第1實施形態同樣地,半導體晶圓1具有分別具有柱狀電極(凸塊電極)2之複數個晶片區域X、及劃分該等複數個晶片區域X之切割區域D。於此種半導體晶圓1之具有柱狀電極2之第1表面1a上貼附表面保護帶3。接著,自與第1表面1a相反側之第2表面1b研削之前之半導體晶圓1之第2表面1b側,沿著切割區域D,將隱形切割用之雷射光21照射至半導體晶圓1。
半導體晶圓1之隱形切割具有如下步驟:將雷射光21聚光於半導體晶圓1之內部,形成成為半導體晶圓1之分割之起點之改質層22;以及對形成有改質層22之半導體晶圓1施加外力,將半導體晶圓1分割為包括複數個晶片區域X之半導體晶片。圖10A表示了利用雷射光21之改質層22之形成步驟。改質層22包含分割用之晶圓材質之改質區域及於半導體晶圓1之厚度方向延伸之龜裂等,藉由之後之外力之施加步驟以改質層22為起點將半導體晶圓1分割為複數個半導體晶片。
接下來,如圖10B所示,將形成有改質層22之半導體晶圓1之第2表面1b研削至與所製造之半導體晶片對應之厚度為止之後,剝離表面保護帶3。接著,於半導體晶圓1之經研削之第2表面1b貼附包括樹脂帶之切割帶4。如圖10C所示,藉由將貼附於形成有改質層22之半導體晶圓1之第2表面1b之切割帶(樹脂帶)4於其面方向擴張(延伸),以改質層22為起點來分割半導體晶圓1。基於改質層22之形成與切割帶4之擴張,於相鄰之複數個晶片區域X間形成間隙G,藉此將複數個晶片區域X單片化而形成複數個半導體晶片7。具有經單片化之半導體晶片7之半導體晶圓1之整體形狀由切割帶4來維持。
接下來,如圖11A所示,於經單片化之複數個半導體晶片7上,自半導體晶圓1之第1表面1a側貼附熱塑性之非導電性樹脂膜(NCF)8。此時,將NCF8之一部分填充至相鄰之複數個半導體晶片7間之間隙G內。NCF8向間隙G內之填充步驟與第1實施形態同樣地實施。例如,如圖3A及圖3B所示,能夠應用減壓下之貼附步驟與大氣壓下之填充步驟。此時,除了NCF8之大氣開放以外,亦可一併使用NCF8之加熱,例如向相當於間隙G之部分之局部加熱。又,亦可使用加熱器或烘箱等,將NCF8整體加熱。NCF8向間隙G內之填充步驟能夠與第1實施形態同樣地實施。
接下來,如圖11B所示,於填充至間隙G內之NCF8形成槽23,根據複數個半導體晶片7分割NCF8。此時,槽23以其寬度較間隙G之寬度窄之方式形成。藉此,於隔著間隙G配置之2個半導體晶片7之側面分別殘存NCF8。如下所述,殘存在半導體晶片7之側面之NCF8有助於將半導體晶片7安裝於基板時內圓角之形成,藉此能夠提高半導體晶片7之安裝強度。槽23之寬度與第1實施形態之第2槽9同樣地,較佳為以於2個半導體晶片7之側面分別殘存5 μm以上之NCF8之方式調整。
槽23之形成步驟與第1實施形態之第2槽9之形成步驟同樣地實施。例如,如圖4所示,使用具有較間隙G之寬度窄之寬度之切割刀片10,來切斷填充至間隙G內之NCF8。藉此,能夠於填充至間隙G內之NCF8形成槽23。又,如圖5A及圖5B所示,對形成於間隙G內之NCF8照射雷射光11而切斷之後,藉由將切割帶4於其面方向擴張來形成槽23。如圖6所示,亦存在根據切割帶4之材質等,而省去雷射切割步驟,僅利用擴張步驟形成槽23之情況。
藉由於填充至間隙G內之NCF8形成槽23,並根據複數個半導體晶片7分割NCF8,來形成具有經單片化之NCF8之半導體晶片7。如圖11C所示,自切割帶4依次拾取此種具有NCF8之半導體晶片7。接下來,使自切割帶4拾取之具有NCF8之半導體晶片7於安裝步驟之中途上下反轉之後,如圖11D所示,安裝於具有電極12之基板13製作半導體裝置15。半導體晶片7將其柱狀電極2連接於基板13之電極12,且安裝於基板13,藉此製作半導體裝置15。根據應用隱形切割而形成之半導體晶片7,如圖11C及圖11D所示,能夠抑制NCF8自半導體基板1之側面突出。因此,能夠抑制拾取具有NCF8之半導體晶片7時之吸附錯誤等。
(半導體裝置) 利用上述第1及第2實施形態之製造方法製作之半導體裝置15既可直接利用,又亦可用作其他半導體裝置之一部分。圖12係表示使半導體裝置15進一步功能化之半導體裝置,例如用作半導體記憶裝置之一部分之例之圖。圖12所示之半導體記憶裝置31具有設置於基板32上之半導體裝置15。於半導體裝置15中,半導體晶片7之電極2與基板32之電極33連接,於該狀態下安裝於基板32。半導體晶片7例如作為控制器晶片發揮功能。於半導體裝置15之周圍配置有間隔件34,例如矽間隔件。間隔件34利用DAF(Die Attach Film,晶片黏結膜)35黏著於基板32。
於半導體晶片7及間隔件34上,配置有第1記憶體晶片36及第2記憶體晶片37。第1記憶體晶片36利用DAF35黏著於半導體晶片7及間隔件34。第2記憶體晶片37利用DAF35黏著於第1記憶體晶片36。第2記憶體晶片37以第1記憶體晶片36之電極38露出之方式,階梯狀地積層於第1記憶體晶片36上。第2記憶體晶片37之電極39與第1記憶體晶片36之電極38利用接合線40電連接,第1記憶體晶片36之電極38與基板32之電極41利用接合線40電連接。於基板31上,以將各構成要素密封之方式形成有塑模樹脂42。此種半導體記憶裝置31中之控制器晶片(7)之安裝中有效地利用實施形態之半導體裝置之製造方法。
再者,對本發明之幾個實施形態進行了說明,但該等實施形態係作為示例而提出者,並不意圖限定發明之範圍。該等實施形態能以其他各種形態實施,於不脫離發明之主旨之範圍內,能夠進行各種省略、置換、變更。該等實施形態或其變化包含於發明之範圍或主旨中,同時包含於申請專利範圍所記載之發明及其均等之範圍中。相關申請之引用
本申請案以2019年09月17日申請之先行之日本專利申請案第2019-168888號之優先權之利益為基礎,且追求其利益,其內容整體藉由引用包含於本文中。
1:半導體晶圓 1a:第1表面 1b:第2表面 2:柱狀電極(凸塊電極) 3:表面保護帶 4:切割帶 5:第1槽 6:切割刀片 7:半導體晶片 8:非導電性樹脂膜(NCF) 9:第2槽 10:第2切割刀片 11:雷射光 12:電極 13:基板 14:內圓角 15:半導體裝置 21:雷射光 22:改質層 23:槽 31:半導體記憶裝置 32:基板 33:電極 34:間隔件 35:DAF 36:第1記憶體晶片 37:第2記憶體晶片 38:電極 39:電極 40:接合線 41:電極 42:塑模樹脂
圖1A至圖1E係表示第1實施形態之半導體裝置之製造方法之剖視圖。
圖2A至圖2C係表示第1實施形態之半導體裝置之製造方法之剖視圖。
圖3A及圖3B係表示圖1A至圖1E所示之半導體裝置之製造方法中之非導電性膜之貼附步驟及填充步驟之剖視圖。
圖4係表示圖2A至圖2C所示之半導體裝置之製造方法中之非導電性膜之分割步驟之第1例之剖視圖。
圖5A及圖5B係表示圖2A至圖2C所示之半導體裝置之製造方法中之非導電性膜之分割步驟之第2例之剖視圖。
圖6係表示圖2A至圖2C所示之半導體裝置之製造方法中之非導電性膜之分割步驟之第3例之剖視圖。
圖7係表示由實施形態之半導體裝置之製造方法獲得之半導體裝置之第1例之剖視圖。
圖8係表示由實施形態之半導體裝置之製造方法獲得之半導體裝置之第2例之剖視圖。
圖9係表示由實施形態之半導體裝置之製造方法獲得之半導體裝置之第3例之剖視圖。
圖10A至圖10C係表示第2實施形態之半導體裝置之製造方法之剖視圖。
圖11A至圖11D係表示第2實施形態之半導體裝置之製造方法之剖視圖。
圖12係表示使用由實施形態之半導體裝置之製造方法獲得之半導體裝置之半導體記憶裝置之剖視圖。
1:半導體晶圓
2:柱狀電極(凸塊電極)
4:切割帶
5:第1槽
7:半導體晶片
8:非導電性樹脂膜(NCF)
9:第2槽
12:電極
13:基板
14:內圓角
15:半導體裝置

Claims (15)

  1. 一種半導體裝置之製造方法,其具備如下步驟:將具備分別具有柱狀電極之複數個晶片區域、及劃分上述複數個晶片區域之切割區域之半導體晶圓沿著上述切割區域分割,將上述複數個晶片區域單片化而形成複數個半導體晶片;於上述經單片化之複數個半導體晶片上,自上述半導體晶圓之第1表面側貼附非導電性樹脂膜,並且將上述非導電性樹脂膜之一部分填充至相鄰之上述複數個半導體晶片間之間隙;於填充至上述間隙內之上述非導電性樹脂膜,一面使上述非導電性樹脂膜殘留於上述經單片化之半導體晶片之側面,一面形成具有較上述間隙之寬度窄之寬度之槽,藉此根據上述複數個半導體晶片分割上述非導電性樹脂膜;及依次拾取具有上述經分割之非導電性樹脂膜之上述複數個半導體晶片,一面將上述拾取之上述半導體晶片之上述柱狀電極接合於基板之電極,一面隔著上述非導電性樹脂膜而將上述半導體晶片安裝於上述基板;且上述非導電性樹脂膜之貼附及填充步驟具備如下步驟:減壓下將上述非導電性樹脂膜貼附於上述複數個半導體晶片;以及將貼附有上述非導電性樹脂膜之上述複數個半導體晶片大氣開放,並將上述非導電性樹脂膜之一部分填充至上述間隙內。
  2. 如請求項1之半導體裝置之製造方法,其中上述非導電性樹脂膜之貼 附及填充步驟進而具備將上述大氣開放之上述非導電性樹脂膜之至少相當於上述間隙之部分加熱之步驟。
  3. 如請求項1或2之半導體裝置之製造方法,其中上述複數個晶片區域之單片化步驟具備如下步驟:一面於上述半導體晶圓之與具有上述柱狀電極之第1表面為相反側之第2表面貼附樹脂帶;及一面利用上述樹脂帶維持上述半導體晶圓之晶圓形狀,一面自上述半導體晶圓之上述第1表面側沿著上述切割區域形成第1槽。
  4. 一種半導體裝置之製造方法,其具備如下步驟:準備半導體晶圓,該半導體晶圓具備:分別具有柱狀電極之複數個晶片區域、及劃分上述複數個晶片區域之切割區域;於上述半導體晶圓之與具有上述柱狀電極之第1表面為相反側之第2表面貼附樹脂帶;形成第1槽,該第1槽自上述半導體晶圓之上述第1表面側沿著上述切割區域貫通上述半導體晶圓而到達上述樹脂帶;沿著上述切割區域分割上述半導體晶圓,將上述複數個晶片區域單片化而形成複數個半導體晶片;在上述樹脂帶上,於上述經單片化之複數個半導體晶片上,自上述半導體晶圓之第1表面側貼附非導電性樹脂膜,並且將上述非導電性樹脂膜之一部分填充至相鄰之上述複數個半導體晶片間之間隙;於經填充至上述間隙內之上述非導電性樹脂膜,一面使上述非導電性樹脂膜殘留於上述經單片化之半導體晶片之側面,一面形成具有較上述 間隙之寬度窄之寬度之槽,藉此根據上述複數個半導體晶片分割上述非導電性樹脂膜;及依次拾取具有上述經分割之非導電性樹脂膜之上述複數個半導體晶片,一面將上述拾取之上述半導體晶片之上述柱狀電極接合於基板之電極,一面隔著上述非導電性樹脂膜而將上述半導體晶片安裝於上述基板。
  5. 如請求項1、2及4中任一項之半導體裝置之製造方法,其中上述非導電性樹脂膜之貼附及填充步驟具備如下步驟:將上述非導電性樹脂膜貼附於上述複數個半導體晶片;以及將貼附於上述複數個半導體晶片之上述非導電性樹脂膜之至少相當於上述間隙之部分加熱,並將上述非導電性樹脂膜之一部分填充至上述間隙內。
  6. 如請求項1、2及4中任一項之半導體裝置之製造方法,其中上述非導電性樹脂膜之分割步驟具備利用具有較上述間隙之寬度窄之寬度之刀片將填充至上述間隙內之上述非導電性樹脂膜切斷之步驟。
  7. 如請求項6之半導體裝置之製造方法,其中上述非導電性樹脂膜之分割步驟進而具備將利用上述刀片切斷之上述非導電性樹脂膜於其面方向延伸之步驟。
  8. 如請求項1、2及4中任一項之半導體裝置之製造方法,其中上述非導電性樹脂膜之分割步驟具備對填充至上述間隙內之上述非導電性樹脂膜照射雷射光而熔融斷開之步驟。
  9. 如請求項1、2及4中任一項之半導體裝置之製造方法,其中上述非導電性樹脂膜之分割步驟進而具備將利用上述雷射熔融斷開之上述非導電性樹脂膜於其面方向延伸之步驟。
  10. 如請求項1、2及4中任一項之半導體裝置之製造方法,其中上述非導電性樹脂膜之分割步驟具備將上述非導電性樹脂膜於其面方向延伸而分割上述非導電性樹脂膜之步驟。
  11. 如請求項1、2及4中任一項之半導體裝置之製造方法,其中上述複數個晶片區域之單片化步驟具備如下步驟:對上述半導體晶圓之具有上述柱狀電極之第1表面,沿著上述切割區域照射雷射光而形成改質層;於上述半導體晶圓之與上述第1表面相反側之第2表面貼附樹脂帶;以及將上述樹脂帶於其面方向延伸,而分割上述半導體晶圓。
  12. 如請求項1、2及4中任一項之半導體裝置之製造方法,其中於安裝於上述基板之上述半導體晶片之側面,利用上述非導電性樹脂膜形成內圓角。
  13. 如請求項1、2及4中任一項之半導體裝置之製造方法,其中依次拾取具有上述經分割之非導電性樹脂膜之上述複數個半導體晶片時,上述複數個半導體晶片之側面係被上述非導電性樹脂膜覆蓋。
  14. 如請求項1、2及4中任一項之半導體裝置之製造方法,其中依次拾取具有上述經分割之非導電性樹脂膜之上述複數個半導體晶片時,上述複數個半導體晶片之側面全部係被上述非導電性樹脂膜覆蓋。
  15. 如請求項1、2及4中任一項之半導體裝置之製造方法,其中依次拾取具有上述經分割之非導電性樹脂膜之上述複數個半導體晶片時,上述非導電性樹脂膜係自上述複數個半導體晶片之上述第2表面突出。
TW109101376A 2019-09-17 2020-01-15 半導體裝置之製造方法 TWI740350B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019168888A JP2021048205A (ja) 2019-09-17 2019-09-17 半導体装置の製造方法
JP2019-168888 2019-09-17

Publications (2)

Publication Number Publication Date
TW202113937A TW202113937A (zh) 2021-04-01
TWI740350B true TWI740350B (zh) 2021-09-21

Family

ID=74869778

Family Applications (1)

Application Number Title Priority Date Filing Date
TW109101376A TWI740350B (zh) 2019-09-17 2020-01-15 半導體裝置之製造方法

Country Status (4)

Country Link
US (1) US11309219B2 (zh)
JP (1) JP2021048205A (zh)
CN (1) CN112530816B (zh)
TW (1) TWI740350B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220361338A1 (en) * 2021-05-07 2022-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package with stress reduction design and method for forming the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201611186A (zh) * 2014-09-11 2016-03-16 吉帝偉士股份有限公司 半導體裝置之製造方法
US9425177B2 (en) * 2013-06-25 2016-08-23 Micron Technology, Inc. Method of manufacturing semiconductor device including grinding semiconductor wafer
TW201932558A (zh) * 2017-12-14 2019-08-16 日商日東電工股份有限公司 接著膜及附有切晶帶之接著膜

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0395639U (zh) 1990-01-17 1991-09-30
JP3455762B2 (ja) 1999-11-11 2003-10-14 カシオ計算機株式会社 半導体装置およびその製造方法
JP3459622B2 (ja) * 2000-07-18 2003-10-20 サンユレック株式会社 電子部品の製造方法
JP4748518B2 (ja) * 2005-07-20 2011-08-17 古河電気工業株式会社 ダイシングダイボンドテープおよびダイシングテープ
JP5084829B2 (ja) 2007-06-28 2012-11-28 パナソニック株式会社 半導体素子の実装構造体の製造方法、半導体素子の実装方法、及び加圧ツール
JP2009260213A (ja) * 2008-03-24 2009-11-05 Hitachi Chem Co Ltd 半導体装置の製造方法
JP2011129779A (ja) 2009-12-18 2011-06-30 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
JP5474630B2 (ja) 2010-03-30 2014-04-16 トッパン・フォームズ株式会社 電子部品およびその製造方法、部品実装基板
US9064881B2 (en) * 2010-11-11 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Protecting flip-chip package using pre-applied fillet
US20130157414A1 (en) * 2011-12-20 2013-06-20 Nxp B. V. Stacked-die package and method therefor
US9245804B2 (en) * 2012-10-23 2016-01-26 Nxp B.V. Using a double-cut for mechanical protection of a wafer-level chip scale package (WLCSP)
US8816500B2 (en) * 2012-12-14 2014-08-26 Infineon Technologies Ag Semiconductor device having peripheral polymer structures
US9343433B2 (en) * 2014-01-28 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with stacked dies and methods of forming the same
US9484227B1 (en) * 2015-06-22 2016-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Dicing in wafer level package
DE102015120755A1 (de) * 2015-11-30 2017-06-01 Infineon Technologies Ag Verfahren zum Vereinzeln von einer Vielzahl von Chips
CN109563218A (zh) * 2016-08-10 2019-04-02 松下知识产权经营株式会社 密封用丙烯酸类组合物、片材、层叠片、固化物、半导体装置及半导体装置的制造方法
TWI675441B (zh) * 2018-05-14 2019-10-21 欣興電子股份有限公司 封裝載板結構及其製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9425177B2 (en) * 2013-06-25 2016-08-23 Micron Technology, Inc. Method of manufacturing semiconductor device including grinding semiconductor wafer
TW201611186A (zh) * 2014-09-11 2016-03-16 吉帝偉士股份有限公司 半導體裝置之製造方法
TW201932558A (zh) * 2017-12-14 2019-08-16 日商日東電工股份有限公司 接著膜及附有切晶帶之接著膜

Also Published As

Publication number Publication date
JP2021048205A (ja) 2021-03-25
CN112530816B (zh) 2024-03-08
US11309219B2 (en) 2022-04-19
TW202113937A (zh) 2021-04-01
CN112530816A (zh) 2021-03-19
US20210082761A1 (en) 2021-03-18

Similar Documents

Publication Publication Date Title
US9269873B2 (en) Semiconductor light emitting device and method for manufacturing same
US7560302B2 (en) Semiconductor device fabricating method
TWI643267B (zh) 半導體裝置及其製造方法
JP2009529804A (ja) 半導体デバイスのパッケージング
TW201314757A (zh) 於塗佈後研磨前之切塊
US20180204786A1 (en) Die with metallized sidewall and method of manufacturing
US10490470B2 (en) Semiconductor package and method for fabricating a semiconductor package
JP6797234B2 (ja) 半導体パッケージ構造体及びその製造方法
TWI798519B (zh) 半導體裝置及其製造方法
WO2014128796A1 (ja) 半導体装置
WO2018196630A1 (zh) 传感器封装结构的制备方法和传感器封装结构
TWI740350B (zh) 半導體裝置之製造方法
TWI689056B (zh) 封裝結構及其製造方法
JP2015225933A (ja) 半導体装置及びその製造方法
TWI582867B (zh) 晶片封裝製程
CN109524358B (zh) 半导体装置及其制造方法
CN110797334B (zh) 半导体装置及其制造方法
TW201236073A (en) Pre-cut wafer applied underfill film on dicing tape
JP2007242684A (ja) 積層型半導体装置及びデバイスの積層方法
JPH09172029A (ja) 半導体チップ及びその製造方法並びに半導体装置
US9214413B2 (en) Semiconductor die package with pre-molded die
TWI466199B (zh) 具有晶圓尺寸貼片的封裝方法
JP6422296B2 (ja) 電子部品およびその製造方法
US20150279790A1 (en) Prevention of warping during handling of chip-on-wafer
JP6223085B2 (ja) 半導体装置の製造方法