JP6422296B2 - 電子部品およびその製造方法 - Google Patents
電子部品およびその製造方法 Download PDFInfo
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- JP6422296B2 JP6422296B2 JP2014207654A JP2014207654A JP6422296B2 JP 6422296 B2 JP6422296 B2 JP 6422296B2 JP 2014207654 A JP2014207654 A JP 2014207654A JP 2014207654 A JP2014207654 A JP 2014207654A JP 6422296 B2 JP6422296 B2 JP 6422296B2
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- Prior art keywords
- chip
- resin
- sealing
- mounting substrate
- electronic component
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
Claims (2)
- チップを基材表面に電極パターンが形成された実装基板に実装し、樹脂封止する電子部品の製造方法において、
チップ実装面に、前記チップ表面に形成された電極と接続されるチップ電極接続部と、該チップ電極接続部に囲まれた部分に前記チップ電極接続部と離間し、前記チップ電極接続部と同じ高さの樹脂堰き止め部とを備え、前記チップ実装面の裏面側の外部実装面に外部接続部を備えた実装基板を用意する工程と、
前記チップ表面が、前記樹脂堰き止め部に対向するように前記チップ電極接続部と前記チップ表面に形成された電極を接続する工程と、
前記実装基板のチップ実装面に露出する前記実装基板および前記チップ上を被覆し、前記チップ表面と前記実装基板のチップ実装面との間に封止樹脂を注入するとともに、前記基材表面の高さと前記樹脂堰き止め部の表面の高さとの間に形成される段部により拡げられた空間に前記封止樹脂が溜まり、前記チップ表面と前記樹脂堰き止め部との間に空間を残すように樹脂封止を行う工程と、を含むことを特徴とする電子部品の製造方法。 - 請求項1記載の電子部品の製造方法において、樹脂封止する工程は、減圧状態で、前記実装基板のチップ実装面に露出する前記実装基板および前記チップ上を樹脂シートで被覆し、前記減圧状態を破り常圧状態にすることにより前記樹脂シートを加圧し、前記段部により拡げられた空間に前記封止樹脂が溜まり、前記チップ表面と前記樹脂堰き止め部との間に空間を残すように樹脂封止することを特徴とする電子部品の製造方法。
Priority Applications (1)
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JP2014207654A JP6422296B2 (ja) | 2014-10-09 | 2014-10-09 | 電子部品およびその製造方法 |
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JP2014207654A JP6422296B2 (ja) | 2014-10-09 | 2014-10-09 | 電子部品およびその製造方法 |
Publications (2)
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JP2016076666A JP2016076666A (ja) | 2016-05-12 |
JP6422296B2 true JP6422296B2 (ja) | 2018-11-14 |
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JP2014207654A Active JP6422296B2 (ja) | 2014-10-09 | 2014-10-09 | 電子部品およびその製造方法 |
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JP (1) | JP6422296B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2021029259A1 (ja) * | 2019-08-09 | 2021-02-18 | ナガセケムテックス株式会社 | モールドアンダーフィル封止用の多層シート、モールドアンダーフィル封止方法、電子部品実装基板及び電子部品実装基板の製造方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3207222B2 (ja) * | 1991-08-29 | 2001-09-10 | 株式会社東芝 | 電子部品装置 |
JP2758115B2 (ja) * | 1992-12-28 | 1998-05-28 | ローム株式会社 | 半導体装置 |
JPH11233673A (ja) * | 1998-02-13 | 1999-08-27 | Hitachi Ltd | 半導体装置及びその製造方法並びに電子装置 |
US5969461A (en) * | 1998-04-08 | 1999-10-19 | Cts Corporation | Surface acoustic wave device package and method |
JP3702961B2 (ja) * | 2002-10-04 | 2005-10-05 | 東洋通信機株式会社 | 表面実装型sawデバイスの製造方法 |
JP2009010942A (ja) * | 2007-05-29 | 2009-01-15 | Nippon Dempa Kogyo Co Ltd | 圧電部品及びその製造方法 |
WO2010109703A1 (ja) * | 2009-03-24 | 2010-09-30 | 日本電気株式会社 | 電子装置、基板および電子装置の製造方法 |
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