TWI798519B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TWI798519B
TWI798519B TW109100632A TW109100632A TWI798519B TW I798519 B TWI798519 B TW I798519B TW 109100632 A TW109100632 A TW 109100632A TW 109100632 A TW109100632 A TW 109100632A TW I798519 B TWI798519 B TW I798519B
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Taiwan
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resin layer
semiconductor
chip
controller chip
substrate
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TW109100632A
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TW202109687A (zh
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丹羽恵一
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日商鎧俠股份有限公司
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  • Wire Bonding (AREA)

Abstract

本實施形態之半導體裝置具備第1基板。第1半導體晶片於與該第1基板對向之第1面上，具有與第1基板之端子連接之電極。第1樹脂層係非導電性，設置於第1基板與第1半導體晶片之間。並且，第1樹脂層覆蓋第1半導體晶片之與第1面為相反側之第2面整體，且具有較該第2面平坦之上表面。

Description

半導體裝置及其製造方法
本實施形態係關於一種半導體裝置及其製造方法。
半導體晶片有時具有金屬凸塊，其藉由覆晶之方式連接至配線板上之端子上。又，半導體晶片有時被薄膜化，於經過半導體元件之製造工序時會產生翹曲。這種出現翹曲之半導體晶片若藉由覆晶之方式連接至配線板上，半導體晶片有時會出現缺口。
又，於出現翹曲之半導體晶片上積層其它半導體晶片時，積層之半導體晶片之間密接性差，亦會出現半導體晶片間之接著劑剝落之問題。
本發明提供一種半導體裝置，於將出現翹曲之半導體晶片安裝至配線板上時，可抑制半導體晶片之龜裂，於半導體晶片上良好地接著其它半導體晶片。
本實施形態之半導體裝置具備第1基板。第1半導體晶片於與上述第1基板對向之第1面上，具有連接於第1基板之端子之電極。第1樹脂層為非導電性，設置於第1基板與第1半導體晶片之間。並且，第1樹脂層覆蓋第1半導體晶片之與第1面為相反側之第2面整體，且具有較該第2面平坦之上表面。
以下，參照圖式來說明本發明之實施形態。本實施形態並非用於限定本發明。圖式係示意圖或概念圖，各部分之比率等未必與實物相同。於說明書及圖式中，對於與前圖已出現之元件相同之元件標註相同符號，並適當地省略詳細說明。
(第1實施形態)圖1係表示第1實施形態之半導體裝置之構成例之剖視圖。本實施形態之半導體裝置1例如係NAND型閃速記憶體。半導體裝置1具備配線板10、樹脂層20、控制器晶片30、接著層40、間隔件50、NAND型記憶體晶片(以下稱為記憶體晶片)60、金屬焊墊70、接合線80、密封樹脂90。再者，本實施形態並不限定於NAND型閃速記憶體，亦能應用於藉由覆晶連接之半導體裝置。
作為第1基板之配線板10具備絕緣基板11、配線12、接觸插塞13、金屬焊墊14、金屬凸塊15、阻焊劑16。絕緣基板11例如使用玻璃環氧樹脂等絕緣材料形成。配線12設置於絕緣基板11之表面、背面或內部，將金屬焊墊14與金屬凸塊15電性連接。接觸插塞13以貫穿絕緣基板11之方式設置，將配線12之間電性連接。金屬焊墊14於配線板10之表面連接控制器晶片30之電極31。金屬凸塊15於配線板10之背面連接於配線12。配線12、接觸插塞13及金屬焊墊14例如使用銅等導電性材料形成。金屬凸塊15例如使用鎳、焊料等導電性材料形成。
作為第1半導體晶片之控制器晶片30具有：與配線板10對向之第1面F1；位於第1面F1之相反側之第2面F2。第1面F1上，設置有作為電極之金屬凸塊31。金屬凸塊31連接於配線板10之金屬焊墊14。即，控制器晶片30藉由覆晶之方式連接於配線板10上。
控制器晶片30被薄化，於第1面F1或第2面F2上具有半導體元件。於形成半導體元件時，控制器晶片30有時會翹曲。控制器晶片30例如會以山形、椀形或鞍形翹曲。圖1中，控制器晶片30以山形翹曲。
樹脂層(第1樹脂層)20被填充於配線板10與控制器晶片30之間，覆蓋金屬焊墊14與電極31之連接部分而進行保護。進而，樹脂層20亦設置於控制器晶片30之第2面F2上，覆蓋第2面F2整體。樹脂層20為非導電性之樹脂材料(NCP(Non Conductive Paste))，例如可為環氧樹脂、丙烯酸樹脂、二氧化矽等混合而成之漿料。樹脂層20覆蓋控制器晶片30之整體，其上表面F3大致平坦。樹脂層20之上表面F3位於至少較控制器晶片30之第2面F2高之位置，較第2面F2更平坦。
間隔件50設置於控制器晶片30之周圍，藉由接著層(DAF(Die Attachment Film))40而接著於配線板10上。間隔件50之設置高度為與樹脂層20之上表面F3之高度大致相等，支持記憶體晶片60。間隔件50例如具有四邊形之框形狀，以包圍控制器晶片30四周之方式設置於配線板10之表面上。間隔件50例如使用矽等材料形成。
記憶體晶片60設置於控制器晶片30之上方，藉由接著層40接著於樹脂層20及間隔件50上。記憶體晶片60例如具有將複數個記憶胞三維配置而成之立體型記憶胞陣列。接著層40設置於樹脂層20及間隔件50上，將記憶體晶片60接著於樹脂層20及間隔件50上。
此處，控制器晶片30具有翹曲，但控制器晶片30之第2面F2整體上設置有樹脂層20。樹脂層20之上表面F3大致平坦，因此，記憶體晶片60可不受控制器晶片30之翹曲之影響而配置於大致平坦之樹脂層20之上表面F3上。因此，可抑制記憶體晶片60產生缺口。
複數個接著層40及複數個記憶體晶片60亦可交替地積層於樹脂層20及間隔件50上。如此，即使於控制器晶片30之上方積層複數個記憶體晶片60，由於樹脂層20之上表面F3大致平坦，因此，複數個記憶體晶片60亦難以受到控制器晶片30之翹曲之影響。即，複數個記憶體晶片60不易出現缺口，不易自接著層40剝落。
接合線80將記憶體晶片60之金屬焊墊70與配線板10之金屬焊墊14之任一個之間電性連接。作為第2樹脂層之密封樹脂90整體覆蓋控制器晶片30、記憶體晶片60、接合線80等配線板10上之構造進行保護。
如此，根據本實施形態，樹脂層20覆蓋控制器晶片30之第2面F2整體，控制器晶片30之第2面F2形成為大致平坦之上表面F3。藉此，即使控制器晶片30翹曲時，樹脂層20亦會抵消控制器晶片30之翹曲而大致平坦地設置於第2面F2上。因此，樹脂層20之厚度T20較佳為控制器晶片30之翹曲量(控制器晶片30之上端與下端之間的距離)T30以上。藉此，樹脂層20可自配線板10之表面一直設置至控制器晶片30之上端,從而可大致平坦地覆蓋第2面F2整體。由於樹脂層20之上表面F3大致平坦，因此記憶體晶片60不易受到控制器晶片30之翹曲之影響。因此，即使於控制器晶片30之上方積層複數個記憶體晶片60，亦能抑制記憶體晶片60之缺口或接著不良。
再者，圖1中，同一半導體封裝體內設置有兩個晶片，即，藉由覆晶方式連接之控制器晶片30及藉由引線接合方式連接之記憶體晶片60。即，圖1中，表示混合型多晶片封裝體。但，本實施形態亦可與控制器晶片30同樣地將複數個記憶體晶片60藉由覆晶之方式連接。
其次，說明本實施形態之半導體裝置1之製造方法。
圖2(A)～圖8係表示第1實施形態之半導體裝置1之製造方法之一例之立體圖或剖視圖。圖2(A)～圖2(D)表示半導體晶圓製程至切割工序之製造工序。半導體晶圓製程可應用於控制器晶片30及記憶體晶片60之任一個。以下，亦將控制器晶片30或記憶體晶片60稱為半導體晶片C。
首先，於半導體晶圓W之表面上，形成未圖示之半導體元件。半導體元件可為記憶胞陣列或CMOS(Complementary Metal Oxide Semiconductor，互補金氧半導體)電路等。其次，藉由CMP(Chemical Mechanical Polishing，化學機械研磨)法等對半導體晶圓W之背面進行研磨。然後，於半導體晶圓W上形成TSV(Through Silicon Via，矽穿孔)、電極焊墊、金屬凸塊等(均未圖示)。
圖2(A)表示形成半導體元件後之半導體晶圓W。複數個半導體晶片C之間有切割線DL，如下所述，藉由切斷該切割線DL而將半導體晶片C單片化。
其次，如圖2(B)所示，於張設在晶圓環130內之可撓性之樹脂帶131上貼附半導體晶圓W。然後，使用雷射振盪器150自半導體晶圓W之表面對與切割線DL對應之部分照射雷射光。藉此，於半導體晶圓W之切割線DL上形成槽。
其次，如圖2(C)所示，使用切割刀片160切斷半導體晶圓W之切割線DL。藉此，於樹脂帶131上，將半導體晶圓W單片化為半導體晶片C。
其次，對樹脂帶131照射紫外線，減弱半導體晶片C與樹脂帶131之間之接著劑之黏接性，從而能夠自樹脂帶131取下半導體晶片C，再者進行外觀檢查等。
圖3～圖8表示於配線板10上安裝半導體晶片C(控制器晶片30或記憶體晶片60)之組裝工序。再者，於圖4以後之圖中，省略了控制器晶片30之翹曲之圖示。
如圖3所示，向配線板10之表面上供給樹脂層20之材料。於此階段中，樹脂層20之材料為液狀，被供給至配置控制器晶片30之區域。
其次，如圖4所示，壓接裝置100經由FAB(Film Assist Bonding，膜輔助接合)膜95吸附控制器晶片30，並將該控制器晶片30配置於配線板10上。此時，壓接裝置100以設置於控制器晶片30之第1面F1上之電極31對應於配線板10之金屬焊墊14之方式，於配線板10上積層控制器晶片30。
壓接裝置100具有與未圖示之真空泵連接之抽吸孔105，藉由該抽吸孔105來吸附控制器晶片30。壓接裝置100之吸附面為大致平坦面，以便將控制器晶片30壓接至配線板10上，且使樹脂層20之上表面F3大致平坦。為了使樹脂層20之材料不會附著於壓接裝置100上，壓接裝置100與控制器晶片30之間介置有作為樹脂膜之FAB膜95。為了使FAB膜95不會阻礙壓接裝置100對控制器晶片30之吸附，於FAB膜95上與抽吸孔105對應之部位設置有孔。
壓接裝置100於將控制器晶片30積層至配線板10上之後，對配線板10及控制器晶片30施加壓力並進行加熱。藉此，將控制器晶片30之電極31與配線板10之金屬焊墊14連接(熔接)。於配線板10上積層控制器晶片30時，樹脂層20之材料向壓接裝置100及控制器晶片30之兩側擠出，並藉由控制器晶片30之側面一定程度堆至第2面F2側。為了使樹脂層20之材料會向第2面F2側擠出，於圖3之樹脂層20之材料之供給階段，調節樹脂層20之材料之供給量。
其次，如圖5所示，停止壓接裝置100之抽真空，使壓接裝置100略向D1方向上升。此時，由於抽真空停止，因此控制器晶片30自壓接裝置100脫離而留於配線板10上。D1方向係控制器晶片30及記憶體晶片60之積層方向，於鉛垂方向上朝上。
其次，如圖6所示，向D2方向移動FAB膜95，使FAB膜95之孔之位置與壓接裝置100之抽吸孔105之位置錯開。較佳為於壓接裝置100之吸附面上，FAB膜95之孔不重疊。此時，壓接裝置100不進行抽真空，因此FAB膜95可容易地相對於壓接裝置100移動。藉此，可抑制樹脂層20之材料藉由FAB膜95之孔而附著於壓接裝置100之情形。
其次，向D3方向略微下降壓接裝置100。D3方向係積層方向，於鉛垂方向上朝下。此處，壓接裝置100之底面之FAB膜95與控制器晶片30之第2面F2之間會形成間隙G。下一工序中，樹脂層20之材料被導入間隙G，FAB膜95上與控制器晶片30對向之面變成樹脂層20之上表面F3。因此，壓接裝置100之底面之設定位置較樹脂層20之上表面F3高了FAB膜95之高度。
其次，如圖7所示，使壓接裝置100向D4方向往返動作。D4方向係大致水平之方向，該方向與D1、D3方向大致正交。此時，FAB膜95不移動，壓接裝置100相對於FAB膜95而相對移動。如此，於樹脂層20上配置FAB膜95，藉由該FAB膜95而用壓接裝置100使樹脂層20之上表面平坦化。藉此，樹脂層20之材料於間隙G內擴散，FAB膜95與控制器晶片30之間變得大致平坦。結果，控制器晶片30嵌入樹脂層20內，樹脂層20之材料覆蓋第2面F2整體。又，樹脂層20之上表面F3大致平坦化。如此，當壓接裝置100之底面(壓接面)之面積小於控制器晶片30之第2面F2之面積時，藉由使壓接裝置100朝大致水平方向往返動作，將樹脂層20大致整平。其次，藉由對樹脂層20之材料進行熱處理等，而使樹脂層20固化。
其次，如圖8所示，藉由接著層40，於控制器晶片30周圍接著間隔件50。進而，於間隔件50及樹脂層20上形成接著層40，於該接著層40上配置記憶體晶片60。藉此，記憶體晶片60於控制器晶片30之上方接著於樹脂層20及間隔件50上。
然後，亦可進一步積層接著層40及記憶體晶片60。藉由引線接合，用密封樹脂90將記憶體晶片60及控制器晶片30密封。藉此，完成圖1所示之半導體裝置1。亦可代替引線接合，而使用未圖示之金屬凸塊，將複數個記憶體晶片60以覆晶之方式連接。
如上所述，根據本實施形態，壓接裝置100於配線板10上積層控制器晶片30並進行覆晶連接後，接著於FAB膜95與控制器晶片30之間形成間隙G，並向間隙G導入樹脂層20之材料。然後，壓接裝置100自FAB膜95上使樹脂層20大致平坦，藉由樹脂層20覆蓋控制器晶片30之第2面F2整體。藉此，即使當控制器晶片30翹曲時，樹脂層20亦能抵消控制器晶片30之翹曲而大致平坦地覆蓋第2面F2。結果，即使於控制器晶片30之上方積層記憶體晶片60，亦能抑制記憶體晶片60之缺口、接著不良。再者，第1實施形態中，樹脂層20之材料僅供給一次，但如第3實施形態及之後之實施形態所示，亦可分為兩次供給。
(第2實施形態)圖9～圖11係表示第2實施形態之半導體裝置1之製造方法之一例之剖視圖。第2實施形態中，壓接裝置100之吸附面之面積大於控制器晶片30之第2面F2之面積。因此，不用向D4方向移動壓接裝置100，即可使樹脂層20之材料大致平坦。
例如，如圖3所示，向配線板10上供給樹脂層20之材料後，如圖9所示，壓接裝置100藉由FAB膜95吸附控制器晶片30，將該控制器晶片30配置於配線板10上。壓接裝置100對配線板10及控制器晶片30施加壓力並進行加熱。藉此，將控制器晶片30之電極31與配線板10之金屬焊墊14藉由覆晶之方式連接。
其次，如圖10所示，停止壓接裝置100之抽真空，向D1方向略微上升壓接裝置100。其次，以樹脂層20之材料不會附著至壓接裝置100之方式，向D2方向移動FAB膜95，使FAB膜95之孔之位置與壓接裝置100之抽吸孔105之位置錯開。
其次，如圖11所示，向D3方向略微下降壓接裝置100，利用毛細管現象向間隙G內導入樹脂層20之材料。藉此，樹脂層20之材料覆蓋第2面F2整體，其上表面F3大致平坦化。進而，藉由對樹脂層20之材料進行熱處理等而使樹脂層20固化。
之後之工序如第1實施形態說明般進行。藉此，完成圖1所示之半導體裝置1。如此，即使使用吸附面之面積大之壓接裝置100，亦能製造本實施形態之半導體裝置1。於此情形時，無需使壓接裝置100向D4方向往返動作。
(第3實施形態)圖12～圖15係表示第3實施形態之半導體裝置1之製造方法之一例之剖視圖。第3實施形態中，樹脂層20之材料分為兩次供給。例如，如圖3所示，向配線板10之表面上供給樹脂層20之材料。
其次，如圖12所示，壓接裝置100藉由FAB膜95吸附控制器晶片30，將該控制器晶片30配置於配線板10上。此時，壓接裝置100以控制器晶片30之第1面F1上設置之電極31與配線板10之金屬焊墊14對應之方式，於配線板10上積層控制器晶片30。壓接裝置100對配線板10及控制器晶片30施加壓力並進行加熱，將控制器晶片30之電極31與配線板10之金屬焊墊14藉由覆晶之方式連接。第3實施形態之該階段中，壓接裝置100並未於FAB膜95與控制器晶片30之間形成間隙G，暫時未用樹脂層20覆蓋控制器晶片30之第2面F2。因此，得到圖13所示之構造。
其次，如圖14所示，再次向控制器晶片30之第2面F2上供給樹脂層20之材料。
其次，如圖15所示，壓接裝置100經由FAB膜95將樹脂層20之材料於控制器晶片30之第2面F2上整平為大致平坦。FAB膜95之孔之位置與壓接裝置100之抽吸孔105之位置錯開。此時，壓接裝置100以於FAB膜95與控制器晶片30之第2面F2之間形成間隙G之方式，朝D4方向進行往返動作。藉此，樹脂層20之材料被導入間隙G，樹脂層20之上表面變得大致平坦。進而，藉由對樹脂層20之材料進行熱處理等，使樹脂層20固化。
如此，於第3實施形態中，第一次供給樹脂層20之材料後，壓接裝置100為了將控制器晶片30藉由覆晶之方式連接至配線板10上，而於配線板10上對控制器晶片30施加壓力。然後，第二次供給樹脂層20之材料後，壓接裝置100再次向控制器晶片30上移動，以由樹脂層20大致平坦地覆蓋控制器晶片30之第2面F2之方式，將樹脂層20之材料整平。
其後之工序如第1實施形態說明般進行。藉此，完成圖1所示之半導體裝置1。如此，即使分兩次供給樹脂層20之材料，亦能製造本實施形態之半導體裝置1。
(第4實施形態)圖16～圖19係表示第4實施形態之半導體裝置1之製造方法之一例之剖視圖。第4實施形態中，分兩次供給樹脂層20之材料，此點與第3實施形態相同。另一方面，與第2實施形態同樣地，壓接裝置100之吸附面之面積大於控制器晶片30之第2面F2之面積。即，第4實施形態係第2及第3實施形態之組合。
例如，如圖3所示，向配線板10之表面上供給樹脂層20之材料。其次，如圖16所示，壓接裝置100經由FAB膜95吸附控制器晶片30，將該控制器晶片30配置於配線板10上。此時，壓接裝置100以將設置於控制器晶片30之第1面F1上之電極31與配線板10之金屬焊墊14對應之方式，於配線板10上積層控制器晶片30。壓接裝置100對配線板10及控制器晶片30施加壓力並進行加熱，將控制器晶片30之電極31與配線板10之金屬焊墊14予以覆晶連接。在第4實施形態之該階段，壓接裝置100並未於FAB膜95與控制器晶片30之間形成間隙G，尚未由樹脂層20覆蓋控制器晶片30之第2面F2。因此，得到圖17所示之構造。
其次，如圖18所示，再次向控制器晶片30之第2面F2上供給樹脂層20之材料。
其次，如圖19所示，壓接裝置100藉由FAB膜95將樹脂層20之材料於控制器晶片30之第2面F2上整平為大致平坦。FAB膜95之孔之位置與壓接裝置100之抽吸孔105之位置錯開。此時，壓接裝置100之吸附面之面積大於控制器晶片30之第2面F2之面積，因此，壓接裝置100無需向D4方向移動。FAB膜95與控制器晶片30之第2面F2之間之間隙G內導入樹脂層20之材料，樹脂層20之上表面大致平坦。進而，藉由對樹脂層20之材料進行熱處理等，而使樹脂層20固化。
之後之工序如第1實施形態說明之那樣進行。藉此，完成圖1所示之半導體裝置1。如此，組合第2及第3實施形態亦能製造半導體裝置1。
雖然對本發明之若干實施形態進行了說明，但該等實施形態係作為示例而提出者，並不意圖限定發明之範圍。該等實施形態能以其它各種形態實施，且於不脫離發明主旨之範圍內，可進行各種省略、替換、變更。該等實施形態及其變化包含於發明範圍及主旨內，且同樣包含於申請專利範圍所記載之發明及其均等範圍內。相關申請引用 本案基於2019年8月27日申請之先行之日本專利申請第2019-154549號之優先權之利益，且要求其利益，其所有內容藉由引用之方式包含於本文中。
1:半導體裝置10:配線板11:絕緣基板12:配線13:接觸插塞14:金屬焊墊15:金屬凸塊16:阻焊劑20:樹脂層30:控制器晶片31:電極40:接著層50:間隔件60:NAND型記憶體晶片70:金屬焊墊80:接合線90:密封樹脂95:FAB膜100:壓接裝置105:抽吸孔130:晶圓環131:樹脂帶150:雷射振盪器160:切割刀片C:半導體晶DL:切割線F1:第1面F2:第2面F3:樹脂層20之上表面G:間隙T20:厚度T30:翹曲量W:半導體晶圓
圖1係表示第1實施形態之半導體裝置之構成例之剖視圖。  圖2(A)～(C)係表示第1實施形態之半導體裝置之製造方法之一例之立體圖。  圖3係接著圖2表示半導體裝置之製造方法之一例之剖視圖。  圖4係接著圖3表示半導體裝置之製造方法之一例之剖視圖。  圖5係接著圖4表示半導體裝置之製造方法之一例之剖視圖。  圖6係接著圖5表示半導體裝置之製造方法之一例之剖視圖。  圖7係接著圖6表示半導體裝置之製造方法之一例之剖視圖。  圖8係接著圖7表示半導體裝置之製造方法之一例之剖視圖。  圖9係表示第2實施形態之半導體裝置之製造方法之一例之剖視圖。  圖10係接著圖9表示半導體裝置之製造方法之一例之剖視圖。  圖11係接著圖10表示半導體裝置之製造方法之一例之剖視圖。  圖12係表示第3實施形態之半導體裝置之製造方法之一例之剖視圖。  圖13係接著圖12表示半導體裝置之製造方法之一例之剖視圖。  圖14係接著圖13表示半導體裝置之製造方法之一例之剖視圖。  圖15係接著圖14表示半導體裝置之製造方法之一例之剖視圖。  圖16係表示第4實施形態之半導體裝置之製造方法之一例之剖視圖。  圖17係接著圖16表示半導體裝置之製造方法之一例之剖視圖。  圖18係接著圖17表示半導體裝置之製造方法之一例之剖視圖。  圖19係接著圖18表示半導體裝置之製造方法之一例之剖視圖。
1:半導體裝置
10:配線板
11:絕緣基板
12:配線
13:接觸插塞
14:金屬焊墊
15:金屬凸塊
16:阻焊劑
20:樹脂層
30:控制器晶片
31:電極
40:接著層
50:間隔件
60:NAND型記憶體晶片
70:金屬焊墊
80:接合線
90:密封樹脂
F1:第1面
F2:第2面
F3:樹脂層20之上表面
T20:厚度
T30:翹曲量

Claims (7)

  1. 一種半導體裝置，其具備：第1基板，其設置有第1端子；有翹曲之第1半導體晶片，其於與上述第1基板對向之第1面上，具有與上述第1基板之上述第1端子連接之電極；非導電性之第1樹脂層，其設置於上述第1基板與上述第1半導體晶片之間，且覆蓋上述第1半導體晶片之與上述第1面為相反側之第2面整體；接著層，其設置於上述第1樹脂層之上表面上；第2半導體晶片，其設置於上述接著層上；及第2樹脂層，其覆蓋上述第2半導體晶片、上述第1樹脂層及上述第1基板之表面；其中上述第1樹脂層之上述上表面較上述第2面平坦。
  2. 如請求項1之半導體裝置，其進而具備間隔件，該間隔件設置於上述第1半導體晶片之周圍，具有與上述第1樹脂層之上述上表面之高度大致相等之高度，上述第2半導體晶片設置於上述第1樹脂層及上述間隔件之上。
  3. 如請求項1或2之半導體裝置，其中，上述第1樹脂層之厚度為上述第1半導體晶片之翹曲量以上。
  4. 一種半導體裝置之製造方法，其包括如下步驟：向設置有第1端子之 第1基板上供給非導電性之第1樹脂層之材料，以將設置在第1半導體晶片之第1面上之電極與上述第1端子對應之方式，於上述第1基板上積層有翹曲之第1半導體晶片，藉由對上述第1基板及上述第1半導體晶片施加壓力並進行加熱，而將上述第1半導體晶片之電極與上述第1基板之端子連接，於上述第1半導體晶片之與上述第1面為相反側之第2面整體覆蓋上述第1樹脂層之材料，於上述第1樹脂層之上表面上設置接著層，於上述接著層上設置第2半導體晶片，設置第2樹脂層，該第2樹脂層覆蓋上述第2半導體晶片、上述第1樹脂層及上述第1基板之表面，其中上述第1樹脂層之上述上表面較上述第2面平坦。
  5. 如請求項4之半導體裝置之製造方法，其中，使用壓接裝置將上述第1半導體晶片之電極與上述第1基板之端子連接後，要平坦化上述第1樹脂層時，藉由樹脂膜使上述第1樹脂層之上表面平坦化。
  6. 如請求項4或5之半導體裝置之製造方法，其中，使用壓接裝置將上述第1端子與上述電極連接後，於上述第2面與上述壓接裝置之間設置間隙，並向上述間隙內導入上述第1樹脂層之材料。
  7. 如請求項4或5之半導體裝置之製造方法，其中，使用壓接裝置將上述第1端子與上述電極連接後，再次向上述第2面上供給上述第1樹脂層之材料，上述壓接裝置以上述第1樹脂層之材料覆蓋上述第2面整體。
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US11961778B2 (en) * 2021-09-27 2024-04-16 Western Digital Technologies, Inc. Semiconductor device package having multi-layer molding compound and method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120068341A1 (en) * 2010-09-17 2012-03-22 Irvine Sensors Corporation Method for Depackaging Prepackaged Integrated Circuit Die and a Product from the Method
US20150214207A1 (en) * 2012-08-27 2015-07-30 Ps4 Luxco S.A.R.L. Chip stack, semiconductor devices having the same, and manufacturing methods for chip stack
TW201535538A (zh) * 2013-12-25 2015-09-16 Renesas Electronics Corp 半導體裝置之製造方法
TW201535668A (zh) * 2014-03-13 2015-09-16 Toshiba Kk 半導體裝置及半導體裝置之製造方法
TW201926623A (zh) * 2017-11-27 2019-07-01 力成科技股份有限公司 封裝結構及其製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4942140A (en) * 1987-03-25 1990-07-17 Mitsubishi Denki Kabushiki Kaisha Method of packaging semiconductor device
JP2010118554A (ja) 2008-11-13 2010-05-27 Nec Electronics Corp 半導体装置およびその製造方法
JP5112275B2 (ja) * 2008-12-16 2013-01-09 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
KR101598688B1 (ko) * 2014-03-25 2016-02-29 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
CN109983571A (zh) * 2016-11-21 2019-07-05 三菱电机株式会社 半导体装置
JP2019161113A (ja) * 2018-03-15 2019-09-19 東芝メモリ株式会社 半導体装置
JP2019165046A (ja) * 2018-03-19 2019-09-26 東芝メモリ株式会社 半導体装置およびその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120068341A1 (en) * 2010-09-17 2012-03-22 Irvine Sensors Corporation Method for Depackaging Prepackaged Integrated Circuit Die and a Product from the Method
US20150214207A1 (en) * 2012-08-27 2015-07-30 Ps4 Luxco S.A.R.L. Chip stack, semiconductor devices having the same, and manufacturing methods for chip stack
TW201535538A (zh) * 2013-12-25 2015-09-16 Renesas Electronics Corp 半導體裝置之製造方法
TW201535668A (zh) * 2014-03-13 2015-09-16 Toshiba Kk 半導體裝置及半導體裝置之製造方法
TW201926623A (zh) * 2017-11-27 2019-07-01 力成科技股份有限公司 封裝結構及其製造方法

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