TW201926623A - 封裝結構及其製造方法 - Google Patents

封裝結構及其製造方法 Download PDF

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Publication number
TW201926623A
TW201926623A TW107141429A TW107141429A TW201926623A TW 201926623 A TW201926623 A TW 201926623A TW 107141429 A TW107141429 A TW 107141429A TW 107141429 A TW107141429 A TW 107141429A TW 201926623 A TW201926623 A TW 201926623A
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Taiwan
Prior art keywords
conductive
circuit structure
redistribution circuit
die
sealing body
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TW107141429A
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English (en)
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TWI714913B (zh
Inventor
張簡上煜
徐宏欣
林南君
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力成科技股份有限公司
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Publication of TW201926623A publication Critical patent/TW201926623A/zh
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Publication of TWI714913B publication Critical patent/TWI714913B/zh

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)

Abstract

一種封裝結構包括重佈線路結構、晶粒、至少一連接模組、第一絕緣密封體、堆疊晶片以及第二絕緣密封體。晶粒配置並電性連接至重佈線路結構。連接模組配置於重佈線路結構上。連接模組具有保護層以及多個導電條。多個導電條嵌入保護層中。保護層包括對應於多個導電條的多個開口。第一絕緣密封體密封晶粒與連接模組。堆疊晶片配置於第一絕緣密封體與晶粒上。堆疊晶片電性連接至連接模組。第二絕緣密封體密封堆疊晶片。另提供一種封裝結構的製造方法。

Description

封裝結構及其製造方法
本發明通常是有關於一種封裝結構及其製造方法，且特別是有關於一種具有連接模組（connecting module）的封裝結構及其製造方法。
在近年來的半導體封裝技術的研究中已經開始關注於發展具有小體積、重量輕、高密度以及低製造成本的產品。對於多功能半導體封裝而言，已經使用一種用於堆疊晶片的技術，以提供封裝具有較大的儲存或執行數據的容量。在對具有改進期望特徵的多功能電子元件的需求快速增加下，實為本領域的技術人員的一大挑戰。
本發明提供一種封裝結構及其製造方法，可以在較低的製造成本下有效地減少封裝結構的高度。
本發明的封裝結構包括重佈線路結構、晶粒、至少一連接模組、第一絕緣密封體、堆疊晶片以及第二絕緣密封體。晶粒配置並電性連接至重佈線路結構。連接模組配置於重佈線路結構上。連接模組具有保護層以及多個導電條。多個導電條嵌入保護層中。保護層包括對應於多個導電條的多個開口。第一絕緣密封體密封晶粒與連接模組。堆疊晶片配置於第一絕緣密封體與晶粒上。堆疊晶片電性連接至連接模組。第二絕緣密封體密封堆疊晶片。
在本發明的一實施例中，前述的封裝結構更包括底膠，配置於重佈線路結構與晶粒之間。
本發明提供一種封裝結構的製造方法。製造方法至少包括以下步驟。提供載板。形成重佈線路結構於載板上。配置多個晶粒以及多個連接模組於重佈線路結構上。每一連接模組具有保護層以及嵌入保護層的多個導電條。形成第一絕緣密封體，以密封多個晶粒與多個連接模組。從重佈線路結構上移除載板。形成多個開口於多個連接模組的保護層中。多個開口對應至多個導電條。配置堆疊晶片於多個晶粒與相對於重佈線路結構的第一絕緣密封體上。堆疊晶片電性連接至多個連接模組。藉由第二密封體密封堆疊晶片。
在本發明的一實施例中，前述的製造方法更包括形成多個導電端子於相對於多個晶粒與多個連接模組的重佈線路結構上。
在本發明的一實施例中，前述的製造方法更包括執行切割製程。
在本發明的一實施例中，前述的製造方法更包括形成底膠於重佈線路結構與多個晶粒之間。
基於上述，容易預先製造的連接模組可以作為封裝結構內的垂直連接特徵。由於連接模組的厚度小，進而可以有效地縮小封裝結構的尺寸。此外，連接模組的使用可以導致在傳統封裝結構中免除額外的載板或較厚的銅柱，進而降低製造成本。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
下文將會附加標號以對本發明較佳實施例進行詳細描述，並以圖式說明。在可能的情況下，相同或相似的構件在圖式中將以相同的標號顯示。
圖1A至圖1K是依據本發明一些實施例的封裝結構10的製造方法的剖面示意圖。請參照圖1A，提供具有離型層102形成於其上的載板100。載板100可以是玻璃基板或玻璃支撐板。然而，本發明不限於此。其他合適的基板材料也可以被使用，只要所述材料能夠承載在其之上所形成的封裝結構且能夠承受後續的製程即可。離型層102可以包括光熱轉換（light to heat conversion, LTHC）材料、環氧樹脂（epoxy resin）、無機材料、有機聚合物材料或其他適宜的黏著材料。然而，本發明不限於此。在一些替代實施例中，可以使用其他適宜的離型層。
請參照圖1B，於載板100上形成重佈線路結構200。重佈線路結構200可以包括至少一介電層202、多個導電圖案204以及多個導通孔206。可以藉由適宜的製造技術如旋轉塗佈（spin-on coating）、化學氣相沉積（chemical vapor deposition, CVD）、電漿輔助化學氣相沉積（plasma-enhanced chemical vapor deposition, PECVD）或其他類似者，以形成介電層202。介電層202可以由氧化矽、氮化矽、碳化矽、氮氧化矽、聚酰亞胺、苯並環丁烯（benzocyclobutene, BCB）或其他類似者等的非有機或有機介電材料所製成。可以藉由濺鍍、蒸鍍、化學鍍（electro-less plating）或電鍍來形成導電圖案204以及導通孔206。導電圖案204以及導通孔206嵌入介電層202中。介電層202與導電圖案204可以交替形成。導通孔206穿過介電層202，以與導電圖案204相互電性連接。導電圖案204與導通孔206可以由銅、鋁、鎳、金、銀、錫、上述之組合、銅/鎳/金之複合結構，或其他適宜的導電材料所組成。
在圖1B的示例性實施例中，重佈線路結構200包括四個介電層202，然而，本發明對於介電層202的數量並不加以限制，並且可以基於電路的設計而進行調整。最上介電層202可以具有多個開口OP1，多個開口OP1暴露出最上導電圖案204，以於後續的製程中進行電性連接。最下介電層202暴露出部分的最下導電圖案204，使得最下導電圖案204可以經由導通孔206與其他導電圖案204進行內連線。
請參照圖1C，於重佈線路結構200上配置多個晶粒300以及多個連接模組500。晶粒300可以包括數位晶粒、類比晶粒或混合訊號晶粒。舉例而言，晶粒300可以是特殊應用積體電路（Application-Specific Integrated Circuit, ASIC）晶粒、邏輯晶粒，或其他適宜的晶粒。每一晶粒300包括半導體基板302、多個導電接墊304、鈍化層306以及多個導電連接器308。在一些實施例中，半導體基板302可以是具有主動元件（如電晶體或其他類似者）的矽基板，以及可以選擇性地形成被動元件（如電阻、電容、電感或其他類似者）於其中。導電接墊304分佈於半導體基板302上。導電接墊304可以包括鋁接墊、銅接墊或其他適宜的金屬接墊。於半導體基板302上形成鈍化層306，以部分覆蓋每一導電接墊304。換句話說，鈍化層306具有多個接觸開口，暴露出每一導電接墊304的至少一部分。鈍化層306可以是氧化矽層、氮化矽層、氮氧化矽層或是由其他適宜的聚合物材料或介電材料所形成的介電層。於導電接墊304上配置導電連接器308。舉例而言，導電連接器308可以部分地配置於鈍化層306的接觸開口中，以提供與導電接墊304的電性連接。在一些實施例中，每一導電連接器308可以包括導電栓塞308a與配置於導電栓塞308a上的導電凸塊308b。可以於導電接墊304上電鍍導電栓塞308a。電鍍製程是，舉例而言，電鍍、化學鍍、浸鍍（immersion plating）或其他類似者。導電栓塞308a可以包括銅、銅合金或其他類似者。導電凸塊308b可以由銅、鎳、錫、銀、上述之組合所製成。在一些實施例中，可以省略導電栓塞308a。換句話說，導電連接器308可以包括C2（晶片連接）凸塊或C4（控制塌陷高度晶片連接）凸塊。
在一些實施例中，每一晶粒300具有主動面300a以及相對於主動面300a的背面300b。如圖1C所示，以面朝下的方式配置晶粒300，使得晶粒300的主動面300a面向重佈線路結構200。晶粒300可以經由覆晶（flip-chip）接合電性連接至重佈線路結構200。舉例而言，可以於介電層202的部分開口OP1中配置晶粒300的導電連接器308，以與重佈線路結構200的導電圖案204直接接觸。這樣，可以實現晶粒300與重佈線路結構200之間的電性連接。重佈線路結構200可以被用於將電路訊號重新分佈至晶粒300，或從晶粒300將電路訊號重新分佈出去，且可以在比晶粒300更寬的區域中擴展。因此，在一些實施例中，重佈線路結構200可以被稱為是扇出式（fan-out）重佈線路結構。
在一些實施例中，於重佈線路結構200與晶粒300之間形成底膠400，以將導電連接器308與最上導電接墊204之間的耦合處保護且隔離。在一些實施例中，底膠400填充至最上介電層202的開口OP1中。底膠400可以藉由毛細填充膠（capillary underfill filling, CUF）的方式形成，且底膠400可以包括聚合物材料、樹脂或二氧化矽添加物。
在圖1C的示例性實施例中，配置連接模組500以圍繞晶粒300。每一連接模組500包括多個導電條502、多個阻障層504、多個導電帽506以及保護層508。導電條502可以形成圓柱形的形狀。然而，本發明不限於此。在一些替代性實施例中，導電條502可以使用多邊形柱或其他適宜的形狀。導電條502的材料包括銅、鋁、鎳、錫、金、銀、或上述之合金、或其他類似者。於導電條502上對應配置導電帽506，以進一步提升連接模組500與其他隨後形成元件之間的電性連接與導線接合能力。在一些實施例中，導電帽506的材料與導電條502的材料不同。舉例而言，導電帽506可以包括金或其他具有優異電性連接能力以及良好導線接合能力的金屬材料。在一些實施例中，阻障層504可以包括鎳、焊料、銀或其他適宜的導電材料。每一阻障層504夾於導電帽506與導電條502之間，以防止導電帽506與導電條502之間的原子擴散。舉例而言，當導電條502、阻障層504以及導電帽506分別由銅、鎳以及金所製成時，由鎳所形成的阻障層504可以防止導電條502中的銅原子從導電條502擴散至導電帽506中。導電帽506被銅汙染後會導致導電帽506容易氧化，進而導致導線接合能力變差。然而，藉由阻障層504的輔助，可以充分防止上述不利的影響。在一些實施例中，如果導電條502已經具有充分的導線接合能力接合隨後形成的元件，則可以省略導電帽506以及阻障層504。
在圖1C的示例性實施例中，導電條502、阻障層504以及導電帽506嵌入保護層508中。換句話說，保護層508保護導電條502、阻障層504以及導電帽506免受外部元件的影響。保護層508的材料可以包括聚合物、環氧樹脂、模塑化合物或其他適宜的介電材料。
在一些實施例中，每一連接模組500可以更包括多個導電凸塊510。於導電條502上對應配置導電凸塊510。於導電條502遠離導電帽506的那一面上配置導電凸塊510。導電凸塊510可以包括焊球或其他類似者。可以於重佈線路結構200另一部分的開口OP1中配置導電凸塊510，以於連接模組500與重佈線路結構200之間形成電性連接。導電凸塊510可以夾於導電條502與重佈線路結構200之間。
在一些實施例中，預先製造連接模組500在其放置於重佈線路結構200上之前。在一些實施例中，可以藉由晶粒接合器（die bonder）、晶片分揀機（chip sorter）或表面黏著技術（Surface Mount Technology, SMT）機器於重佈線路結構200上取放（pick-and-place）連接模組500。每一連接模組500中的導電條502的數量可以基於設計需求而進行調整。下面將結合圖2A至圖2D來討論連接模組500的配置。
圖2A至圖2D是圖1C中的連接模組500依據本發明各種實施例的上視示意圖。請參照圖2A，從上視圖看，每一連接模組500可以呈現矩形形狀。在一些實施例中，連接模組500具有5毫米（millimeter, mm）至15毫米的長度L，以及1.5毫米至2毫米的寬度W。如圖2A所示，導電帽506分佈於保護層508中，使得導電帽506之間的距離最小化，並同時維持導電帽506之間有效的電性隔離。當連接模組500為矩形時，可以於重佈線路結構200上取放多個連接模組500，以圍繞每一晶粒300的四個邊。
請參照圖2B，從上視圖看，每一連接模組500可以呈現正方形形狀。在一些實施例中，連接模組500的每一邊的長度L的範圍可以在5毫米至15毫米之間。當連接模組500為正方形時，可以於重佈線路結構200上取放多個連接模組500，以圍繞每一晶粒300的四個邊。
請參照圖2C，從上視圖看，每一連接模組500可以是環形。換句話說，可以藉由連接模組500包圍空穴C，以容納晶粒300。在一些實施例中，空穴C可以容納一個或多個晶粒300。也就是說，可以於重佈線路結構200上取放多個連接模組500，以圍繞不同晶粒300。
請參照圖2D，每一連接模組500可以包圍多個空穴C。在一些實施例中，每一空穴C可以容納一個或多個晶粒300。也就是說，可以於重佈線路結構200上取放一個連接模組500，以圍繞多個晶粒300，從而實現批次量產（batch production）。
請回頭參照圖1D，於重佈線路結構200上形成絕緣材料612，以密封晶粒300、底膠400以及連接模組500。絕緣材料612的材料可以與連接模組500的保護層508的材料不同。舉例而言，絕緣材料612可以包括藉由模塑製程形成的模塑化合物或絕緣材料如環氧樹脂、矽基樹脂（silicone）或其他適宜的樹脂。
請參照圖1E，在形成絕緣材料612後，從重佈線路結構200上移除離型層102以及載板100。如上面所提到，離型層102可以是光熱轉換層。在暴露於UV雷射下，離型層102與載板100可以從重佈線路結構200的最下介電層202與最下導電圖案204上被剝離分開。在一些實施例中，在移除離型層102與載板100後，對傳統的導線接合組件而言，如圖1E所示的結構可以被切割成條狀。
請參照圖1F，減少絕緣材料612的厚度，以形成第一絕緣密封體610。可以移除部分的絕緣材料612，以暴露出連接模組500的保護層508，以及可以選擇性地暴露出晶粒300的背面300b。同時，藉由保護層508仍然良好地保護著導電帽506。在一些實施例中，可以藉由平坦化製程移除絕緣材料612。平坦化製程包括，舉例而言，化學機械研磨製程（chemical-mechanical polishing, CMP）、機械研磨製程（mechanical grinding process）、蝕刻或其他適宜的製程。在一些實施例中，在暴露出連接模組500的保護層508以及晶粒300的背面300b後，連接模組500、絕緣材料612以及晶粒300可以進一步進行研磨，以減少隨後形成的封裝結構10的整體厚度。在平坦化製程後，於重佈線路結構200上配置第一絕緣密封體610，以側向密封晶粒300以及連接模組500。在一些實施例中，保護層508的頂面508a、第一絕緣密封體610的頂面610a以及晶粒300的背面300b相互實質上共面（coplanar）。如上面所提到，由於第一絕緣密封體610與連接模組500的保護層508由不同材料所製成，因此，這兩層被視為是兩個不同的層。換句話說，可以於兩個構件之間看見清楚的介面。應注意的是，在一些替代性實施例中，可以在如圖1E所示的剝離製程前，執行薄化製程。
請參照圖1G，於連接模組500的保護層508中形成多個開口OP2。在一些實施例中，藉由雷射鑽孔製程（laser drilling process）形成開口OP2。舉例而言，可以部分地移除位於導電帽506正上方的保護層508以形成開口OP2。換句話說，開口OP2的所在位置對應於導電帽506、阻障層504以及導電條502的所在位置。每一開口OP2暴露出連接模組500的每一導電帽506的至少一部分。
請參照圖1H，於晶粒300以及相對於重佈線路結構200的第一絕緣密封體610上配置堆疊晶片710。可以於晶粒300的背面300b以及第一絕緣密封體610的頂面610a放置堆疊晶片710。在一些實施例中，可以由多個晶片彼此相互堆疊構成堆疊晶片710。晶片可以包括具有非揮發性記憶體（non-volatile memory）的記憶晶片，如NAND型快閃記憶體（NAND flash）。然而，本發明不限於此。在一些替代性實施例中，堆疊晶片710的晶片可以是能夠執行其他功能的晶片，如邏輯功能、運算功能或其他類似者。在堆疊晶片710中，可以於兩相鄰晶片之間看見晶片黏著層，以增強這些兩相鄰的晶片之間的黏著力。
堆疊晶片710可以經由多條導線720電性連接至連接模組500的導電帽506。舉例而言，在於晶粒300以及第一絕緣密封體610上配置堆疊晶片710後，可以經由打線接合製程形成多條導線720。導線720的一端連接至堆疊晶片710的至少一晶片。另一方面，導線720的另一端延伸至保護層508的開口OP2中，以連接至導電帽506。導線720的材料可以包括金、鋁或其他適宜的導電材料。在一些實施例中，導線720的材料與導電帽506的材料相同。
請參照圖1I，於第一絕緣密封體610與連接模組500上形成第二絕緣密封體620，以密封堆疊晶片710以及導線720。第二絕緣密封體620的材料可以與第一絕緣密封體610的材料相同或不同。舉例而言，第二絕緣密封體620的材料可以包括環氧樹脂、模塑化合物或其他適宜的絕緣材料。在一些實施例中，第二絕緣密封體620的材料可以為濕氣吸收率較低的材料。可以藉由壓縮成型（compression molding）、轉注成型（transfer molding）或其他適宜的密封製程形成第二絕緣密封體620。如圖1I所示，第二絕緣密封體620填充至連接模組500的保護層508的開口OP2中，以保護導線720位於開口OP2中的線段。第二絕緣密封體620提供給堆疊晶片710與導線720物理支撐、機械保護以及電性和環境隔離。換句話說，堆疊晶片710與導線720嵌入第二絕緣密封體620中。
請參照圖1J，於相對於晶粒300與連接模組500的重佈線路結構200上形成多個導電端子800。在一些實施例中，於重佈線路結構200的最下導電圖案204上配置導電端子800。換句話說，重佈線路結構200的最下導電圖案204可以被稱為凸塊底金屬（under-ball metallization, UBM）圖案。可以藉由植球製程（ball placement process）以及/或回焊製程（reflow process）形成導電端子800。導電端子800可以為導電凸塊，如焊球。然而，本發明不限於此。在一些替代性實施例中，導電端子800可以基於設計需求而使用其他可能的形式或形狀。舉例而言，導電端子800可以使用導電柱或導電栓塞（conductive posts）的形式。
請參照圖1K，在形成導電端子800後，進行切割（singulation）製程，以獲得多個封裝結構10。切割製程包括，舉例而言，以旋切刀（rotating blade）或雷射光束切割。
藉由使用容易預先製造的連接模組500作為封裝結構10內的垂直連接特徵，由於連接模組500的厚度小，進而可以有效地縮小封裝結構10的尺寸。此外，連接模組500的使用可以導致在傳統封裝結構中免除額外的載板或較厚的銅柱，進而降低製造成本。
圖3是依據本發明一些替代實施例的封裝結構20的剖面示意圖。請參照圖3，圖3中的封裝結構20類似於圖1K中的封裝結構10，因此採用相同的標號來表示近似的元件，且詳細內容於此不加以贅述。圖3的封裝結構20與圖1K的封裝結構10差別在於：封裝結構20更包括於晶粒300與連接模組500之間配置多個虛設晶粒910。可以在形成第一絕緣密封體610之前，於重佈線路結構200上配置虛設晶粒910。可以藉由取放製程（pick-and-place process）於重佈線路結構200上放置虛設晶粒910。如圖3所示，第一絕緣密封體610的頂面610a、虛設晶粒910的頂面910a、晶粒300的背面300b以及保護層508的頂面508a相互實質上共面。
在一些實施例中，虛設晶粒910為電性浮接（electrically floating）。虛設晶粒910可以與重佈線路結構200、晶粒300、連接模組500以及堆疊晶片710電性絕緣。在一些實施例中，虛設晶粒910可以沒有主動元件。換句話說，虛設晶粒910可以不對封裝結構20的運作做出貢獻。
在一些實施例中，可以經由黏著層920，將每一虛設晶粒910黏著至重佈線路結構200上。舉例而言，可以於虛設晶粒910與重佈線路結構200之間配置黏著層920。黏著層920可以保護重佈線路結構200免於由於放置虛設晶粒910而導致的壓痕，且可以最小化在重佈線路結構200上的虛設晶粒910的位移。在一些實施例中，黏著層920可以包括晶粒黏著膜（die attach film, DAF）或其他類似的材料。
在一些實施例中，若晶粒300的尺寸小於堆疊晶片710，則虛設晶粒910可以作為隔板。也就是說，可以使用虛設晶粒910，以提供堆疊晶片710額外的物理支撐。應注意的是，雖然圖3繪示的為兩個虛設晶粒910，本發明不限於此。可以基於堆疊晶片710與晶粒300的尺寸而調整虛設晶粒910的數量。
綜上所述，容易預先製造的連接模組可以作為封裝結構內的垂直連接特徵。由於連接模組的厚度小，進而可以有效地縮小封裝結構的尺寸。此外，連接模組的使用可以導致在傳統封裝結構中免除額外的載板或較厚的銅柱，進而降低製造成本。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10、20‧‧‧封裝結構
100‧‧‧載板
102‧‧‧離型層
200‧‧‧重佈線路結構
202‧‧‧介電層
204‧‧‧導電圖案
206‧‧‧導通孔
300‧‧‧晶粒
300a‧‧‧主動面
300b‧‧‧背面
302‧‧‧半導體基板
304‧‧‧導電接墊
306‧‧‧鈍化層
308‧‧‧導電連接器
308a‧‧‧導電栓塞
308b、510‧‧‧導電凸塊
400‧‧‧底膠
500‧‧‧連接模組
502‧‧‧導電條
504‧‧‧阻障層
506‧‧‧導電帽
508‧‧‧保護層
508a、610a、910a‧‧‧頂面
610‧‧‧第一絕緣密封體
612‧‧‧絕緣材料
620‧‧‧第二絕緣密封體
710‧‧‧堆疊晶片
720‧‧‧導線
800‧‧‧導電端子
910‧‧‧虛設晶粒
920‧‧‧黏著層
C‧‧‧空穴
L‧‧‧長度
OP1、OP2‧‧‧開口
W‧‧‧寬度
圖1A至圖1K是依據本發明一些實施例的封裝結構的製造方法的剖面示意圖。 圖2A至圖2D是圖1C中的連接模組依據本發明各種實施例的上視示意圖。 圖3是依據本發明一些替代實施例的封裝結構的剖面示意圖。

Claims (10)

  1. 一種封裝結構，包括： 重佈線路結構； 晶粒，配置並電性連接至所述重佈線路結構； 至少一連接模組，配置於所述重佈線路結構上，所述連接模組具有保護層以及多個導電條，其中所述多個導電條嵌入所述保護層中，且所述保護層包括對應於所述多個導電條的多個開口； 第一絕緣密封體，密封所述晶粒與所述連接模組； 堆疊晶片，配置於所述第一絕緣密封體與所述晶粒上，其中所述堆疊晶片電性連接至所述連接模組；以及 第二絕緣密封體，密封所述堆疊晶片。
  2. 如申請專利範圍第1項所述的封裝結構，更包括多個導電端子，配置於相對於所述晶粒與所述連接模組的所述重佈線路結構上。
  3. 如申請專利範圍第1項所述的封裝結構，更包括多條導線，嵌入所述第二絕緣密封體中，其中所述堆疊晶片經由所述多條導線電性連接至所述連接模組，且所述多條導線延伸至所述保護層的所述多個開口中。
  4. 如申請專利範圍第1項所述的封裝結構，更包括多個虛設晶粒，配置於所述晶粒與所述連接模組之間。
  5. 如申請專利範圍第1項所述的封裝結構，其中： 所述保護層的材料與所述第一絕緣密封體的材料不同； 所述連接模組更包括多個導電凸塊，夾於所述多個導電條與所述重佈線路結構之間； 所述連接模組更包括多個導電帽，對應配置於所述多個導電條上，且所述保護層的所述多個開口暴露出每一所述導電帽的至少一部分； 所述多個導電條的材料與所述多個導電帽的材料不同；或 所述第二絕緣密封體填充至所述保護層的所述多個開口中。
  6. 一種封裝結構的製造方法，包括： 提供載板； 形成重佈線路結構於所述載板上； 配置多個晶粒以及多個連接模組於所述重佈線路結構上，每一所述連接模組具有保護層以及多個導電條，其中所述多個導電條嵌入所述保護層中； 形成第一絕緣密封體，以密封所述多個晶粒與所述多個連接模組； 從所述重佈線路結構上移除所述載板； 形成多個開口於所述多個連接模組的所述保護層中，其中所述多個開口對應至所述多個導電條； 配置堆疊晶片於所述多個晶粒與相對於所述重佈線路結構的所述第一絕緣密封體上，其中所述堆疊晶片電性連接至所述多個連接模組；以及 藉由所述第二密封體密封所述堆疊晶片。
  7. 如申請專利範圍第6項所述的製造方法，更包括形成多條導線嵌入所述第二絕緣密封體中，其中所述堆疊晶片經由所述多條導線電性連接至所述多個連接模組，且所述多條導線延伸至所述保護層的所述多個開口中。
  8. 如申請專利範圍第6項所述的製造方法，更包括放置多個虛設晶粒於所述多個晶粒與所述多個連接模組之間。
  9. 如申請專利範圍第6項所述的製造方法，其中所述晶粒具有主動面以及相對於主動面的背面，所述晶粒包括多個導電連接器位於所述主動面，且所述第一絕緣密封體的形成步驟包括： 形成絕緣材料於所述重佈線路結構上，以覆蓋所述多個晶粒與所述多個連接模組；以及 移除部分的所述絕緣材料，以暴露出所述多個連接模組的所述保護層與所述多個晶粒的所述背面。
  10. 如申請專利範圍第6項所述的製造方法，其中： 所述多個晶粒經由覆晶接合電性連接至所述重佈線路結構； 每一所述連接模組更包括多個導電凸塊，且所述多個連接模組經由取放製程配置於所述重佈線路結構上，使得所述多個導電凸塊與所述重佈線路結構直接接觸；或 每一所述連接模組更包括多個導電帽，對應配置於所述多個導電條上，且所述保護層的所述多個開口暴露出每一所述導電帽的至少一部分。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI798519B (zh) * 2019-08-27 2023-04-11 日商鎧俠股份有限公司 半導體裝置及其製造方法

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9922964B1 (en) * 2016-09-19 2018-03-20 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with dummy die
US11948917B2 (en) * 2019-04-23 2024-04-02 Intel Corporation Die over mold stacked semiconductor package
US11383970B2 (en) * 2019-07-09 2022-07-12 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and related methods
TWI711131B (zh) 2019-12-31 2020-11-21 力成科技股份有限公司 晶片封裝結構
TWI768294B (zh) * 2019-12-31 2022-06-21 力成科技股份有限公司 封裝結構及其製造方法
TW202143401A (zh) 2020-05-08 2021-11-16 力成科技股份有限公司 半導體封裝方法及其結構
JP2022014121A (ja) * 2020-07-06 2022-01-19 キオクシア株式会社 半導体装置およびその製造方法
KR20220006807A (ko) 2020-07-09 2022-01-18 에스케이하이닉스 주식회사 적층 반도체 칩을 포함하는 반도체 패키지
KR20220008168A (ko) 2020-07-13 2022-01-20 삼성전자주식회사 반도체 패키지
KR20220015632A (ko) 2020-07-31 2022-02-08 에스케이하이닉스 주식회사 적층 반도체 칩을 포함하는 반도체 패키지
CN111968949B (zh) * 2020-08-27 2022-05-24 青岛歌尔微电子研究院有限公司 芯片封装工艺及封装芯片
JP2022129462A (ja) * 2021-02-25 2022-09-06 キオクシア株式会社 半導体装置および半導体装置の製造方法
KR20220150093A (ko) * 2021-05-03 2022-11-10 삼성전자주식회사 반도체 패키지

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8021976B2 (en) * 2002-10-15 2011-09-20 Megica Corporation Method of wire bonding over active area of a semiconductor circuit
US6358836B1 (en) * 2000-06-16 2002-03-19 Industrial Technology Research Institute Wafer level package incorporating elastomeric pads in dummy plugs
JP4012527B2 (ja) * 2004-07-14 2007-11-21 日本無線株式会社 電子部品の製造方法
US9082806B2 (en) * 2008-12-12 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
CN101866915B (zh) * 2009-04-15 2015-08-19 三星电子株式会社 集成电路装置及其操作方法、存储器存储装置及电子系统
US8624374B2 (en) * 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
KR101855294B1 (ko) * 2010-06-10 2018-05-08 삼성전자주식회사 반도체 패키지
US8941222B2 (en) * 2010-11-11 2015-01-27 Advanced Semiconductor Engineering Inc. Wafer level semiconductor package and manufacturing methods thereof
JP5646415B2 (ja) * 2011-08-31 2014-12-24 株式会社東芝 半導体パッケージ
US9613830B2 (en) 2011-12-30 2017-04-04 Deca Technologies Inc. Fully molded peripheral package on package device
US20130249101A1 (en) * 2012-03-23 2013-09-26 Stats Chippac, Ltd. Semiconductor Method of Device of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units
US9385006B2 (en) * 2012-06-21 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming an embedded SOP fan-out package
US9391041B2 (en) * 2012-10-19 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out wafer level package structure
CN203118928U (zh) * 2012-12-13 2013-08-07 欣兴电子股份有限公司 封装结构
US9368438B2 (en) * 2012-12-28 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package (PoP) bonding structures
US8980691B2 (en) * 2013-06-28 2015-03-17 Stats Chippac, Ltd. Semiconductor device and method of forming low profile 3D fan-out package
KR101550496B1 (ko) * 2013-07-24 2015-09-04 에스티에스반도체통신 주식회사 적층형 반도체패키지 및 그 제조방법
TWI517269B (zh) * 2013-09-27 2016-01-11 矽品精密工業股份有限公司 層疊式封裝結構及其製法
JP6273362B2 (ja) 2013-12-23 2018-01-31 インテル コーポレイション パッケージ構造上のパッケージ及びこれを製造するための方法
US9653442B2 (en) * 2014-01-17 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and methods of forming same
US20150287697A1 (en) * 2014-04-02 2015-10-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Method
US9527723B2 (en) 2014-03-13 2016-12-27 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming microelectromechanical systems (MEMS) package
TWI517343B (zh) 2014-03-25 2016-01-11 恆勁科技股份有限公司 覆晶堆疊封裝結構及其製作方法
US9881859B2 (en) 2014-05-09 2018-01-30 Qualcomm Incorporated Substrate block for PoP package
CN104064551B (zh) 2014-06-05 2018-01-16 华为技术有限公司 一种芯片堆叠封装结构和电子设备
US10453785B2 (en) 2014-08-07 2019-10-22 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming double-sided fan-out wafer level package
KR102165024B1 (ko) 2014-09-26 2020-10-13 인텔 코포레이션 와이어-접합 멀티-다이 스택을 구비한 집적 회로 패키지
US9941207B2 (en) 2014-10-24 2018-04-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of fabricating 3D package with short cycle time and high yield
TWI654723B (zh) * 2015-02-06 2019-03-21 矽品精密工業股份有限公司 封裝結構之製法
US9613931B2 (en) * 2015-04-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (SIP) having dummy dies and methods of making the same
US9837484B2 (en) * 2015-05-27 2017-12-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming substrate including embedded component with symmetrical structure
US9679873B2 (en) * 2015-06-18 2017-06-13 Qualcomm Incorporated Low profile integrated circuit (IC) package comprising a plurality of dies
KR101809521B1 (ko) * 2015-09-04 2017-12-18 주식회사 네패스 반도체 패키지 및 그 제조방법
TWI566356B (zh) * 2015-10-15 2017-01-11 力成科技股份有限公司 封裝結構及其製造方法
US10483211B2 (en) * 2016-02-22 2019-11-19 Mediatek Inc. Fan-out package structure and method for forming the same
US10797038B2 (en) * 2016-02-25 2020-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and rework process for the same
TWM537310U (zh) * 2016-11-14 2017-02-21 Jorjin Tech Inc ３ｄ多晶片模組封裝結構（一）

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI798519B (zh) * 2019-08-27 2023-04-11 日商鎧俠股份有限公司 半導體裝置及其製造方法

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