CN109841606A - 封装结构及其制造方法 - Google Patents

封装结构及其制造方法 Download PDF

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Publication number
CN109841606A
CN109841606A CN201811423732.6A CN201811423732A CN109841606A CN 109841606 A CN109841606 A CN 109841606A CN 201811423732 A CN201811423732 A CN 201811423732A CN 109841606 A CN109841606 A CN 109841606A
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China
Prior art keywords
link block
crystal grain
insulating seal
conductive
protective layer
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CN201811423732.6A
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English (en)
Inventor
张简上煜
徐宏欣
林南君
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Powertech Technology Inc
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Powertech Technology Inc
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Publication of CN109841606A publication Critical patent/CN109841606A/zh
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
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Abstract

本发明提供一种封装结构包括重布线路结构、晶粒、至少一连接模块、第一绝缘密封体、堆叠芯片以及第二绝缘密封体。晶粒配置并电性连接至重布线路结构。连接模块配置于重布线路结构上。连接模块包括保护层以及嵌入保护层中的多个导电条。第一绝缘密封体密封晶粒与连接模块。堆叠芯片配置于第一绝缘密封体与晶粒上。堆叠芯片电性连接至连接模块。第二绝缘密封体密封堆叠芯片。还提供一种封装结构的制造方法。

Description

封装结构及其制造方法
技术领域
本发明涉及一种封装结构及其制造方法，尤其涉及一种具有连接模块(connecting module)的封装结构及其制造方法。
背景技术
在近年来的半导体封装技术的研究中已经开始关注于发展具有小体积、重量轻、高密度以及低制造成本的产品。对于多功能半导体封装而言，已经使用一种用于堆叠芯片的技术，以提供封装具有较大的储存或执行数据的容量。在对具有改进期望特征的多功能电子元件的需求快速增加下，实为本领域的技术人员的一大挑战。
发明内容
本发明提供一种封装结构及其制造方法，可以在较低的制造成本下有效地减少封装结构的高度。
本发明的封装结构包括重布线路结构、晶粒、至少一连接模块、第一绝缘密封体、堆叠芯片以及第二绝缘密封体。晶粒配置并电性连接至重布线路结构。连接模块配置于重布线路结构上。连接模块包括保护层以及嵌入保护层中的多个导电条。第一绝缘密封体密封晶粒与连接模块。堆叠芯片配置于第一绝缘密封体与晶粒上。堆叠芯片电性连接至连接模块。第二绝缘密封体密封堆叠芯片。
在本发明的一实施例中，前述的封装结构还包括粘着层。粘着层夹于所述晶粒的背面与堆叠芯片之间。
在本发明的一实施例中，前述的多个导电帽的材料包括金。
本发明提供一种封装结构的制造方法。制造方法至少包括以下步骤。提供载板。配置多个晶粒以及多个连接模块于载板上。每一所述连接模块包括保护层以及多个嵌入所述保护层中的导电条。于载板上形成第一绝缘密封体，以密封多个晶粒与多个连接模块。于多个晶粒、多个连接模块以及第一绝缘密封体上形成重布线路结构。从多个晶粒、连接模块以及第一绝缘密封体上移除载板。于多个晶粒与相对于重布线路结构的第一绝缘密封体上配置堆叠芯片。堆叠芯片电性连接至多个连接模块。通过第二密封体密封堆叠芯片。
在本发明的一实施例中，前述的制造方法还包括形成多个导电端子于相对于多个晶粒与多个连接模块的重布线路结构上。
在本发明的一实施例中，前述的制造方法还包括执行切割制造。
基于上述，容易预先制造的连接模块可以作为封装结构内的垂直连接特征。由于连接模块的厚度小，进而可以有效地缩小封装结构的尺寸。此外，连接模块的使用可以导致在传统封装结构中免除额外的载板或较厚的铜柱，进而降低制造成本。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附附图作详细说明如下。
附图说明
图1A至图1J是依据本发明一些实施例的封装结构的制造方法的剖面示意图。
【符号说明】
10：封装结构
100：载板
102：离型层
200：晶粒
200a：主动面
200b：背面
202：半导体基板
204：导电接垫
206：钝化层
208：导电连接器
208a、302a、306b、308a、308b、512a、510a、510b：表面
300：连接模块
302：导电条
304：阻障层
306：导电帽
308：保护层
400：粘着层
510：第一绝缘密封体
512：绝缘材料
520：第二绝缘密封体
600：重布线路结构
602：介电层
602a、602b：开口
604：导电图案
606：导通孔
710：堆叠芯片
720：导线
800：导电端子
具体实施方式
下文将会附加标号以对本发明较佳实施例进行详细描述，并以附图说明。在可能的情况下，相同或相似的构件在附图中将以相同的标号显示。
图1A至图1J是依据本发明一些实施例的封装结构10的制造方法的剖面示意图。请参照图1A，提供具有离型层102形成于其上的载板100。载板100可以是玻璃基板或玻璃支撑板。然而，本发明不限于此。其他合适的基板材料也可以被使用，只要所述材料能够承载在其之上所形成的封装结构且能够承受后续的制造即可。离型层102可以包括光热转换(light to heat conversion,LTHC)材料、环氧树脂(epoxy resin)、无机材料、有机聚合物材料或其他适宜的粘着材料。然而，本发明不限于此。在一些替代实施例中，可以使用其他适宜的离型层。
请参照图1B，于离型层102与载板100上配置多个晶粒200以及多个连接模块300。晶粒200可以包括数字晶粒、模拟晶粒或混合信号晶粒。举例而言，晶粒200可以是特殊应用集成电路(Application-Specific Integrated Circuit,ASIC)晶粒、逻辑晶粒，或其他适宜的晶粒。每一晶粒200包括半导体基板202、多个导电接垫204、钝化层206以及多个导电连接器208。在一些实施例中，半导体基板202可以是包括主动元件(如晶体管或其他类似者)的硅基板，以及可以选择性地形成被动元件(如电阻、电容、电感或其他类似者)于其中。导电接垫204分布于半导体基板202上。导电接垫204可以包括铝接垫、铜接垫或其他适宜的金属接垫。于半导体基板202上形成钝化层206，以部分覆盖每一导电接垫204。换句话说，钝化层206具有多个接触开口，暴露出每一导电接垫204的至少一部分。钝化层206可以是氧化硅层、氮化硅层、氮氧化硅层或是由其他适宜的聚合物材料或介电材料所形成的介电层。于导电接垫204上配置导电连接器208。举例而言，导电连接器208可以延伸至钝化层206的接触开口中，以提供与导电接垫204的电性连接。在一些实施例中，可以于导电接垫204上电镀导电连接器208。电镀制造是，举例而言，电镀、化学镀、浸镀(immersion plating)或其他类似者。导电连接器208可以采用导电栓塞(conductive posts)、导电柱或导电凸块的形式。导电连接器208的材料包括铜、铝、锡、金、银、上述的合金或其他适宜的导电材料。
在一些实施例中，每一晶粒200具有主动面200a以及相对于主动面200a的背面200b。如图1B所示，以面朝上的方式配置晶粒200。换句话说，晶粒200的主动面200a从载板100上远离，而晶粒200的背面200b面向载板100。在一些实施例中，晶粒200可以经由粘着层400附接在载板100上。举例而言，可以于晶粒200的背面200b配置粘着层400，使得粘着层400夹于晶粒200的半导体基板202与离型层102之间。粘着层400可以暂时增强晶粒200与离型层102之间的粘着力，以防止晶粒位移。在一些实施例中，粘着层400可以为干膜，且可以经由层压制造(lamination process)粘着于离型层102上。或者，可以经由涂布制造将粘着层400(液体形式)的溶液涂布至离型层102上。接着，将溶液干燥或固化，以形成粘着层400的固体层。粘着层400可以由B阶(B-stage)材料所制成，举例而言，粘着层400可以包括由树脂构成的晶粒粘着膜(die attach film,DAF)。然而，本发明不限于此。在一些替代实施例中，可以使用其他具有粘着特性的材料来作为粘着层400的材料。在一些实施例中，粘着层400为可选的。当未使用粘着层400时，晶粒200可以直接附接于离型层102上。
如图1B所示，沿至少一晶粒200的周围配置连接模块300。每一连接模块300包括多个导电条302、多个阻障层304、多个导电帽306以及保护层308。导电条302可以形成圆柱形的形状。然而，本发明不限于此。在一些替代性实施例中，导电条302可以使用多边形柱或其他适宜的形状。导电条302的材料包括铜、铝、镍、锡、金、银、上述的合金、或其他类似者。于导电条302上对应配置导电帽306。于导电条302上配置导电帽306以进一步提升连接模块300与其他随后形成元件之间的电性连接与导线接合能力。在一些实施例中，导电帽306的材料与导电条302的材料不同。举例而言，导电帽306可以包括金或其他具有优异电性连接能力以及良好导线接合能力的金属材料。在一些实施例中，阻障层304可以包括镍、焊料、银或其他适宜的导电材料。每一阻障层304夹于导电帽306与导电条302之间，以防止导电帽306与导电条302之间的原子扩散。举例而言，当导电条302、阻障层304以及导电帽306分别由铜、镍以及金所制成时，由镍所形成的阻障层304可以防止导电条302中的铜原子从导电条302扩散至导电帽306中。导电帽306被铜污染后会导致导电帽306容易氧化，进而导致导线接合能力变差。然而，通过阻障层304的辅助，可以充分防止上述不利的影响。在一些实施例中，如果导电条302已经具有充分的导线接合能力接合随后形成的元件，则可以省略导电帽306以及阻障层304。
如图1B所示，导电条302、阻障层304以及导电帽306嵌入保护层308中。然而，保护层308暴露出每一导电条302的至少一部分以及每一导电帽306的至少一部分。举例而言，保护层308可以侧向密封导电条302、阻障层304以及导电帽306。同时，可以通过保护层308将导电条302的表面302a暴露出来。在一些实施例中，导电条302的表面302a实质上与保护层308的第一表面308a共面(coplanar)。类似地，可以通过保护层308将导电帽306的表面306b暴露出来。也就是说，导电帽306的表面306b实质上与保护层308的第二表面308b(保护层308中相对于第一表面308a的表面)共面。应注意的是，图1B中的配置仅为示例性示出，而本发明不限于此。在一些替代实施例中，保护层308可以覆盖导电条302的表面302a，使得导电条302未被暴露出来。换句话说，保护层308的第一表面308a可以位于比导电条302的顶表面302a还要高的高度。在一些实施例中，保护层308的材料包括聚合物、环氧树脂、模塑化合物或其他适宜的介电材料。
在一些实施例中，预先制造连接模块300，在其放置于载板100上之前。在一些实施例中，可以通过取放制造(pick-and-place process)将连接模块300放置于载板100上。举例而言，可以通过晶粒接合器(die bonder)、芯片分拣机(chip sorter)或表面粘着技术(Surface Mount Technology,SMT)机器于载板100及离型层102上取放(pick-and-place)连接模块300。如图1B所示，以导电帽306面向载板100的方式放置连接模块300。也就是说，以导电帽306比导电条302更靠近载板100的方式放置连接模块300。每一连接模块300中的导电条302的数量可以依设计需求而调整。从上方来看(未示出)，导电条302分布于保护层308中，使得导电条302之间的距离最小化，并同时维持导电条302之间有效的电性隔离。在一些实施例中，从上方来看，连接模块300可以呈现正方形形状、矩形形状、环形形状或其他几何形状。
请参照图1C，于载板100与离型层102上形成绝缘材料512，以覆盖晶粒200与连接模块300。换句话说，绝缘材料512密封晶粒200与连接模块300。在一些实施例中，绝缘材料512的材料可以与连接模块300的保护层308的材料不同。举例而言，绝缘材料512可以包括通过模塑制造形成的模塑化合物或绝缘材料(如环氧树脂、硅基树脂(silicone)或其他适宜的树脂)。在一些实施例中，通过覆盖成型制造(over-molding process)形成绝缘材料512，使得晶粒200与连接模块300没有被暴露出来。举例而言，如图1C所示，绝缘材料512的顶表面512a位于比保护层308的第一表面308a、导电条302的表面302a以及导电连接器208的顶表面208a还要高的高度。
请参照图1D，减少绝缘材料512的厚度，以形成第一绝缘密封体510。举例而言，移除部分的绝缘材料512直到晶粒200的导电连接器208以及连接模块300的导电条302此两者被暴露出来。在一些实施例中，可以经由平坦化制造移除绝缘材料512。平坦化制造包括，举例而言，化学机械研磨制造(chemical-mechanical polishing,CMP)、机械研磨制造(mechanical grinding process)、蚀刻或其他适宜的制造。在一些实施例中，平坦化制造可以更进一步研磨连接模块300、绝缘材料512以及晶粒200，以减少随后形成的封装结构10的整体厚度。在平坦化制造后，于载板100与离型层102上形成第一绝缘密封体510，以侧向密封晶粒200以及连接模块300。在一些实施例中，保护层308的第一表面308a、第一绝缘密封体510的第一表面510a、导电条302的表面302a以及导电连接器208的顶表面208a相互实质上共面。如上面所提到，由于第一绝缘密封体510与连接模块300的保护层308由不同材料所制成，第一绝缘密封体510与保护层308被视为是两个不同的层。换句话说，可以于第一绝缘密封体510与保护层308之间看见清楚的界面。
请参照图1E，于晶粒200、连接模块300以及第一绝缘密封体510上形成重布线路结构600。重布线路结构600可以包括至少一介电层602、多个导电图案604以及多个导通孔606。可以通过适宜的制造技术如旋转涂布(spin-on coating)、化学气相沉积(chemicalvapor deposition,CVD)、等离子体辅助化学气相沉积(plasma-enhanced chemical vapordeposition,PECVD)或其他类似者，以形成介电层602。介电层602可以由氧化硅、氮化硅、碳化硅、氮氧化硅、聚酰亚胺、苯并环丁烯(benzocyclobutene,BCB)或其他类似者等的非有机或有机介电材料所制成。另一方面，可以通过溅镀、蒸镀、化学镀(electro-less plating)或电镀来形成导电图案604以及导通孔606。导电图案604以及导通孔606嵌入介电层602中。介电层602与导电图案604可以交替堆叠。导通孔606穿过介电层602，以与导电图案604相互电性连接。导电图案604与导通孔606可以由铜、铝、镍、金、银、锡、上述的组合、铜/镍/金的复合结构，或其他适宜的导电材料所组成。
如图1E所示，重布线路结构600包括四个介电层602，然而，本发明对于介电层602的数量并不加以限制，并且可以基于电路的设计而进行调整。最下介电层602可以具有多个接触开口602a。多个接触开口602a部分暴露出连接模块300的导电条302与晶粒200的导电连接器208。导通孔606配置于接触开口602a中可以与连接模块300的导电条302以及晶粒200的导电连接器208直接接触。换句话说，晶粒200的导电连接器208与重布线路结构600直接接触，以提供晶粒200与重布线路结构600之间的电性连接。类似地，连接模块300的导电条302也与重布线路结构600直接接触，以提供连接模块300与重布线路结构600之间的电性连接。中间介电层602暴露出部分的最下导电图案604，使得最下导电图案604可以经由导通孔606与其他导电图案604(举例而言，中间导电图案604)电性连接。最上介电层602具有多个接触开口602b。多个接触开口602b暴露出部分的中间导电图案604。最上导通孔606可以延伸至接触开口602b，以与最上导电图案604以及中间导电图案604电性连接。另一方面，为了后续制造中的电性连接，于最上介电层602上配置最上导电图案604。在一些实施例中，最上导电图案604可以被称为凸块底金属(under-ball metallization,UBM)图案。
在一些实施例中，重布线路结构600可以被用于将电路信号重新分布至晶粒200，或从晶粒200将电路信号重新分布出去，且可以在比晶粒200更宽的区域中扩展。因此，在一些实施例中，重布线路结构600可以被称为是扇出式(fan-out)重布线路结构。
请参照图1F，从晶粒200、连接模块300、粘着层400以及第一绝缘密封体510上移除离型层102以及载板100。如上面所提到，离型层102可以是光热转换层。在暴露于UV激光下，离型层102与载板100可以从导电帽306、连接模块300的保护层308、粘着层400以及第一绝缘密封体510上被剥离分开。在移除载板100与离型层102时，暴露出保护层308的第二表面308b、导电帽306的表面306b以及第一绝缘密封体510的第二表面510b(第一绝缘密封体510中相对于第一表面510a的表面)。如图1F所示，导电帽306的表面306b、保护层308的第二表面308b以及第一绝缘密封体510的第二表面510b实质上相互共面。
请参照图1G，将图1F所示出的结构上下翻转，使得晶粒200、连接模块300以及第一绝缘密封体510显示为配置于重布线路结构600上/上方。之后，于晶粒200及相对于重布线路结构600的第一绝缘密封体510上配置堆叠芯片710。举例而言，可以于粘着层400及第一绝缘密封体510的第二表面510b上放置堆叠芯片710。也就是说，粘着层400夹于堆叠芯片710与晶粒200的背面200b之间。在一些实施例中，可以由多个芯片彼此相互堆叠构成堆叠芯片710。芯片可以包括具有非易失性存储器(non-volatile memory)的存储芯片，如NAND型快闪存储器(NAND flash)。然而，本发明不限于此。在一些替代性实施例中，堆叠芯片710的芯片可以是能够执行其他功能的芯片，如逻辑功能、运算功能或其他类似者。在堆叠芯片710中，可以于两相邻芯片之间看见芯片粘着层，以增强这些两相邻的芯片之间的粘着力。
堆叠芯片710可以经由多条导线720电性连接至连接模块300的导电帽306。举例而言，在于粘着层400、第一绝缘密封体510上配置堆叠芯片710后，可以经由打线接合制造形成多条导线720。导线720的一端连接至堆叠芯片710的至少一芯片。另一方面，导线720的另一端连接至导电帽306的表面306b。导线720的材料可以包括金、铝或其他适宜的导电材料。在一些实施例中，导线720的材料与导电帽306的材料相同。
请参照图1H，于第一绝缘密封体510与连接模块300上形成第二绝缘密封体520，以密封堆叠芯片710以及导线720。第二绝缘密封体520的材料可以与第一绝缘密封体510的材料相同或不同。举例而言，第二绝缘密封体520的材料可以包括环氧树脂、模塑化合物或其他适宜的绝缘材料。在一些实施例中，第二绝缘密封体520的材料可以为湿气吸收率较低的材料。可以通过压缩成型(compression molding)、转注成型(transfer molding)或其他适宜的密封制造形成第二绝缘密封体520。第二绝缘密封体520提供给堆叠芯片710与导线720物理支撑、机械保护以及电性和环境隔离。换句话说，堆叠芯片710与导线720嵌入第二绝缘密封体520中。
请参照图1I，于相对于晶粒200与连接模块300的重布线路结构600上形成多个导电端子800。在一些实施例中，于重布线路结构600的UBM图案(如图1I所示的最下导电图案604)上配置导电端子800。可以通过植球制造(ball placement process)和/或回焊制造(reflow process)形成导电端子800。导电端子800可以为导电凸块，如焊球。然而，本发明不限于此。在一些替代性实施例中，导电端子800可以基于设计需求而使用其他可能的形式或形状。举例而言，导电端子800可以使用导电柱或导电栓塞的形式。
请参照图1J，在形成导电端子800后，进行切割(singulation)制造，以获得多个封装结构10。切割制造包括，举例而言，以旋切刀(rotating blade)或激光光束切割。
综上所述，容易预先制造的连接模块可以作为封装结构内的垂直连接特征。由于连接模块的厚度小，进而可以有效地缩小封装结构的尺寸。此外，连接模块的使用可以导致在传统封装结构中免除额外的载板或较厚的铜柱，进而降低制造成本。
虽然本发明已以实施例揭示如上，然其并非用以限定本发明，任何所属技术领域中的技术人员，在不脱离本发明的精神和范围内，当可作些许的更改与润饰，故本发明的保护范围当视权利要求所界定的为准。

Claims (10)

1.一种封装结构，包括：
重布线路结构；
晶粒，配置并电性连接至所述重布线路结构；
至少一连接模块，配置于所述重布线路结构上，其中所述连接模块包括保护层以及多个导电条，所述多个导电条嵌入所述保护层中；
第一绝缘密封体，密封所述晶粒与所述连接模块；
堆叠芯片，配置于所述第一绝缘密封体与所述晶粒上，所述堆叠芯片电性连接至所述连接模块；以及
第二绝缘密封体，密封所述堆叠芯片。
2.根据权利要求1所述的封装结构，还包括多个导电端子，配置于相对于所述晶粒与所述连接模块的所述重布线路结构上。
3.根据权利要求1所述的封装结构，还包括多条导线，嵌入所述第二绝缘密封体中，其中所述堆叠芯片经由所述多条导线电性连接至所述连接模块。
4.根据权利要求1所述的封装结构，其中所述连接模块还包括多个导电帽，对应配置于所述多个导电条上，且所述保护层暴露出每一所述导电帽的至少一部分，且：
所述多个导电条的材料与所述多个导电帽的材料不同；或
所述多个导电帽的表面、所述保护层的表面以及所述第一绝缘密封体的表面实质上共面。
5.根据权利要求1所述的封装结构，其中：
所述晶粒具有主动面以及相对于所述主动面的背面，所述晶粒包括多个导电连接器，位于所述主动面上，且所述多个导电连接器与所述重布线路结构直接接触；或
所述保护层的材料与所述第一绝缘密封体的材料不同。
6.一种封装结构的制造方法，包括：
提供载板；
配置多个晶粒以及多个连接模块于所述载板上，其中每一所述连接模块包括保护层以及多个导电条，所述多个导电条嵌入所述保护层中；
形成第一绝缘密封体于所述载板上，以密封所述多个晶粒与所述多个连接模块；
形成重布线路结构于所述多个晶粒、所述多个连接模块以及所述第一绝缘密封体上；
从所述多个晶粒、所述多个连接模块以及所述第一绝缘密封体上移除所述载板；
配置堆叠芯片于所述多个晶粒与相对于所述重布线路结构的所述第一绝缘密封体上，其中所述堆叠芯片电性连接至所述多个连接模块；以及
通过第二绝缘密封体密封所述堆叠芯片。
7.根据权利要求6所述的制造方法，还包括形成多条导线嵌入所述第二绝缘密封体中，其中所述堆叠芯片经由所述多条导线电性连接至所述多个连接模块。
8.根据权利要求6所述的制造方法，其中所述多个连接模块经由取放制造配置于所述载板上。
9.根据权利要求6所述的制造方法，其中：
每一所述连接模块还包括多个导电帽，对应配置于所述多个导电条上，且所述保护层暴露出每一所述导电帽的至少一部分；且
所述多个连接模块配置于所述载板上，使得所述多个导电帽面向所述载板。
10.根据权利要求6所述的制造方法，其中所述晶粒具有主动面以及相对于所述主动面的背面，所述晶粒包括多个导电连接器位于所述主动面，且所述第一绝缘密封体的形成步骤包括：
形成绝缘材料于所述载板上，以覆盖所述多个晶粒与所述多个连接模块；以及
移除部分的所述绝缘材料，以暴露出所述多个晶粒的所述多个导电连接器与所述多个连接模块的所述多个导电条。
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