TW201926601A - 封裝結構及其製造方法 - Google Patents

封裝結構及其製造方法 Download PDF

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Publication number
TW201926601A
TW201926601A TW107141430A TW107141430A TW201926601A TW 201926601 A TW201926601 A TW 201926601A TW 107141430 A TW107141430 A TW 107141430A TW 107141430 A TW107141430 A TW 107141430A TW 201926601 A TW201926601 A TW 201926601A
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Taiwan
Prior art keywords
conductive
sealing body
conductive structures
insulating sealing
die
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TW107141430A
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English (en)
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TWI677066B (zh
Inventor
張簡上煜
徐宏欣
林南君
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力成科技股份有限公司
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Publication of TW201926601A publication Critical patent/TW201926601A/zh
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Publication of TWI677066B publication Critical patent/TWI677066B/zh

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Wire Bonding (AREA)

Abstract

一種封裝結構，其包括重佈線路結構、晶粒、多個導電結構、第一絕緣密封體、晶片堆疊體以及第二絕緣密封體。晶粒配置在重佈線路結構上且電性連接至重佈線路結構。導電結構位於重佈線路結構上且電性連接至重佈線路結構。這些導電結構環繞晶粒。第一絕緣密封體包覆晶粒及導電結構。第一絕緣密封體包括暴露出多個導電結構的頂表面的多個開口。晶片堆疊體配置在第一絕緣密封體與晶粒上。晶片堆疊體電性連接至多個導電結構。第二絕緣密封體包覆晶片堆疊體。

Description

封裝結構及其製造方法
本發明提供一種封裝結構及其製造方法，且特別是有關於一種具有電性連接至晶片堆疊體的短導電結構的封裝結構及其製造方法。
近年來半導體封裝技術的發展，著重在提供體積更小、重量更輕、積體度(integration level)更高與製造成本更低的產品。對於多功能的半導體封裝，堆疊晶片的技術已被用於提供具有更大儲存或處理數據之容量的封裝。對於改善所需的多功能之電子元件的需求快速增加，為本領域研究人員的一大挑戰。
本發明提供一種封裝結構及其製造方法，可有效降低封裝結構的高度且具有較低的製造成本。
本發明的封裝結構包括重佈線路結構、晶粒、多個導電結構、第一絕緣密封體、晶片堆疊體以及第二絕緣密封體。晶粒配置在重佈線路結構上且電性連接至重佈線路結構。導電結構位於重佈線路結構上且電性連接至重佈線路結構。這些導電結構環繞晶粒。第一絕緣密封體包覆晶粒及導電結構。第一絕緣密封體包括暴露出多個導電結構的頂表面的多個開口。晶片堆疊體配置在第一絕緣密封體與晶粒上。晶片堆疊體電性連接至多個導電結構。第二絕緣密封體包覆晶片堆疊體。
在本發明的封裝結構的製造方法包括以下步驟。提供載板。形成重佈線路結構在載板上。配置多個導電結構及多個晶粒在重佈線路結構上。這些導電結構環繞這些晶粒。形成第一絕緣密封體以包覆多個晶粒及多個導電結構。形成多個開口在第一絕緣密封體中，以暴露出多個導電結構的頂表面。從重佈線路結構移除載板。配置晶片堆疊體在相對於重佈線路結構的多個晶粒及第一絕緣密封體上。晶片堆疊體電性連接至多個導電結構。藉由第二絕緣密封體包覆晶片堆疊體。
基於上述，導電結構可作為封裝結構內的垂直連接特徵。由於導電結構的厚度小，可以有效地減少封裝結構的尺寸。此外，藉由短的導電結構的匹配，可以省略傳統封裝結構中的額外的載板或較厚銅柱，進而降低製造成本。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1A至圖1L是依據本發明一些實施例的封裝結構10的製造方法的剖面示意圖。請參照圖1A，提供載板100，載板100具有去黏合層102。載板100可以是玻璃基板或玻璃支撐板。然而，本發明不限於此。可以採用其他適宜的基板材料，只要所述材料能夠承載在其之上所形成的封裝結構且能夠承受後續的製程即可。去黏合層102可以包括光熱轉換（light to heat conversion，LTHC）材料、環氧樹脂（epoxy resin）、無機材料、有機聚合物材料或其他適宜的黏著材料。然而，本發明不以此為限，在一些替代實施例中可使用其他適宜的去黏合層。
請參照圖1B，形成重佈線路結構200在載板100上。重佈線路結構200可包括至少一層介電層202、多個導電圖案204與多個導通孔206。可以藉由適宜的製造技術，如：旋轉塗佈（spin-on coating）、化學氣相沉積（chemical vapor deposition；CVD）、電漿輔助化學氣相沉積（plasma-enhanced chemical vapor deposition；PECVD）或其他類似者，以形成介電層202。介電層202可以由氧化矽、氮化矽、碳化矽、氮氧化矽、聚酰亞胺、苯並環丁烯等的非有機或有機介電材料所製成。另一方面，可以藉由濺鍍、蒸鍍、化學鍍（electro-less plating）或電鍍（electroplating）來形成導電圖案204以及導通孔206。導電圖案204與導通孔206嵌入於介電層202中。介電層202與導電圖案204可以交替地堆疊。導通孔206可以穿過介電層202，以使導電圖案204彼此電性連接。導電圖案204與導通孔206可以由銅、鋁、鎳、金、銀、錫、上述之組合、銅/鎳/金的複合結構或是其他適宜的導電材料所組成。
請參照圖1B，重佈線路結構200包括四層的介電層202。然而，本發明對於介電層202的數量並不加以限制，並且可以基於電路的設計而進行調整。頂部的介電層202具有多個開口OP1，開口OP1暴露出部分頂部的導電圖案204，以用於後續製程的電性連接。為了進一步電性連接至其他電路元件，底部的介電層202暴露出部分的底部的導電圖案204。
請參照圖1C，導電結構300設置在相對於載板100的重佈線路結構200上。在一些實施例中，導電結構300可鍍析於重佈線路結構200的頂部的導電圖案204上。鍍析製程可以為電鍍、化學鍍、浸鍍（immersion plating）或類似之方法。在一些實施例中，導電結構300可以形成圓柱狀。也就是說，導電結構300可以包括導電栓塞（conductive post）、導電柱（conductive pillar）或其他相似物。然而，本發明不限於此。在一些替代實施例中，導電結構300可以採用多邊形柱或其他適宜形狀。在一些實施例中，每個導電結構300是多層複合結構。每一個導電結構300包括第一層302、堆疊於第一層302上的第二層304以及堆疊於第二層304上的第三層306。第一層302的材料、第二層304的材料與第三層306的材料可以彼此不相同。舉例來說，第一層302的材料包括銅、鋁、錫、銀、上述之合金或其他相似材料。第二層304的材料包括鎳、焊料或其他相似材料。第三層的材料包括銅、金或其他具有優異的導電性和良好的打線接合性的金屬材料。在一些實施例中，第一層302、第二層304和第三層306可以形成銅/鎳/金複合結構。第三層306能增強導電結構300與其他後續形成的元件之間的電性連接。另一方面，第二層304夾在第一層302和第三層306之間，用以作為第一層302和第三層306之間的阻擋層。舉例來說，當第一層302、第二層304和第三層306是銅/鎳/金複合結構時，由鎳形成的第二層304可以防止第一層302的銅原子擴散到第三層306中。若第三層306受到銅污染會使第三層306容易氧化，進而導致不良的打線接合性。然而，藉由第二層304作為阻擋層，可以充分防止上述的不利影響。雖然圖1C中的導電結構300由三層所構成，但本發明不以此為限。在一些替代實施例中，每個導電結構300可以是單層結構，或由兩層、四層或更多層所構成的多層結構。
如圖1C所示，導電結構300填入部分的重佈線路結構200的頂介電層202的開口OP1。舉例而言，導電結構300的第一層302可以部分地位於頂部的介電層202的開口OP1內，以在重佈線路結構200和導電結構300之間形成電性連接。第一層302可以與重佈線路結構200的頂導電圖案204具有物理接觸。
請參照圖1D，配置多個晶粒400在相對於載板100的重佈線路結構200上。晶粒可以透過取放製程（pick and place process）以配置在重佈線路結構200上。在一些實施例中，放置晶粒400以使導電結構300環繞晶粒400。導電結構300沿著至少一個晶粒400的週圍設置。晶粒400可包括數位晶粒、類比晶粒或混合訊號（mixed signal）晶粒。舉例來說，晶粒400可以是特殊應用積體電路（Application-Specific Integrated Circuit；ASIC）晶粒、邏輯晶粒、或其他適宜的晶粒。每一個晶粒400包括半導體基板402、多個導電接墊404、保護層（passivation layer）406與多個導電連接件408。在一些實施例中，半導體基板402可以是具有主動元件（如：電晶體或其他類似者）及選擇性地具有被動元件（如：電阻、電容、電感或其他類似者）形成於其上的矽基板。導電接墊404分佈在半導體基板402上。導電接墊404可以包括鋁接墊，銅接墊或其他適宜的金屬接墊。保護層406形成在半導體基板402上，並部分地覆蓋每個導電接墊404。換言之，保護層406具有多個接觸開口，其露出每個導電接墊404的至少一部分。保護層406可以是氧化矽層、氮化矽層、氮氧化矽層、或由聚合材料或其他適宜的介電材料所形成的介電層。導電連接件408設置在導電接墊404上。舉例而言，導電連接件408可以延伸到保護層406的接觸開口中，以提供與導電接墊404的電性連接。在一些實施例中，每個導電連接件408可以包括導電柱體408a和設置在導電柱體408a上的導電凸塊408b。導電柱體408a可以鍍析於導電接墊404上。鍍析製程可以為電鍍、化學鍍、浸鍍或類似之方法。導電柱體408a可包括銅、銅合金或其他相似材料等。另一方面，導電凸塊408b可以由銅、鎳、錫、銀或上述之組合所構成。在一些實施例中，可以省略導電柱體408a。導電連接件408可以包括晶片連接（Chip Connection；C2）凸塊或控制塌陷高度晶片連接（Controlled Collapse Chip Connection；C4）凸塊。
每一個晶粒具有主動面400a及相對於主動面400a的一個背面400b。如圖1D所示，晶粒400以面朝下的方式設置，使得晶粒400的主動面400a面向重佈線路結構200。晶粒400可以藉由覆晶接合以連接重佈線路結構200。晶粒400的導電連接件408可以設置在頂介電層202的開口OP1的另一部分中，並可以與重佈線路結構200的頂部的導電圖案204物理性接觸。如此一來，可實現晶粒400與重佈線路結構200之間的電性連接。在一些實施例中，重佈線路結構200可用於傳遞電信號到/從晶粒400，且可在較晶粒400更寬的區域中擴展。因此，在一些實施例中，重佈線路結構200可以被稱為「扇出重佈線路結構（fan-out redistribution structure）」。
如圖1D所示，導電結構300的厚度t300 小於晶粒400的厚度t400 。舉例而言，晶粒400的背面400b至重佈線路結構200的高度高於導電結構300的頂表面300a至重佈線路結構200的高度。
在一些實施例中，形成底膠500在重佈線路結構200和晶粒400之間，以保護和隔離導電連接件408和頂導電圖案204之間的耦合。在一些實施例中，底膠500填充到頂部的介電層202的開口OP1中。底膠500可以由包括聚合物材料、樹脂或二氧化矽添加劑的毛細填充膠（capillary underfill filling；CUF）製成。
儘管圖1C及圖1D繪示出了於放置晶粒400之前形成導電結構300，但本發明不以此為限。在一些替代實施例中，可以於形成導電結構300之前，將晶粒400放置在重佈線路結構200上。也就是說，圖1C及圖1D所示的製造步驟是可互換的。
請參照圖1E，在重佈線路結構200上形成絕緣材料612，以包覆導電結構300、晶粒400和底膠500。絕緣材料612可以包括由模塑製程所形成的模塑化合物或絕緣材料（如：環氧樹脂、矽基樹脂（silicone）或其他適宜的樹脂）。在一些實施例中，可以藉由包覆射出成形製程（over-molding process）形成絕緣材料612，以使導電結構300和晶粒400不會被露出。如圖1E所示，絕緣材料612的頂表面612a的水平高度高於導電結構300的頂表面300a和晶粒400的背面400b的水平高度。
請參照圖1F，減少絕緣材料612的厚度，以形成第一絕緣密封體610。可以將絕緣材料612的一部分移除，以暴露出晶粒400的背面400b，同時導電結構300仍完全被第一絕緣密封體610完全密封。在一些實施例中，移除絕緣材料612可藉由平坦化製程。平坦化製程可以是化學機械研磨（CMP）、機械研磨、蝕刻製程或其他適宜的製程。平坦化製程可以進一步研磨絕緣材料612和晶粒400，以減少隨後形成的封裝結構10的總厚度。在平坦化製程之後，將第一絕緣密封體610設置在重佈線路結構200上，以橫向包覆晶粒400。第一絕緣密封體610也包覆導電結構300的側壁與頂表面300a。第一絕緣密封體610的頂表面610a和晶粒400的背面400b基本上可以彼此共面。另一方面，第一絕緣密封體610的頂表面610a具有高於導電結構300的頂表面300a的水平高度。第一絕緣密封體610的厚度t610 可以大於每一個導電結構300的厚度t300 。
請參照圖1G，在第一密封絕緣體610中形成多個開口OP2。在一些實施例中，開口OP2是藉由雷射鑽孔製程形成。位於導電結構300上方的第一絕緣密封體610可以被部分地去除以形成開口OP2。如圖1G所示，開口OP2的位置對應於導電結構300的位置。每個開口OP2可以暴露出每個導電結構300的一部分。開口OP2可以暴露出導電結構300的頂表面300a。在一些實施例中，開口OP2可以部分地暴露出導電結構300的第三層306。
請參照圖1H，去黏合層102及載板100從重佈線路結構200移除。當去黏合層102是光熱轉換層（Light-To-Heat-Conversion Release Coating；LTHC）時，去黏合層102及載體100在暴露於UV雷射光時可以從重佈線路結構200的底部的介電層202及底部的導電圖案204剝離並分離。如圖1H所示的結構可以鋸成框條式（Strip Form），以用於傳統的打線接合組件。
請參照圖1I，晶片堆疊體是710配置在相對於重佈線路結構200的第一絕緣密封體610與晶粒400上。晶片堆疊體710可位在晶粒400的背面400b和第一絕緣密封體610的頂表面610a上。晶片堆疊體710可以藉由多個晶片彼此頂部堆疊形成。晶片可以是具有非揮發性記憶體的記憶體晶片，例如NAND快取（NAND flash）記憶體。然而，本發明不限於此。在一些替代性實施例中，晶片堆疊體710的晶片可以是執行其他功能的晶片，例如邏輯功能、計算功能或其他相似功能。晶片黏著層（未繪示）可以設置在晶片堆疊710中的兩個相鄰晶片之間，以提升兩個晶片之間的黏著。
晶片堆疊體710可以藉由多個導線720電性連接至導電結構300。當晶片堆疊體710配置在晶粒400和第一絕緣密封體610上時，多條導電線720可藉由打線接合製程所形成。導線720的一端耦合到晶片堆疊體710的至少一個晶片，導線720延伸到第一絕緣密封體610的開口OP2中，導線720的另一端耦合到導電結構300的第三層306。導線720的材料可包括金、鋁或其他適宜的導電材料。在一些實施例中，導線720的材料與導電結構300的第三層306的材料相同。
請參照圖1J，第二絕緣密封體620形成在第一絕緣密封體610和晶粒400上，以包覆晶片堆疊體710和導線720，以使晶片堆疊體710和導電線720嵌入於第二絕緣密封體620中。第二絕緣密封體620的材料可以與第一絕緣密封體610的材料相同或不同。第二絕緣密封體620的材料可以是環氧樹脂、模塑化合物或其他適宜的絕緣材料。在一些實施例中，第二絕緣密封體620的材料可具有低濕氣吸收率。第二絕緣密封體620可以藉由壓縮模塑（compression molding）、轉移模塑（transfer molding）或密封製程的製程所形成。如圖1J所示，第二絕緣密封體620可以填充第一絕緣密封體610的開口OP2，以保護位於開口OP2中的導線720的區段。第二絕緣密封體620可以與導電結構300的一部分物理性地接觸。第二絕緣密封體620為晶片堆疊體710和導線720提供物理支撐、機械保護以及電與環境隔離。
請參照圖1K，多個導電端子800形成在相對於晶粒400及導電結構300的重佈線路結構200上。在一些實施例中，導電端子800位於重佈線路結構200的底導電圖案204上。換言之，重佈線路結構200的底部的導電圖案204可以作為凸塊底金屬（under-ball metallurgy；UBM）圖案。導電端子800可以藉由植球製程（ball placement process）及/或回焊製程（reflow process）來形成。導電端子800可以是焊球等的導電凸塊。然而，本發明不限於此。在一些替代性的實施例中，導電端子800可以依據設計上的需求採用其他可能的形式和形狀。舉例來說，導電端子800可以是導電柱或導電栓塞（conductive post）。
請參照圖1L，在形成導電端子800後，進行切單製程（singulation process）以形成多個封裝結構10。切單製程包括例如用旋轉刀片或雷射光束進行切割。
綜上所述，導電結構可作為封裝結構內的垂直連接特徵。由於導電結構的厚度小，可以有效地減少封裝結構的尺寸。此外，藉由短的導電結構的匹配，可以省略傳統封裝結構中的額外的載板或較厚銅柱，進而降低製造成本。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10‧‧‧封裝結構
100‧‧‧載板
102‧‧‧去黏合層
200‧‧‧重佈線路結構
202‧‧‧介電層
204‧‧‧導電圖案
206‧‧‧導通孔
300‧‧‧導電結構
300a、612a‧‧‧頂表面
302‧‧‧第一層
304‧‧‧第二層
306‧‧‧第三層
OP1、OP2‧‧‧開口
400‧‧‧晶粒
400a‧‧‧主動面
400b‧‧‧背面
402‧‧‧半導體基板
404‧‧‧導電接墊
406‧‧‧保護層
408‧‧‧導電連接件
408a‧‧‧導電柱體
408b‧‧‧導電凸塊
500‧‧‧底膠
610‧‧‧第一絕緣密封體
612‧‧‧絕緣材料
620‧‧‧第二絕緣密封體
t300、t400、t610‧‧‧厚度
710‧‧‧晶片堆疊體
720‧‧‧導線
800‧‧‧導電端子
圖1A至圖1L是依據本發明一些實施例的封裝結構的製造方法的剖面示意圖。

Claims (10)

  1. 一種封裝結構，包括： 重佈線路結構； 晶粒，配置在所述重佈線路結構上且電性連接至所述重佈線路結構； 多個導電結構，位於所述重佈線路結構上且電性連接至所述重佈線路結構，其中所述多個導電結構環繞所述晶粒； 第一絕緣密封體，包覆所述晶粒及所述多個導電結構，其中所述第一絕緣密封體包括暴露出所述多個導電結構的頂表面的多個開口； 晶片堆疊體，配置在所述第一絕緣密封體與所述晶粒上，其中所述晶片堆疊體電性連接至所述多個導電結構；以及 第二絕緣密封體，包覆所述晶片堆疊體。
  2. 如申請專利範圍第1項所述的封裝結構，更包括： 多條導線，嵌於所述第二絕緣密封體中，其中所述晶片堆疊體藉由所述多條導線電性連接至所述多個導電結構，且所述多條導線延伸至所述第一絕緣密封體的所述多個開口內。
  3. 如申請專利範圍第1項所述的封裝結構，其中所述第二絕緣密封體填入所述第一絕緣密封體的所述多個開口內。
  4. 如申請專利範圍第1項所述的封裝結構，其中每一所述多個導電結構包括第一層、堆疊於所述第一層上的第二層以及堆疊於所述第二層上的第三層，且所述第一絕緣密封體的所述多個開口暴露出所述第三層。
  5. 如申請專利範圍第4項所述的封裝結構，其中所述第三層的材料包括金。
  6. 如申請專利範圍第1項所述的封裝結構，其中所述第一絕緣密封體的厚度大於每一所述多個導電結構的厚度。
  7. 如申請專利範圍第1項所述的封裝結構，其中所述第一絕緣密封體的頂表面高於所述多個導電結構的頂表面。
  8. 如申請專利範圍第1項所述的封裝結構，其中所述晶粒具有主動面及相對於所述主動面的背面，所述晶粒包括位於所述主動面上的多個導電連接件，且所述多個導電連接件直接接觸所述重佈線路結構。
  9. 一種封裝結構的製造方法，包括： 提供載板； 形成重佈線路結構在所述載板上； 配置多個導電結構及多個晶粒在所述重佈線路結構上，其中所述多個導電結構環繞所述多個晶粒； 形成第一絕緣密封體，以包覆所述多個晶粒及所述多個導電結構； 形成多個開口在所述第一絕緣密封體中，以暴露出所述多個導電結構的頂表面； 從所述重佈線路結構移除所述載板； 配置晶片堆疊體在相對於所述重佈線路結構的所述多個晶粒及所述第一絕緣密封體上，其中所述晶片堆疊體電性連接至所述多個導電結構；以及 藉由第二絕緣密封體包覆所述晶片堆疊體。
  10. 如申請專利範圍第9項所述的封裝結構的製造方法，其中每一所述多個晶粒具有主動面及相對於所述主動面的背面，且形成所述第一絕緣密封封體的步驟包括： 形成絕緣材料在所述重佈線路結構上，以覆蓋所述多個晶粒及所述多個導電結構；以及 移除部分的所述絕緣材料，以暴露出所述多個晶粒的所述多個背面，其中所述多個導電結構不被露出。
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