JP6820307B2 - パッケージ構造体及びパッケージ構造体の製造方法 - Google Patents

パッケージ構造体及びパッケージ構造体の製造方法 Download PDF

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JP6820307B2
JP6820307B2 JP2018214378A JP2018214378A JP6820307B2 JP 6820307 B2 JP6820307 B2 JP 6820307B2 JP 2018214378 A JP2018214378 A JP 2018214378A JP 2018214378 A JP2018214378 A JP 2018214378A JP 6820307 B2 JP6820307 B2 JP 6820307B2
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conductive
layer
die
insulating
package structure
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JP2019096873A (ja
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上▲ユ▼ 張簡
上▲ユ▼ 張簡
宏欣 徐
宏欣 徐
南君 林
南君 林
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力成科技股▲分▼有限公司
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
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Description

本開示は一般に、パッケージ構造体及びパッケージ構造体の製造方法に関するものであり、特に、チップ積層体に電気的に接続される短い導電構造体を有するパッケージ構造体及びパッケージ構造体の製造方法に関するものである。
近年の半導体パッケージ技術の開発では、より小さな体積で、より軽量で、集積レベルが高く、製造コストが低い製品の輸送に着目されてきた。多機能半導体パッケージに対して、チップを積層する技術を用いて、データを保存し処理する容量がより大きなパッケージが提供されている。所望機能を増やすことが当該分野における研究者にとって挑戦となり、多機能電子部品に対する需要が急速に高まってきた。
本開示は、パッケージ構造体の高さが効果的に低くなり、パッケージ構造体の製造コストがより低くなる、パッケージ構造体及びパッケージ構造体の製造方法を提供する。
本開示は、再分配構造体と、ダイと、複数の導電構造体と、第１絶縁カプセル材と、チップ積層体と、第２絶縁カプセル材と、を含むパッケージ構造体を提供する。ダイは、再分配構造体上に配置され、再分配構造体に電気的に接続される。導電構造体は、再分配構造体上に配置され、再分配構造体に電気的に接続される。導電構造体はダイを取り囲む。第１絶縁カプセル材は、ダイ及び導電構造体をカプセル化する。第１絶縁構造体は、導電構造体の上面を露出させる複数の開口部を含む。チップ積層体は、第１絶縁カプセル材及びダイの上に配置される。チップ積層体は、導電構造体に電気的に接続される。第２絶縁カプセル材は、チップ積層体をカプセル化する。
本開示は、パッケージ構造体の製造方法を提供する。本方法は、少なくとも以下のステップを含む。キャリアを提供する。キャリア上に再分配構造体を形成する。複数のダイ及び複数の導電構造体を再分配構造体上に配置する。導電構造体はダイを取り囲む。第１絶縁カプセル材を形成してダイ及び導電構造体をカプセル化する。第１絶縁カプセル材に複数の開口部を形成して、導電構造体の上面を露出させる。キャリアを再分配構造体から除去する。チップ積層体を、ダイ及び第１絶縁カプセル材の、再分配構造体とは反対側に配置する。チップ積層体は導電構造体に電気的に接続される。チップ積層体を第２絶縁カプセル材によってカプセル化する。
上記記載に基づいて、導電構造体は、パッケージ構造体内の垂直接続機構としての機能を果たすことができる。導電構造体の厚さが薄くなるため、パッケージ構造体のサイズを有効に減少させることができる。また、短い導電構造体の適応によって、従来のパッケージ構造体における、付加的なキャリアを除去し又は銅ピラーをより薄くすることができ、これにより、製造コストを削減する。
上記記載をよりわかりやすくするため、添付の図面とともにいくつかの実施形態を以下詳細に説明する。
本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。 本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。 本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。 本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。 本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。 本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。 本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。 本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。 本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。 本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。 本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。 本開示のある実施形態に従うパッケージ構造体の製造方法を示す模式断面図である。
本開示を更に理解するために図面を添付する。添付の図面をこの明細書に組み込んで、当該明細書の一部を構成する。図面は、本開示の例示的実施形態を示し、本開示の原理を本明細書と共に説明するのに役立つ。
これから、本発明の好ましい実施形態に詳細に言及する。本発明の実施例は、添付の図面に図示されている。可能な限り、同一又は類似の部分に言及するために同一の参照番号を図面及び明細書で使用する。
図１Ａから図１Ｌは、本開示のある実施形態に従うパッケージ構造体１０の製造方法を示す模式断面図である。図１Ａを参照して、その上に剥離層１０２が形成される、キャリア１００が提供される。キャリア１００をガラス基板又はガラス支持板とすることができる。しかしながら、これらの構成は本開示を限定すると解釈されるものではない。その上のパッケージ構造体を構造的に支持しながら続いて起こるプロセスに耐え得る限り、他の適切な基板材料を適合し得る。剥離層１０２は、光熱変換（ＬＴＨＣ）材料、エポキシ樹脂、無機材料、有機高分子材料又は他の適切な接着材を含み得る。しかしながら、本開示はこれらの構成に限定されるものではなく、ある代替的実施形態では、他の適切な剥離層を使用することができる。
図１Ｂを参照して、キャリア１００上に再分配構造体２００を形成する。再分配構造体２００は、少なくとも一層の誘電層２０２と、複数の導電パターン２０４と、複数の導電ビア２０６とを含み得る。スピンオンコーティング、化学蒸着（ＣＶＤ）又はプラズマＣＶＤ（ＰＥＣＶＤ）等の適切な製造技術で誘電層２０２を形成することができる。誘電層２０２を、シリコン酸化物、シリコン窒化物、炭化珪素、オキシ窒化ケイ素、ポリイミド又はベンゾシクロブテン（ＢＣＢ）等の、無機又は有機誘電材料で製造することができる。他方では、導電パターン２０４及び導電ビア２０６を、スパッタリング、エバポレーション、無電解メッキ又は電気メッキによって形成することができる。導電パターン２０４及び導電ビア２０６は、誘電層２０２に埋め込まれる。誘電層２０２及び導電パターン２０４を交互に積層させることができる。導電ビア２０６は、誘電層２０２を貫通し、導電パターン２０４を互いに電気的に接続する。導電パターン２０４及び導電ビア２０６を、銅、アルミニウム、ニッケル、金、銀、スズ若しくはこれらの組み合わせ、銅／ニッケル／金の複合構造又は他の適切な導電材料で製造し得る。
図１Ｂに示すように、再分配層２００は４つの誘電層２０２を含む。しかしながら、誘電層２０２の数は限定されず、回路設計に基づいて誘電層の数を調節することができる。最上部誘電層２０２は、続いて起こるプロセスで電気接続する最上部導電パターン２０４の一部を露出させるために、複数の開口部ＯＰ１を持つことができる。底部誘電層２０２は、他の回路部品と更に電気接続する底部導電パターン２０４の一部を露出させる。
図１Ｃを参照して、複数の導電構造体３００が再分配構造体２００のキャリア１００とは反対側に配置される。ある実施形態では、導電構造体３００を再分配構造体２００の上部導電パターン２０４上にメッキすることができる。メッキプロセスを、電気メッキ、無電解メッキ又は浸漬メッキ等とすることができる。ある実施形態では、導電構造体３００を円柱状カラムとして成形することができる。すなわち、導電構造体３００は、導電ポスト又は導電ピラー等を含むことができる。しかしながら、本開示はこの構成に限定されるものではない。ある代替的実施形態では、導電構造体３００は多角柱状又は他の適切な形状をとることができる。ある実施形態では、それぞれの導電構造体３００は多層複合体構成物である。第１層３０２、第１層３０２上に積層される第２層３０４、及び第２層３０４上に積層される第３層３０６は、それぞれの導電構造体３００を構成することができる。第１層３０２の材料、第２層３０４の材料及び第３層３０６の材料を互いに異なる材料とすることができる。例えば、第１層３０２の材料は、銅、アルミニウム、スズ、銀又はこれらの合金等を含む。第２層３０４の材料は、ニッケル又ははんだ等を含む。第３層の材料は、銅、金又は電気伝導性に優れワイヤボンディング性が良好な他の金属材料を含む。ある実施形態では、第１層３０２、第２層３０４及び第３層３０６は、Cu/Ni/Auの複合構造物を形成することができる。第３層３０６は、導電構造体３００の続いて形成される他の要素との電気的接続性を高めることができる。他方では、第２層３０４は、第１層３０２と第３層３０６との間に挟まれて、第１層３０２と第３層３０６との間のバリア層としての機能を果たす。例えば、第１層３０２、第２層３０４及び第３層３０６がCu/Ni/Auの複合構造物であるときに、ニッケルで製造される第２層３０４は、第１層３０２の銅原子が第３層３０６内へ拡散することを妨げることができる。第３層３０６が銅で汚染されると、第３層３０６が容易に酸化し、そのためワイヤボンディング性が悪化するであろう。しかしながら、バリア層としての第２層３０４によって、上述した悪影響を十分に抑えることができる。図１Ｃでは３層で構成される導電構造体３００を図示したが、本開示はこの構成に限定されるものではない。ある代替的実施形態では、それぞれの導電構造体３００を、単層構造体、又は２層、４層若しくは５層以上で構成される多層構造体とすることができる。
図１Ｃに示すように、導電構造体３００は、再分配構造体２００の上部誘電層２０２の開口部ＯＰ１の一部を埋める。例えば、導電構造体３００の第１層３０２を上部誘電層２０２の開口部ＯＰ１に部分的に配置して、再分配構造体２００と導電構造体３００との間に電気的接続を形成することができる。第１層３０２は再分配構造体２００の上部導電パターン２０４と物理的に接触することができる。
図１Ｄを参照して、複数のダイ４００を再分配構造体２００のキャリア１００とは反対側に配置する。つまみ上げ配置プロセスによって、ダイ４００を再分配構造体２００上に配置することができる。ある実施形態では、ダイ４００を、導電構造体３００がダイ４００を取り囲むように設置する。導電構造体３００は、少なくとも１つのダイ４００の外周に沿って配置される。ダイ４００は、デジタルダイ、アナログダイ又は混合信号ダイを含み得る。例えば、ダイ４００を、特定用途向け集積回路（ＡＳＩＣ）ダイ、論理ダイ又は他の適切なダイとすることができる。それぞれのダイ４００は、半導体基板４０２と、複数の導電パッド４０４と、不活性化層４０６と、複数の導電コネクタ４０８とを含む。ある実施形態では、半導体基板４０２を、その中に形成される能動素子（例えばトランジスタ等）及び任意に受動素子（例えば抵抗器、コンデンサ又はインダクタ等）を含む、シリコン基板とすることができる。導電パッド４０４は、半導体基板４０２にわたって分布する。導電パッド４０４は、アルミニウムパッド、銅パッド又は他の適切な金属パッドを含むことができる。不活性化層４０６は、半導体基板４０２にわたって形成されて、各接続パッド４０４を部分的に被覆する。言い換えれば、不活性化層４０６は、各接続パッド４０４の少なくとも一部をあらわにする複数のコンタクト開口部を有する。不活性化層４０６を、シリコン酸化層、シリコン窒化層、シリコン酸窒化層若しくは高分子材料で形成される誘電層、又は他の適切な誘電材料とすることができる。導電コネクタ４０８は、導電パッド４０４上に配置される。例えば、導電コネクタ４０８は、不活性化層４０６のコンタクト開口部内へ延在して、導電パッド４０４と電気的に接続することができる。ある実施形態では、それぞれの導電コネクタ４０８は、導電ポスト４０８ａと、導電ポスト４０８ａ上に配置される導電バンプ４０８ｂとを含むことができる。導電ポスト４０８ａを導電パッド４０４上にメッキすることができる。メッキプロセスを、電気メッキ、無電解メッキ又は浸漬メッキ等とすることができる。導電ポスト４０８ａは、銅又は銅合金等を含むことができる。他方では、導体バンプ４０８ｂを、銅、ニッケル、スズ、銀又はこれらの組み合わせで製造し得る。ある実施形態では、導電ポスト４０８ａを省略することができる。導電コネクタ４０８は、Ｃ２（チップ接続）バンプ又はＣ４（制御コラプスチップ接続、Controlled Collapse Chip Connection）バンプを含むことができる。
各ダイ４００は、有効面４００ａと、有効面４００ａの反対側の裏面４００ｂとを有する。図１Ｄに示すように、ダイ４００は、ダイ４００の有効面４００ａが再分配構造体２００を向くように、表を下にして配置される。ダイ４００をフリップチップボンディングによって再分配構造体２００に接続することができる。ダイ４００の導電コネクタ４０８を最上部誘電層２０２の開口部ＯＰ１の他の部分に配置することができ、導電コネクタ４０８を再分配層２００の上部導電パターン２０４と物理的に接触させることができる。かくしてダイ４００と再分配構造体２００とを電気的に接触させることができる。ある実施形態では、再分配構造体２００を使用して、ダイ４００への又はダイ４００からの電気信号の経路を変えることができ、再分配構造体２００は、ダイ４００よりも広い領域に拡張することができる。したがって、ある実施形態では、再分配構造体２００を「ファンアウト再分配構造体」と呼ぶことができる。
図１Ｄに示すように、導電構造体３００の厚さｔ３００を、ダイ４００の厚さｔ４００よりも薄くする。例えば、再分配構造体２００に関して、ダイ４００の裏面４００ｂを、導電構造体３００の上面３００ａよりも高くすることができる。
ある実施形態では、再分配構造体２００とダイ４００との間にアンダーフィル５００を形成して、導電コネクタ４０８と最上部導電パターン２０４との間の接続を保護し絶縁する。ある実施形態では、アンダーフィル５００は、最上部誘電層２０２の開口部ＯＰ１を充填する。高分子材料、樹脂又はシリカ添加剤を含むキャピラリーアンダーフィル（ＣＵＦ）でアンダーフィル５００を製造することができる。
図１Ｃ及び図１Ｄにおいて、ダイ４００を設置する前に、導電構造体３００が形成されることを表すが、本開示はこの構成に限定されるものではない。ある代替的実施形態では、導電構造体３００を形成する前に、ダイ４００を再分配構造体２００上に設置することができる。すなわち、図１Ｃに表す製造ステップと図１Ｄに表す製造ステップとは交換可能である。
図１Ｅを参照して、再分配構造体２００上に絶縁材６１２を形成して、導電構造体３００、ダイ４００及びアンダーフィル５００をカプセル化する。絶縁材６１２は、成形プロセスによって形成される成形コンパウンド、又はエポキシ、シリコーン若しくは他の適切な樹脂等の絶縁材を含むことができる。ある実施形態では、絶縁材６１２は、導電構造体３００及びダイ４００があらわにならないように、オーバーモールドプロセスによって形成される。図１Ｅに示すように、絶縁材６１２の上面６１２ａは、導電構造体３００の上面３００ａ及びダイ４００の裏面４００ｂよりも高く位置付けられる。
図１Ｆを参照して、絶縁材６１２の厚さを薄くして、第１絶縁カプセル材６１０を形成する。絶縁材６１２の一部を除去して、ダイ４００の裏面４００ｂを露出させることができる一方、導電構造体３００は依然として第１絶縁カプセル材６１０によって完全にカプセル化されている。ある実施形態では、平坦化プロセスによって絶縁材６１２を除去することができる。平坦化プロセスを、化学機械研磨（ＣＭＰ）、機械的研磨、エッチング又は他の適切なプロセスとすることができる。研磨プロセスでは、絶縁材６１０及びダイ４００を更に研磨して、後に形成するパッケージ構造体１０の全厚を薄くすることができる。平坦化プロセス後、第１絶縁カプセル材６１０を再分配構造体２００上に配置して、ダイ４００を横方向にカプセル化する。第１絶縁カプセル材６１０は、導電構造体３００の側壁及び裏面３００ａもカプセル化する。第１絶縁カプセル材６１０の上面６１０ａ及びダイ４００の裏面４００ｂは実質的に互いに同一平面上に存在できる。他方では、第１絶縁カプセル材６１０の上面６１０ａを、導電構造体３００の上面３００ａよりも高くする。第１絶縁カプセル材６１０の厚さｔ６１０を、それぞれの導電構造体３００の厚さｔ３００よりも厚くできる。
図１Ｇを参照して、第１絶縁カプセル材６１０に複数の開口部ＯＰ２を形成する。ある実施形態では、レーザ穴あけプロセスによって開口部ＯＰ２が形成される。導電構造体３００上に設置される第１絶縁カプセル材６１０を部分的に除去して、開口部ＯＰ２を形成することができる。図１Ｇに示すように、開口部ＯＰ２の位置は、導電構造体３００の位置に対応する。それぞれの開口部ＯＰ２は、それぞれの導電構造体３００の一部を露出させることができる。開口部ＯＰ２は、導電構造体３００の上面３００ａを露出させることができる。ある実施形態では、開口部ＯＰ２は、導電構造体３００の第３層３０６を部分的に露出させることができる。
図１Ｈを参照して、剥離層１０２及びキャリア１００を再分配構造体２００から除去する。剥離層１０２がＬＴＨＣ層であるとき、紫外レーザ光線を露光した後に、剥離層１０２及びキャリア１００を、再分配構造体２００の底部誘電層２０２及び底部導電パターン２０４から剥がして分離することができる。図１Ｈに示す構造体をのこぎりで切断して、従来のワイヤボンディング組立用のストリップ形状にすることができる。
図１Ｉを参照して、チップ積層体７１０をダイ４００及び第１絶縁カプセル材６１０の、再分配構造体２００とは反対側に配置する。チップ積層体７１０を、ダイ４００の裏面４００ｂ及び第１絶縁カプセル材６１０の上面６１０ａの上に設置することができる。チップ積層体７１０を、重ねて積層される複数のチップによって形成することができる。チップを、ＮＡＮＤフラッシュ等の不揮発性メモリーを有するメモリチップとすることができる。しかしながら、本開示はこの構成に限定されるものではない。ある代替的実施形態では、チップ積層体７１０のチップを、論理機能又は演算機能等の他の機能を実施できるチップとすることができる。チップ積層体７１０の隣接する２つのチップ間に、これら２つのチップ間の付着性を高めるためのチップ装着層を配置することができる。
チップ積層体７１０を、複数の導電線７２０によって、導電構造体３００に電気的に接続することができる。チップ積層体７１０をダイ４００及び第１絶縁カプセル材６１０の上に配置するときに、複数の導電線７２０をワイヤボンディングプロセスによって形成することができる。導電線７２０の一端部は、チップ積層体７１０の少なくとも１つのチップに接続され、導電線７２０は第１絶縁カプセル材６１０の開口部ＯＰ２内へ延在し、導電線７２０の他端部は導電構造体３００の第３層３０６に接続される。導電線７２０の材料は、金、アルミニウム又は他の適切な導電材料を含み得る。ある実施形態では、導電線７２０の材料は、導電構造体３００の第３層３０６の材料と同じである。
図１Ｊを参照して、第２絶縁カプセル材６２０を、第１絶縁カプセル材６１０及びダイ４００の上に形成して、チップ積層体７１０及び導電線７２０をカプセル化し、チップ積層体７１０及び導電線７２０を第２絶縁カプセル材６２０に埋め込む。第２絶縁カプセル材６２０の材料を、第１絶縁カプセル材６１０と同じ材料とすることができ、又は第１絶縁カプセル材６１０とは異なる材料とすることができる。第２絶縁カプセル材６２０の材料を、エポキシ、成形コンパウンド又は他の適切な絶縁材とすることができる。ある実施形態では、第２絶縁カプセル材６２０の材料の吸湿度を低くすることができる。第２絶縁カプセル材６２０を、圧縮成形、トランスファー成型又は他のカプセル化プロセスによって形成することができる。図１Ｊに示すように、第２絶縁カプセル材６２０は、第１絶縁カプセル材６１０の開口部ＯＰ２を充填して、導電線７２０の開口部ＯＰ２に存在する部分を保護することができる。第２絶縁カプセル材６２０は、導電構造体３００の一部と物理的に接触することができる。第２絶縁カプセル材６２０は、チップ積層体７１０及び導電線７２０に対して、物理的支持、機械的保護並びに電気的絶縁及び環境的分離をもたらす。
図１Ｋを参照して、複数の導電端子８００が、再分配構造体２００の導電構造体３００及びダイ４００とは反対側に形成される。ある実施形態では、導電端子８００は、再分配構造体２００の底部導電パターン２０４上に配置される。言い換えれば、再分配構造体２００の底部導電パターン２０４を、アンダーボール金属被覆法（ＵＢＭ）パターンと呼ぶことができる。導電端子８００を、ボール載置プロセス及び／又はリフロープロセスによって形成することができる。導電端子８００を、はんだボール等の導電バンプとすることができる。しかしながら、本開示はこの構成に限定されるものではない。ある代替的実施形態では、導電端子８００は、設計要件に基づいて他の可能な形態及び形状をとることができる。例えば、導電端子８００は、導電ピラー又は導電ポストの形状をとることができる。
図１Ｌを参照して、導電端子８００を形成した後に、シンギュレーションプロセスを行って、複数のパッケージ構造体１０を得る。シンギュレーションプロセスは例えば、回転ブレード又はレーザ光線を用いた切断を含む。
上記記載に基づいて、導電構造体は、パッケージ構造体内の垂直接続機構としての機能を果たすことができる。導電構造体の厚さが薄くなるため、パッケージ構造体のサイズを有効に減少させることができる。また、短い導電構造体の適応によって、従来のパッケージ構造体における、付加的なキャリアを除去し又は銅ピラーをより薄くすることができ、これにより、製造コストを削減する。
本開示の範囲又は精神から離れることなく、開示される実施形態に対して様々な変更及び変形を加えることができることが、当業者にとって明らかであろう。前述したことを考慮して、変更又は変形は、特許請求の範囲及び特許請求の範囲の均等物に該当する限り、本開示に含まれることを意図する。
本開示は、パッケージ構造体及びパッケージ構造体の製造方法を提供する。パッケージ構造体を、電気製品で利用することができる。本開示の小型化されるパッケージ構造体を利用することで、電気製品のサイズを十分に減少させることができる。
１０：パッケージ構造体
１００：キャリア
１０２：剥離層
２００：再分配構造体
２０２：誘電層
２０４：導電パターン
２０６：導電ビア
３００：導電構造体
３００ａ、６１０ａ、６１２ａ：上面
３０２：第１層
３０４：第２層
３０６：第３層
４００：ダイ
４００ａ：有効面
４００ｂ：裏面
４０２：半導体基板
４０４：導電パッド
４０６：不活性化層
４０８：導電コネクタ
４０８ａ：導電ポスト
４０８ｂ：導電バンプ
５００：アンダーフィル
６１０：第１絶縁カプセル材
６１２：絶縁材
６２０：第２絶縁カプセル材
７１０：チップ積層体
７２０：導電線
８００：導電端子
ＯＰ１、ＯＰ２：開口部
ｔ３００、ｔ４００、ｔ６１０：厚さ

Claims (19)

  1. 交互に積層される少なくとも一層の誘電層と複数の導電パターンとを含み、前記誘電層が複数の前記導電パターンを露出させる複数の開口部を有する再分配構造体と、
    前記再分配構造体上に配置され、前記再分配構造体に電気的に接続され、複数の導電コネクタを含むダイと、
    前記再分配構造体上に配置され、前記再分配構造体に電気的に接続され、前記ダイを取り囲む複数の導電構造体と、
    前記ダイ及び前記導電構造体をカプセル化し、前記導電構造体の上面を露出させる複数の開口部を含む第１絶縁カプセル材と、
    前記第１絶縁カプセル材及び前記ダイの上に配置され、前記導電構造体に電気的に接続されるチップ積層体と、
    前記チップ積層体をカプセル化する第２絶縁カプセル材と、
    前記第２絶縁カプセル材に埋め込まれる複数の導電線と、を備え、
    前記チップ積層体は、前記導電線を通じて前記導電構造体と電気的に接続され、前記導電線は、前記導電構造体と直接接触し、
    それぞれの導電構造体は、第１層と、前記第１層上に積層される第２層と、前記第２層上に積層される第３層と、前記第３層を露出させる前記第１絶縁カプセル材の前記開口部とを含み、前記第１層の材料、前記第２層の材料及び前記第３層の材料は、互いに異なり、
    前記導電構造体は、前記誘電層の開口部の一部を埋め、前記ダイの前記導電コネクタは、前記誘電層の開口部の他の部分に配置されるパッケージ構造体。
  2. 前記再分配構造体の前記ダイ及び前記導電構造体とは反対側に配置される複数の導電端子を更に備える、請求項１に記載のパッケージ構造体。
  3. 前記再分配構造体と前記ダイとの間に配置されるアンダーフィルを更に備える、請求項１に記載のパッケージ構造体。
  4. 前記導電線は前記第１絶縁カプセル材の前記開口部内へ延在する、請求項１に記載のパッケージ構造体。
  5. 前記第２絶縁カプセル材は、前記第１絶縁カプセル材の前記開口部を充填する、請求項１に記載のパッケージ構造体。
  6. 前記第３層の材料は、金を含む、請求項１に記載のパッケージ構造体。
  7. 前記第１絶縁カプセル材の厚さは、それぞれの導電構造体の厚さよりも厚い、請求項１に記載のパッケージ構造体。
  8. 前記第１絶縁カプセル材の上面の高さは、前記導電構造体の前記上面の高さよりも高い、請求項１に記載のパッケージ構造体。
  9. 前記ダイは有効面と前記有効面の反対側に存在する裏面とを有し、前記複数の導電コネクタは前記有効面上に設置され、前記導電コネクタは前記再分配構造体と直接接触する、請求項１に記載のパッケージ構造体。
  10. キャリアを提供するキャリア提供ステップと、
    前記キャリア上に交互に積層される少なくとも一層の誘電層と複数の導電パターンとを含み、前記誘電層が複数の前記導電パターンを露出させる複数の開口部を有する再分配構造体を形成する再分配構造体形成ステップと、
    複数のダイを取り囲む複数の導電構造体及び前記複数のダイを前記再分配構造体上に配置し、それぞれの前記ダイが複数の導電コネクタを含む配置ステップと、
    第１絶縁カプセル材を形成して前記ダイ及び前記導電構造体をカプセル化する第１絶縁カプセル材形成ステップと、
    複数の開口部を前記第１絶縁カプセル材に形成して前記導電構造体の上面を露出させる開口部形成ステップと、
    前記キャリアを前記再分配構造体から除去するキャリア除去ステップと、
    前記導電構造体に電気的に接続されるチップ積層体を、前記ダイ及び前記第１絶縁カプセル材の、前記再分配構造体とは反対側に配置するチップ積層体配置ステップと、
    複数の導電線を形成し、前記チップ積層体を、前記導電線を通じて前記導電構造体に電気的に接続させるステップと、
    前記チップ積層体を第２絶縁カプセル材によってカプセル化し、前記導電線は、前記第２絶縁カプセル材に埋め込まれ、前記導電線は、前記導電構造体と直接接触するチップ積層体カプセル化ステップと、
    を含み、
    それぞれの導電構造体は、第１層と、前記第１層上に積層される第２層と、前記第２層上に積層される第３層と、前記第３層を露出させる前記第１絶縁カプセル材の前記開口部とを含み、前記第１層の材料、前記第２層の材料及び前記第３層の材料は、互いに異なり、
    前記導電構造体は、前記誘電層の開口部の一部を埋め、前記ダイの前記導電コネクタは、前記誘電層の開口部の他の部分に配置されるパッケージ構造体の製造方法。
  11. 複数の導電端子を前記再分配構造体の前記ダイ及び前記導電構造体とは反対側に形成するステップを更に含む、請求項１０に記載のパッケージ構造体の製造方法。
  12. 前記導電線は前記第１絶縁カプセル材の前記開口部内へ延在する、請求項１０に記載のパッケージ構造体の製造方法。
  13. シンギュレーションプロセスを行うステップを更に備える、請求項１０に記載のパッケージ構造体の製造方法。
  14. 前記再分配構造体と前記ダイとの間にアンダーフィルを形成するステップを更に備える、請求項１０に記載のパッケージ構造体の製造方法。
  15. 前記ダイはフリップチップボンディングによって前記再分配構造体に接続される、請求項１０に記載のパッケージ構造体の製造方法。
  16. 第１絶縁カプセル材の前記開口部がレーザ穴あけプロセスによって形成される、請求項１０に記載のパッケージ構造体の製造方法。
  17. 前記チップ積層体カプセル化ステップが、前記第２絶縁カプセル材を前記第１絶縁カプセル材の前記開口部に充填するステップを含む、請求項１０に記載のパッケージ構造体の製造方法。
  18. 前記ダイのそれぞれは、有効面と前記有効面とは反対側の裏面とを有し、
    前記第１絶縁カプセル材形成ステップは、絶縁材を前記再分配構造体上に形成して前記ダイ及び前記導電構造体を被覆するステップと、前記絶縁材の一部を除去して前記ダイの前記裏面を露出させる絶縁体部分除去ステップと、を含む、請求項１０に記載のパッケージ構造体の製造方法。
  19. 前記絶縁体部分除去ステップにおいて、前記導電構造体はあらわにならない、請求項１８に記載のパッケージ構造体の製造方法。
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