US20190164948A1 - Package structure and manufacturing method thereof - Google Patents

Package structure and manufacturing method thereof Download PDF

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Publication number
US20190164948A1
US20190164948A1 US16/112,785 US201816112785A US2019164948A1 US 20190164948 A1 US20190164948 A1 US 20190164948A1 US 201816112785 A US201816112785 A US 201816112785A US 2019164948 A1 US2019164948 A1 US 2019164948A1
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Prior art keywords
conductive
insulating encapsulant
dies
die
package structure
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Abandoned
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US16/112,785
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English (en)
Inventor
Shang-Yu Chang Chien
Hung-Hsin Hsu
Nan-Chun Lin
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Powertech Technology Inc
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Powertech Technology Inc
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Application filed by Powertech Technology Inc filed Critical Powertech Technology Inc
Priority to US16/112,785 priority Critical patent/US20190164948A1/en
Assigned to POWERTECH TECHNOLOGY INC. reassignment POWERTECH TECHNOLOGY INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHANG CHIEN, SHANG-YU, HSU, HUNG-HSIN, LIN, NAN-CHUN
Priority to KR1020180133232A priority patent/KR102123249B1/ko
Priority to JP2018214495A priority patent/JP6835798B2/ja
Priority to TW107141331A priority patent/TWI691029B/zh
Priority to CN201811423732.6A priority patent/CN109841606A/zh
Publication of US20190164948A1 publication Critical patent/US20190164948A1/en
Abandoned legal-status Critical Current

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Definitions

  • the disclosure generally relates to a package structure and a manufacturing method thereof, and in particular, to a package structure having a connecting module and a manufacturing method thereof.
  • the disclosure provides a package structure and a manufacturing method thereof, which effectively reduces the height of the package structure at a lower manufacturing cost.
  • the disclosure provides a package structure including a redistribution structure, a die, at least one connecting module, a first insulating encapsulant, a chip stack, and a second insulating encapsulant.
  • the die is disposed on and electrically connected to the redistribution structure.
  • the connecting module is disposed on the redistribution structure.
  • the connecting module includes a protection layer and a plurality of conductive bars embedded in the protection layer.
  • the first insulating encapsulant encapsulates the die and the connecting module.
  • the chip stack is disposed on the first insulating encapsulant and the die.
  • the chip stack is electrically connected to the connecting module.
  • the second insulating encapsulant encapsulates the chip stack.
  • the disclosure provides a manufacturing method of a package structure.
  • the method includes at least the following steps.
  • a carrier is provided.
  • a plurality of dies and a plurality of connecting modules are disposed on the carrier.
  • Each of the connecting modules includes a protection layer and a plurality of conductive bars embedded in the protection layer.
  • a first insulating encapsulant is formed on the carrier to encapsulate the dies and the connecting modules.
  • a redistribution structure is formed over the dies, the connecting modules, and the first insulating encapsulant.
  • the carrier is removed from the dies, the connecting modules, and the first insulating encapsulant.
  • a chip stack is disposed on the dies and the first insulating encapsulant opposite to the redistribution structure. The chip stack is electrically connected to the connecting modules.
  • the second insulating encapsulant encapsulates the chip stack.
  • the readily available prefabricated connecting module may serve as vertical connecting feature within the package structure. Due to the small thickness of the connecting module, the size of the package structure may be effectively reduced. In addition, the adaption of the connecting module may result in elimination of additional carrier or thicker copper pillars in the conventional package structure, thereby reducing the manufacturing cost.
  • FIG. 1A to FIG. 1J are schematic cross-sectional views illustrating a manufacturing method of a package structure according to some embodiments of the disclosure.
  • FIG. 1A to FIG. 1J are schematic cross-sectional views illustrating a manufacturing method of a package structure 10 according to some embodiments of the disclosure.
  • a carrier 100 having a de-bonding layer 102 formed thereon is provided.
  • the carrier 100 may be a glass substrate or a glass supporting board.
  • suitable substrate material may be adapted as long as the material is able to withstand subsequent processes while structurally supporting the package structure formed thereon.
  • the de-bonding layer 102 may include light to heat conversion (LTHC) materials, epoxy resins, inorganic materials, organic polymeric materials, or other suitable adhesive materials.
  • LTHC light to heat conversion
  • the disclosure is not limited thereto, and other suitable de-bonding layers may be used in some alternative embodiments.
  • a plurality of dies 200 and a plurality of connecting modules 300 are disposed on the de-bonding layer 102 and the carrier 100 .
  • the dies 200 may include digital dies, analog dies, or mixed signal dies.
  • the dies 200 may be application-specific integrated circuit (ASIC) dies, logic dies, or other suitable dies.
  • ASIC application-specific integrated circuit
  • Each die 200 includes a semiconductor substrate 202 , a plurality of conductive pads 204 , a passivation layer 206 , and a plurality of conductive connectors 208 .
  • the semiconductor substrate 202 may be a silicon substrate including active components (e.g., transistors or the like) and optionally passive components (e.g., resistors, capacitors, inductors, or the like) formed therein.
  • the conductive pads 204 are distributed over the semiconductor substrate 202 .
  • the conductive pads 204 may include aluminum pads, copper pads, or other suitable metal pads.
  • the passivation layer 206 is formed over the semiconductor substrate 202 to partially cover each connection pad 204 . In other words, the passivation layer 206 has a plurality of contact openings revealing at least a portion of each connection pad 204 .
  • the passivation layer 206 may be a silicon oxide layer, a silicon nitride layer, a silicon oxy-nitride layer, or a dielectric layer formed of polymeric materials or other suitable dielectric materials.
  • the conductive connectors 208 are disposed on the conductive pads 204 .
  • the conductive connectors 208 may extend into the contact openings of the passivation layer 206 to render electrical connection with the conductive pads 204 .
  • the conductive connectors 208 may be plated on the conductive pads 204 .
  • the plating process is, for example, electro-plating, electroless-plating, immersion plating, or the like.
  • the conductive connectors 208 may take the form of conductive posts, conductive pillars, or conductive bumps.
  • a material of the conductive connectors 208 includes copper, aluminum, tin, gold, silver, alloys thereof, or other suitable conductive materials.
  • each die 200 has an active surface 200 a and a rear surface 200 b opposite to the active surface 200 a .
  • the dies 200 are disposed in a face up manner.
  • the active surfaces 200 a of the dies 200 face away from the carrier 100 while the rear surfaces 200 b of the dies 200 face toward the carrier 100 .
  • the dies 200 may be attached to the carrier 100 through an adhesive layer 400 .
  • the adhesive layer 400 may be disposed on the rear surfaces 200 b of the dies 200 such that the adhesive layer 400 is sandwiched between the semiconductor substrates 202 of the dies 200 and the de-bonding layer 102 .
  • the adhesive layer 400 may temporarily enhance the adhesion between the dies 200 and the de-bonding layer 102 to prevent die shift.
  • the adhesive layer 400 may be a dry film and may be adhered to the de-bonding layer 102 through a lamination process.
  • a solution of the adhesive layer 400 (liquid type) may be coated onto the de-bonding layer 102 through a coating process. Subsequently, the solution is dried or cured to form a solid layer of the adhesive layer 400 .
  • the adhesive layer 400 may be made of B-stage materials.
  • the adhesive layer 400 may include resins constituting a die attach films (DAF).
  • DAF die attach films
  • the adhesive layer 400 is optional. When the adhesive layer 400 is not being utilized, the dies 200 may be directly attached onto the de-bonding layer 102 .
  • the connecting modules 300 are disposed along the periphery of at least one die 200 .
  • Each of the connecting modules 300 includes a plurality of conductive bars 302 , a plurality of barrier layers 304 , a plurality of conductive caps 306 , and a protection layer 308 .
  • the conductive bars 302 may be shaped as cylindrical columns. However, the disclosure is not limited thereto. In some alternative embodiments, the conductive bars 302 may take the form of polygonal columns or other suitable shapes.
  • a material of the conductive bars 302 includes copper, aluminum, nickel, tin, gold, silver, alloys thereof, or the like.
  • the conductive caps 306 are correspondingly disposed on the conductive bars 302 .
  • the conductive caps 306 are disposed on the conductive bars 302 to further enhance the electrical connection and the wire bondability of the connecting modules 300 with other subsequently formed elements.
  • a material of the conductive caps 306 is different from the material of the conductive bars 302 .
  • the conductive caps 306 may include gold or other metallic material with excellent electrical conductivity and good wire bondability.
  • the barrier layer 304 may include nickel, solder, silver, or other suitable conductive materials. Each barrier layer 304 is sandwiched between a conductive cap 306 and a conductive bar 302 to prevent diffusion of atoms between the conductive cap 306 and the conductive bar 302 .
  • the barrier layer 304 formed of nickel may prevent the copper atoms of the conductive bar 302 from diffusing into the conductive cap 306 .
  • the contamination of the conductive cap 306 with copper would cause the conductive cap 306 to oxidize easily, thereby resulting in poor wire bondability.
  • the conductive caps 306 and the barrier layers 304 may be omitted if the conductive bars 302 already have sufficient wire bondability with the subsequently formed elements.
  • the conductive bars 302 , the barrier layers 304 , and the conductive caps 306 are embedded in the protection layer 308 .
  • the protection layer 308 exposes at least a portion of each of the conductive bars 302 and at least a portion of each of the conductive caps 306 .
  • the protection layer 308 may laterally encapsulates the conductive bars 302 , the barrier layers 304 , and the conductive caps 306 .
  • surfaces 302 a of the conductive bars 302 may be exposed by the protection layer 308 .
  • the surfaces 302 a of the conductive bars 302 are substantially coplanar to a first surface 308 a of the protection layer 308 .
  • surfaces 306 b of the conductive caps 306 may also be exposed by the protection layer 308 . That is, the surfaces 306 b of the conductive caps 306 are substantially coplanar to a second surface 308 b (the surface of the protection layer 308 opposite to the first surface 308 a ) of the protection layer 308 . It should be noted that the configuration shown in FIG. 1B merely serves as an exemplary illustration, and the disclosure is not limited thereto. In some alternative embodiments, the protection layer 308 may cover surfaces 302 a of the conductive bars 302 such that the conductive bars 302 are not revealed.
  • the first surface 308 a of the protection layer 308 may be located at a level height higher than the height of the top surfaces 302 a of the conductive bars 302 .
  • a material of the protection layer 308 includes polymers, epoxies, molding compounds, or other suitable dielectric materials.
  • the connecting modules 300 are pre-fabricated before being placed on the carrier 100 .
  • the connecting modules 300 may be placed on the carrier 100 through a picked-and-placed process.
  • the connecting modules 300 are picked-and-placed onto the carrier 100 and the de-bonding layer 102 by a die bonder, a chip sorter, or a SMT (Surface Mount Technology) machine.
  • the connecting modules 300 are placed such that the conductive caps 306 face the carrier 100 . That is, the connecting modules 300 is placed to render the conductive caps 306 closer to the carrier 100 than the conductive bars 302 .
  • a number of the conductive bars 302 within each connecting module 300 may vary depending on design requirements.
  • the conductive bars 302 are distributed within the protection layer 308 such that a distance between conductive bars 302 is minimized while maintaining effective electrical isolation between the conductive bars.
  • the connecting modules 300 may exhibit a square shape, rectangular shape, a ring shape, or other geometries from the top view.
  • an insulating material 512 is formed on the carrier 100 and the de-bonding layer 102 to cover the dies 200 and the connecting modules 300 .
  • the insulating material 512 encapsulates the dies 200 and the connecting modules 300 .
  • a material of the insulating material 512 may be different from the material of the protection layer 308 of the connecting modules 300 .
  • the insulating material 512 may include a molding compound formed by a molding process or an insulating material such as epoxy, silicone, or other suitable resins.
  • the insulating material 512 is formed by an over-molding process such that the dies 200 and the connecting modules 300 are not revealed. For example, as illustrated in FIG.
  • a top surface 512 a of the insulating material 512 is located at a level height higher than the height of the first surface 308 a of the protection layer 308 , the surfaces 302 a of the conductive bars 302 , and top surfaces 208 a of the conductive connectors 208 .
  • a thickness of the insulating material 512 is reduced to form a first insulating encapsulant 510 .
  • a portion of the insulating material 512 is removed until the conductive connectors 208 of the dies 200 and the conductive bars 302 of the connecting modules 300 are both exposed.
  • the insulating material 512 may be removed through a planarization process.
  • the planarization process includes, for example, Chemical Mechanical Polishing (CMP), mechanical grinding, etching, or other suitable process.
  • CMP Chemical Mechanical Polishing
  • the planarization process may further grind the connecting modules 300 , the insulating material 512 , and the dies 200 to reduce the overall thickness of the subsequently formed package structure 10 .
  • the first insulating encapsulant 510 is formed on the carrier 100 and the de-bonding layer 102 to laterally encapsulate the dies 200 and the connecting modules 300 .
  • the first surface 308 a of the protection layer 308 , a first surface 510 a of the first insulating encapsulant 510 , the surfaces 302 a of the conductive bars 302 , and the top surfaces 208 a of the conductive connectors 208 are substantially coplanar to each other.
  • the first insulating encapsulant 510 and the protection layer 308 of the connecting modules 300 are made of different materials, the first insulating encapsulant 510 and the protection layer 308 are considered as two distinct layers. In other words, a clear interface may be seen between the first insulating encapsulant 510 and the protection layer 308 .
  • a redistribution structure 600 is formed on the dies 200 , the connecting modules 300 , and the first insulating encapsulant 510 .
  • the redistribution structure 600 may include at least one dielectric layer 602 , a plurality of conductive patterns 604 , and a plurality of conductive vias 606 .
  • the dielectric layers 602 may be formed by suitable fabrication techniques such as spin-on coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or the like.
  • the dielectric layers 602 may be made of non-organic or organic dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, polyimide, benzocyclobutene (BCB), or the like.
  • the conductive patterns 604 and the conductive vias 606 may be formed by sputtering, evaporation, electro-less plating, or electroplating.
  • the conductive patterns 604 and the conductive vias 606 are embedded in the dielectric layers 602 .
  • the dielectric layers 602 and the conductive patterns 604 may be stacked alternately.
  • the conductive vias 606 penetrate through the dielectric layers 602 to electrically connect the conductive patterns 604 to each other.
  • the conductive patterns 604 and the conductive vias 606 may be made of copper, aluminum, nickel, gold, silver, tin, a combination thereof, a composite structure of copper/nickel/gold, or other suitable conductive materials.
  • the redistribution structure 600 includes four dielectric layers 602 .
  • the bottom dielectric layer 602 may have a plurality of contact openings 602 a partially exposing the conductive bars 302 of the connecting modules 300 and the conductive connectors 208 of the dies 200 .
  • the conductive vias 606 disposed in the contact openings 602 a may be directly in contact with the conductive bars 302 of the connecting modules 300 and the conductive connectors 208 of the dies 200 .
  • the conductive connectors 208 of the dies 200 are directly in contact with the redistribution structure 600 to render the electrical connection between the dies 200 and the redistribution structure 600 .
  • the conductive bars 302 of the connecting modules 300 are also directly in contact with the redistribution structure 600 to render the electrical connection between the connecting modules 300 and the redistribution structure 600 .
  • the middle dielectric layers 602 expose part of the bottom conductive patterns 604 such that the bottom conductive patterns 604 may be electrically connected to other conductive patterns 604 (for example, the middle conductive patterns 604 ) through the conductive vias 606 .
  • the top dielectric layer 602 has a plurality of contact openings 602 b exposing a portion of the middle conductive patterns 604 .
  • the top conductive vias 606 may extend into the contact openings 602 b to electrically connect the top conductive patterns 604 and the middle conductive patterns 604 .
  • the top conductive patterns 604 are disposed on the top dielectric layer 602 for electrical connection in the subsequent processes.
  • the top conductive patterns 604 may be referred to as under-bump metallization (UBM) patterns.
  • the redistribution structure 600 may be used to reroute electrical signals to/from the die 200 and may expand in a wider area than the die 200 . Therefore, in some embodiments, the redistribution structure 600 may be referred to as a “fan-out redistribution structure.”
  • the de-bonding layer 102 and the carrier 100 are removed from the dies 200 , the connecting modules 300 , the adhesive layer 400 , and the first insulating encapsulant 510 .
  • the de-bonding layer 102 may be an LTHC layer.
  • the de-bonding layer 102 and the carrier 100 may be peeled off and separated from the conductive caps 306 and the protection layer 308 of the connecting modules 300 , the adhesive layer 400 , and the first insulating encapsulant 510 .
  • the second surface 308 b of the protection layer 308 Upon removal of the carrier 100 and the de-bonding layer 102 , the second surface 308 b of the protection layer 308 , the surfaces 306 b of the conductive caps 306 , and a second surface 510 b (the surface of the first insulating encapsulant 510 opposite to the first surface 510 a ) of the first insulating encapsulant 510 are exposed.
  • the surfaces 306 b of the conductive caps 306 , the second surface 308 b of the protection layer 308 , and the second surface 510 b of the first insulating encapsulant 510 are substantially coplanar to each other.
  • FIG. 1G the structure illustrated in FIG. 1F is flipped upside down such that the dies 200 , the connecting modules 300 , and the first insulating encapsulant 510 are shown to be disposed on/above the redistribution structure 600 .
  • a chip stack 710 is disposed on the dies 200 and the first insulating encapsulant 510 opposite to the redistribution structure 600 .
  • the chip stack 710 may be placed on the adhesive layer 400 and the second surface 510 b of the first insulating encapsulant 510 . That is, the adhesive layer 400 is sandwiched between the chip stack 710 and the rear surface 200 b of the die 200 .
  • the chip stack 710 may be constituted by a plurality of chips stacked on each other.
  • the chips may include memory chips having non-volatile memory, such as NAND flash.
  • the disclosure is not limited thereto.
  • the chips of the chip stack 710 may be chips capable of performing other functions, such as logic function, computing function, or the like.
  • a chip attachment layer may be seen between two adjacent chips in the chip stack 710 to enhance the adhesion between these two chips.
  • the chip stack 700 may be electrically connected to the conductive caps 306 of the connecting modules 300 through a plurality of conductive wires 720 .
  • a plurality of conductive wires 720 may be formed through a wire-bonding process.
  • One end of the conductive wire 720 is connected to at least one chip of the chip stack 710 .
  • another end of the conductive wire 720 is connected to the surface 306 b of the conductive cap 306 .
  • a material of the conductive wires 720 may include gold, aluminum, or other suitable conductive materials. In some embodiments, the material of the conductive wires 720 is identical to the material of the conductive caps 306 .
  • a second insulating encapsulant 520 is formed on the first insulating encapsulant 510 and the connecting modules 300 to encapsulate the chip stack 710 and the conductive wires 720 .
  • a material of the second insulating encapsulant 520 may be the same or different from that of the first insulating encapsulant 510 .
  • the material of the second insulating encapsulant 520 may include epoxy, molding compound, or other suitable insulating materials.
  • the material of the second insulating encapsulant 520 may have a low moisture absorption rate.
  • the second insulating encapsulant 520 may be formed through compression molding, transfer molding, or other encapsulation processes.
  • the second insulating encapsulant 520 provides physical support, mechanical protection, and electrical and environmental isolation for the chip stack 710 and the conductive wires 720 .
  • the chip stack 710 and the conductive wires 720 are embedded in the second insulating encapsulant 520 .
  • a plurality of conductive terminals 800 is formed on the redistribution structure 600 opposite to the dies 200 and the connecting modules 300 .
  • the conductive terminals 800 are disposed on the UBM patterns (the bottom conductive patterns 604 shown in FIG. 1I ) of the redistribution structure 600 .
  • the conductive terminals 800 may be formed by a ball placement process and/or a reflow process.
  • the conductive terminals 800 may be conductive bumps, such as solder balls.
  • the disclosure is not limited thereto.
  • the conductive terminals 800 may take other possible forms and shapes based on design requirements.
  • the conductive terminals 800 may take the form of conductive pillars or conductive posts.
  • a singulation process is performed to obtain a plurality of package structures 10 .
  • the singulation process includes, for example, cutting with a rotating blade or a laser beam.
  • the readily available prefabricated connecting module may serve as vertical connecting feature within the package structure. Due to the small thickness of the connecting module, the size of the package structure may be effectively reduced. In addition, the adaption of the connecting module may result in elimination of additional carrier or thicker copper pillars in the conventional package structure, thereby reducing the manufacturing cost.

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US20190164888A1 (en) 2019-05-30
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CN109841606A (zh) 2019-06-04
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