TWM537310U - 3d多晶片模組封裝結構(一) - Google Patents
3d多晶片模組封裝結構(一) Download PDFInfo
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- TWM537310U TWM537310U TW105217323U TW105217323U TWM537310U TW M537310 U TWM537310 U TW M537310U TW 105217323 U TW105217323 U TW 105217323U TW 105217323 U TW105217323 U TW 105217323U TW M537310 U TWM537310 U TW M537310U
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- printed circuit
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- circuit board
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- 238000004806 packaging method and process Methods 0.000 title description 2
- 239000004065 semiconductor Substances 0.000 claims description 18
- 239000013078 crystal Substances 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 238000000034 method Methods 0.000 description 16
- 239000000758 substrate Substances 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000001465 metallisation Methods 0.000 description 5
- 238000007639 printing Methods 0.000 description 4
- 238000005553 drilling Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48235—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
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- H01L2924/151—Die mounting substrate
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- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/181—Encapsulation
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- Production Of Multi-Layered Print Wiring Board (AREA)
Description
本創作係有關於半導體封裝結構,尤指一種3D多晶片封裝結構。
半導體裝置係由晶粒(chip,或稱為die)及封裝結構(package)所構成,封裝結構可對晶粒提供保護、電氣傳導路徑(將晶粒上的焊墊(bond pad)引出到外部,以便與外部的電路或裝置連接)及散熱等功能,現代的半導體裝置其晶粒係朝著元件數目增加且縮小體積之趨勢發展,因此,對於半導體封裝結構或製程而言,如何相應的縮小封裝體積並提高集成度,即形成不小的技術挑戰。
在現有的先進封裝製程中,包含堆疊式封裝(PoP,Package on Package)在內的3D封裝技術可用來實現前述縮小體積並提高集成度的目標,其中,可透過導電的直通矽晶穿孔(TSV,through silicon vias)或直通孔洞穿孔(THV,through hole vias)來達成3D裝置的集成(integration),然而,習知的堆疊式封裝通常需要額外的雷射鑽孔(laser drilling)、金屬化(metallization)等製程以形成可貫穿整個封裝厚度的互連結構,如此一來,將使封裝結構的製程更為複雜並提高製造成本,是故,如何針對上述缺失加以改進,即為本案申請人所欲解決之技術困難點所在。
有鑑於習用半導體封裝結構的上述缺失,因此本創作之目的在於發展一種可簡化製程並降低製造成本之3D多晶片封裝結構。
為達成以上之目的,本創作係提供一種3D多晶片模組封裝結構,其包含:一印刷電路基板,係設有一開口,該印刷電路基板的上表面與下表面分別設有,且位於該印刷電路基板上表面的導電墊與位於該印刷電路基板下表面的導電墊相互連接;一第一晶粒,係以令其接觸墊朝下的方式設置於該印刷電路基板的開口內;一第一封裝體,係填設於該印刷電路基板的開口內並包覆該第一晶粒;一重新布線層,係設置於該印刷電路基板與第一晶粒下方,用以使第一晶粒的接觸墊以扇出方式與印刷電路基板下表面的導電墊相連接;複數個外部連接元件,係連接於該重新布線層下方。
其中,該第一晶粒為高接腳數目的半導體晶粒。
其中,進一步包含有一多晶片封裝結構,該多晶片封裝結構係疊設於該印刷電路基板上方,且該多晶片封裝結構與印刷電路基板上表面的導電墊電性連接。
進一步的,該多晶片封裝結構內設有至少兩個第二晶粒。
進一步的,該第二晶粒為較低接腳數目的半導體晶粒。
其中,該第一封裝體上堆疊設置有至少一個第二晶粒,且各該第二晶粒為低接腳數目的半導體晶粒,各該第二晶粒分別透過金屬導線與印刷電路基板上表面的導電墊相連接,又該印刷電路基板上方與第二晶粒周圍設置有一第二封裝體。
藉此,本創作的印刷電路基板只需採用現成且等級較低之印刷電路板,且印刷電路板上無須複雜的雷射鑽孔或金屬化製程即可形成貫穿整個封裝的上下互連結構,此外,該重新布線層亦只需用到相當成熟且精密度較低的半導體製程,從而使本創作可達到簡化製程並降低製造成本之目的。
〔本創作〕
1‧‧‧基本封裝結構
2‧‧‧印刷電路基板
21‧‧‧開口
22‧‧‧導電墊
23‧‧‧導電墊
24‧‧‧導電柱
3‧‧‧第一晶粒
31‧‧‧接觸墊
4‧‧‧載體
5‧‧‧第一封裝體
6‧‧‧重新布線層
7‧‧‧外部連接元件
8‧‧‧多晶片封裝結構
81‧‧‧第二晶粒
82‧‧‧第二封裝體
83‧‧‧封裝基板
84‧‧‧金屬導線
第一圖係本創作之一實施例的結構示意圖。
第二圖至第五圖係本創作之一實施例的製作流程示意圖。
第六圖係本創作之第二實施例的結構示意圖。
第七圖係本創作之第三實施例的結構示意圖。
請參閱第一圖所示,其係本創作之3D多晶片模組封裝結構的基本封裝結構1,其包含:一印刷電路基板(PCB)2,請再配合參閱第二圖至第五圖所示,其揭示了如第一圖之基本封裝結構1的製作流程,其中,該印刷電路基板2上設有一開口21,該印刷電路基板2的上表面與下表面分別設有導電墊(conductive pad)22、23,且位於該印刷電路基板2上表面的導電墊22與位於該印刷電路基板2下表面的導電墊23具體可透過導電柱24、導電層或導電墊而相互連接,一般而言,該印刷電路基板2可以採用雙面板(double-sided board)來製作,也可以採用多層板(multi-layer board)來製作;一第一晶粒3,該第一晶粒3係以令其接觸墊(bond pad)31
朝下的方式設置於該印刷電路基板2的開口21內,請參閱第二圖所示,製作時,係先將該印刷電路基板2置設於一載體4如膠帶(carrier tape)上,再將該第一晶粒3置設在位於該開口21內的載體4上,加以定位,在此,該第一晶粒3優選係為高接腳數目(high pin count)的半導體晶粒如各種處理器,像是個人電腦的中央處理器(CPU)、行動裝置的應用處理器(Application Porcessor,AP)或是圖型處理器(GPU)等等,以便充分發揮本創作的結構特點與應用效益;一第一封裝體(encapsulant)5,該第一封裝體5係填設於該印刷電路基板2的開口21內並包覆該第一晶粒3,該第一封裝體5也可同時將該印刷電路基板2與第一晶粒3連接結合起來,該第一封裝體5具體可為封裝用樹脂,請再配合參閱第三圖所示,製作時,可透過印刷、塗覆或模製等方式將第一封裝體5沉積成型於該開口21內,至此,該印刷電路基板2、第一晶粒3與第一封裝體5即構成一中間階段的晶粒封裝結構;一重新布線層(RDL,Redistribution Layer)6,該重新布線層6係設置於該印刷電路基板2與第一晶粒3下方,用以使第一晶粒3的接觸墊31能夠以扇出(Fan-Out)的方式及結構與印刷電路基板2下表面的導電墊23相連接,請再配合參閱第三圖與第四圖所示,製作時,可先用例如機械剝離的方式將第三圖中的載體4移除,接下來,再將前述的中間階段的晶粒封裝結構上下翻轉,使印刷電路基板2下表面的導電墊23及第一晶粒3的接觸墊31朝上,然後,再透過半導體的圖案化及金屬沉積(例如濺鍍、曝光、顯影、蝕刻)等製程,於該印刷電路基板2及第一晶粒3上方形成該重新布線層6,從而使該重新布線層6可將第一晶粒3的接觸墊31與印刷電路基板2下表
面的導電墊23連接起來,而如第四圖所示,實務上,該重新布線層6所使用的半導體製程其線寬大約在5~20μm(微米)的等級,同時,大約只須用到三、四道光罩即可完成;複數個外部連接元件7,該複數個外部連接元件7係連接於該重新布線層6下方,具體而言,該外部連接元件7可以是焊球(solder ball)或凸塊(solder bump),請再配合參閱第五圖所示,製作時,可透過半導體的植球或凸塊製程(bumping)在如第四圖的重新布線層6上方形成各該外部連接元件7,完成後再翻轉過來即成為如第一圖所示的基本封裝結構1,在一實施例中,該第一晶粒3係為中央處理器(CPU),如此,本創作的第一圖即構成了一種具有創新結構的中央處理器之晶圓級尺寸封裝(Wafer Level Chip Scale Package,WLCSP)。
請參閱第一圖所示,藉由本創作採用具有開口21及相互連接的導電墊22、23的印刷電路基板2,並透過重新布線層6完成位於開口21內的第一晶粒3其接觸墊31與印刷電路基板2下表面的導電墊23之間的電性連接,以實現I/O接點的扇出(I/Opad Fan-Out),而可易於封裝具有較多接點數目的第一晶粒3如CPU,並使本創作的基礎封裝結構1可成為後續進行3D多晶片封裝之核心基礎構造,其中,該印刷電路基板2只需採用現成且等級較低之印刷電路板,且印刷電路板上無須複雜的雷射鑽孔或金屬化製程即可形成貫穿整個封裝的上下互連結構,此外,該重新布線層6亦只需用到相當成熟且精密度較低的半導體製程,從而使本創作可達到簡化製程並降低製造成本之目的。
請再參閱第六圖所示為本創作之第二實施例,其係在如第一
圖之基本封裝結構1的基礎上所完成的3D多晶片模組封裝結構,其中,進一步包含有一多晶片封裝(Multi Chip Package,MCP)結構8,該多晶片封裝結構8係疊設於該印刷電路基板2上方,且該多晶片封裝結構8係與該印刷電路基板2上表面的導電墊22電性連接,一般而言,該多晶片封裝結構8內通常包含有至少兩個以水平放置或垂直堆疊方式設置的第二晶粒81,且該第二晶粒81通常係為低接腳數目(low pin count)的半導體晶粒,例如記憶體晶粒(像是RAM或NAND Flash),此亦為現有的多晶片封裝結構8最廣泛被應用的領域,一般來說,由於第二晶粒81不像CPU具有那麼多的接腳數量,因而該多晶片封裝結構8中的封裝基板83與各第二晶粒81之間只需運用傳統的打線(wire bond)方式來連接,同時,並有一第二封裝體82包覆於第二晶粒81周圍,惟該多晶片封裝結構8的具體細部構造係屬本領域的通常知識且非本案發明點所在,故在此不予詳述,接下來,只需再藉由例如表面黏著技術(SMT)等方式即可將該多晶片封裝結構8的封裝基板83與印刷電路基板2的導電墊22相連接,如第六圖所示,如此即可完成本創作的3D多晶片模組封裝結構,在此,值得注意的是,該第一晶粒3與各第二晶粒81之間的連接即是透過該印刷電路基板2的導電墊22、23以及重新布線層6來實現的,從而證明本創作能夠以較簡單的製程及較低的成本完成3D多晶片的封裝。
請再配合參閱第七圖所示係為本創作之第三實施例,其係本創作在如第一圖之基本封裝結構1的基礎上所完成的另一種3D多晶片模組封裝結構,其係在該基本封裝結構1的第一封裝體5上直接堆疊設置有至少一個第二晶粒81,再利用金屬導線84如金線連接該第二晶粒81與印刷電路基板2上表面的導電墊22,最後,再於印刷電路基板2上方及第二晶粒81周圍設
置有一第二封裝體82,本實施例與第二實施例在製作流程上的差異在於,當完成基本封裝結構1的重新布線層6後,先不植球,然後直接進行該第二晶粒81的堆疊、打線及封模等製程,最後再植球形成該外部連接元件7,本實施例與第二實施例相較,將可具備縮小封裝體積之功效。
1‧‧‧基本封裝結構
2‧‧‧印刷電路基板
22‧‧‧導電墊
23‧‧‧導電墊
24‧‧‧導電柱
3‧‧‧第一晶粒
31‧‧‧接觸墊
5‧‧‧第一封裝體
6‧‧‧重新布線層
7‧‧‧外部連接元件
Claims (6)
- 一種3D多晶片模組封裝結構,其包含:一印刷電路基板(PCB),係設有一開口,該印刷電路基板的上表面與下表面分別設有導電墊,且位於該印刷電路基板上表面的導電墊與位於該印刷電路基板下表面的導電墊相互連接;一第一晶粒,係以令其接觸墊朝下的方式設置於該印刷電路基板的開口內;一第一封裝體,係填設於該印刷電路基板的開口內並包覆該第一晶粒;一重新布線層,係設置於該印刷電路基板與第一晶粒下方,用以使第一晶粒的接觸墊以扇出方式與印刷電路基板下表面的導電墊相連接;複數個外部連接元件,係連接於該重新布線層下方。
- 如申請專利範圍第1項所述之3D多晶片模組封裝結構,其中該第一晶粒為高接腳數目的半導體晶粒。
- 如申請專利範圍第2項所述之3D多晶片模組封裝結構,其中進一步包含有一多晶片封裝結構,該多晶片封裝結構係疊設於該印刷電路基板上方,且該多晶片封裝結構與印刷電路基板上表面的導電墊電性連接。
- 如申請專利範圍第3項所述之3D多晶片模組封裝結構,其中該多晶片封裝結構內設有至少兩個第二晶粒。
- 如申請專利範圍第4項所述之3D多晶片模組封裝結構,其中該第二晶粒為較低接腳數目的半導體晶粒。
- 如申請專利範圍第2項所述之3D多晶片模組封裝結構,其中該第一封裝體上堆疊設置有至少一個第二晶粒,且各該第二晶粒為低接腳數目的半導體晶粒,各該第二晶粒分別透過金屬導線與印刷電路基板上表面的導電墊相連接,又該印刷電路基板上方與第二晶粒周圍設置有一第二封裝體。
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