TWI737054B - 半導體結構、封裝結構及形成半導體結構的方法 - Google Patents

半導體結構、封裝結構及形成半導體結構的方法 Download PDF

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TWI737054B
TWI737054B TW108143535A TW108143535A TWI737054B TW I737054 B TWI737054 B TW I737054B TW 108143535 A TW108143535 A TW 108143535A TW 108143535 A TW108143535 A TW 108143535A TW I737054 B TWI737054 B TW I737054B
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layer
pillar portion
width
conductive bumps
integrated circuit
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TW108143535A
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TW202121624A (zh
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張容華
盧思維
施應慶
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台灣積體電路製造股份有限公司
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Abstract

一種半導體結構，包括積體電路晶粒及多個導電凸塊。 積體電路晶粒包括多個凸塊接墊。多個導電凸塊設置在多個凸塊接墊上。多個導電凸塊中的每一者包括設置在多個凸塊接墊中的一者上的第一柱部分及設置在第一柱部分上的第二柱部分。第二柱部分經由第一柱部分電連接到多個凸塊接墊中的一者，其中第一柱部分的第一寬度大於第二柱部分的第二寬度。也提供一種包括上述半導體結構的封裝結構。

Description

半導體結構、封裝結構及形成半導體結構的方 法
本發明實施例是有關於一種半導體結構、封裝結構及形成半導體結構的方法。
由於各種電子組件(即電晶體、二極體、電阻器、電容器等)的積體密度不斷提高，半導體行業已經歷了迅速的成長。在很大程度上，積體密度的此提高是由於最小特徵尺寸的不斷減小，這允許將更多較小的組件整合到給定區域中。這些較小的電子組件也需要比先前封裝體利用更小面積的較小封裝體。用於半導體組件的一些較小類型的封裝體包括四面扁平封裝體(quad flat package，QFP)、引腳柵格陣列(pin grid array，PGA)封裝體、球柵陣列(ball grid array，BGA)封裝體等等。當前，已開發出促進節能及高速計算的基底上晶圓上晶片(Chip-On-Wafer-On-Substrate，CoWoS)封裝技術。在CoWoS封 裝的封裝製程中，積體電路(integrated circuit，IC)晶粒的散熱是一個重要問題。
根據本發明的實施例，一種半導體結構，包括積體電路晶粒及多個導電凸塊。積體電路晶粒包括多個凸塊接墊。多個導電凸塊設置在所述多個凸塊接墊上，所述多個導電凸塊中的每一者分別包括第一柱部分及第二柱部分。第一柱部分設置在所述多個凸塊接墊中的一者上。第二柱部分設置在所述第一柱部分上，所述第二柱部分經由所述第一柱部分電連接到所述多個凸塊接墊中的一者，且所述第一柱部分的第一寬度大於所述第二柱部分的第二寬度。
根據本發明的實施例，一種封裝結構，包括電路基底、半導體結構、記憶體立方體以及絕緣包封體。半導體結構包括積體電路晶粒及多個導電凸塊。積體電路晶粒包括多個凸塊接墊。多個導電凸塊設置在所述多個凸塊接墊上，所述多個導電凸塊中的每一者分別包括設置在所述多個凸塊接墊中的一者上的第一柱部分及設置在所述第一柱部分上的第二柱部分，所述第二柱部分經由所述第一柱部分分別電連接到所述多個凸塊接墊中的一者，所述第一柱部分的第一寬度大於所述第二柱部分的第二寬度，且所述積體電路晶粒設置在所述電路基底上且經由所述多個導電凸塊電連接到所述電路基底。記憶體立方體設置在所述電路基底上 且電連接到所述電路基底。絕緣包封體橫向地包封所述積體電路晶粒及所述記憶體立方體，所述積體電路晶粒的後表面從所述絕緣包封體可觸及地暴露出來。
根據本發明的實施例，一種形成半導體結構的方法，包括：在包括多個凸塊接墊的積體電路晶粒上形成晶種層；在所述晶種層之上形成第一圖案化光阻層，所述第一圖案化光阻層的多個第一開口暴露出所述積體電路晶粒的所述多個凸塊接墊；在由所述第一圖案化光阻層的所述多個第一開口暴露出的所述晶種層的多個部分上形成多個第一柱部分；在所述第一圖案化光阻層上形成第二圖案化光阻層，所述第二圖案化光阻層的多個第二開口暴露出所述多個第一柱部分；以及在由所述第二圖案化光阻層的所述多個第二開口暴露出的所述多個第一柱部分的多個部分上形成多個第二柱部分，其中所述多個第一柱部分的第一寬度大於所述多個第二柱部分的第二寬度。
100:積體電路晶粒
100a、100b:單體化的積體電路晶粒
110:半導體基底
110’:單體化的半導體基底
120:內連結構
120’:單體化的內連結構
130、204:鈍化層
130’:單體化的鈍化層
140、206:凸塊接墊
150、208:後鈍化層
150’:單體化的後鈍化層
160:晶種層
160’:晶種圖案
160a:底部晶種層
160a’:第一晶種圖案
160b:頂部晶種層
160b’:第二晶種圖案
170:導電凸塊
170a:第一柱部分
170b:第二柱部分
170b1、170b2、170b3、170b4、220a、220b、220c:鍍覆層
170b4’:焊接層或接合層
180:介電材料層
180’:單體化的介電材料層
200:中介層晶圓
200’:中介層
202:導電配線
210:晶種圖案
210a:第一晶種圖案
210b:第二晶種圖案
220、320、700:導電凸塊
300:記憶體立方體
310:記憶體晶粒
312:半導體穿孔
400、750:填充底膠材料
500:絕緣包封體
600:配線基底
650:導電端子
H、H3:高度
H1:第一高度
H2:第二高度
P:排列節距
PR1:第一圖案化光阻層
PR2:第二圖案化光阻層
SS:半導體結構
T:厚度
X:區域
W:半導體晶圓
W1:第一寬度
W2:第二寬度
W3:第三寬度
結合附圖閱讀以下詳細說明，能最透徹地理解本發明的各方面。注意，根據行業中的標準慣例，各種特徵未按比例繪製。事實上，為論述的清晰起見，可任意地增大或減小各種特徵的尺寸。
圖1到圖6示意性地說明製作根據本發明的一些實施例的半導體結構的製程流程。
圖7及圖8示意性地說明製作根據本發明的一些實施例的半導體結構的另一製程流程。
圖9到圖11示意性地說明製作根據本發明的一些實施例的封裝結構的製程流程。
圖12示意性地說明圖9所示區域X的放大剖視圖。
以下公開內容提供諸多不同的實施例或實例以實施所提供主題的不同特徵。下文闡述組件及排列的具體實例以使本發明簡潔。當然，這些僅是實例並不旨在進行限制。舉例來說，在以下說明中，第一特徵形成在第二特徵之上或形成在第二特徵上可包括第一特徵與第二特徵形成為直接接觸的實施例，且還可包括額外特徵可形成在第一特徵與第二特徵之間使得第一特徵與第二特徵不可直接接觸的實施例。另外，本發明可在各種實例中重複使用參考編號及/或字母。此重複是出於簡潔及清晰的目的，本質上並不規定所述的各種實施例及/或配置之間的關係。
此外，為便於說明起見，本文中可使用例如“在…下方(beneath)”、“低於(below)”、“下部(lower)”、“在…上方(above)”、“上部(upper)”等空間相對用語來闡述一個元件或特徵與另外的元件或特徵之間的關係，如圖中所說明。除了圖中所繪示的定向之外，空間相對用語旨在囊括器件在使用或操作中的不同定向。可以其他方式對裝置進行定向(旋轉90度或 處於其他定向)，且同樣地可對本文中所使用的空間相對描述符加以相應地解釋。
還可包括其他的特徵及製程。舉例來說，可包括測試結構來輔助對三維(three dimensional，3D)封裝體或三維積體電路(three dimensional integrated circuit，3D-IC)器件進行驗證測試。測試結構可包括例如形成在重佈線層中或形成在基底上的測試接墊，所述測試接墊允許使用探針及/或探針卡等來對3D封裝體或3D-IC進行測試。可對中間結構及最終結構執行驗證測試。另外，本文中所公開的結構及方法可與測試方法結合使用，所述測試方法包括在中間階段驗證出已知良好的晶粒以提高良率且降低成本。
圖1到圖6示意性地說明製作根據本發明的一些實施例的半導體結構的製程流程。
參考圖1，提供包括例如排列成陣列的多個半導體晶粒或積體電路晶粒100的半導體晶圓W。在對半導體晶圓W執行晶圓鋸割製程之前，半導體晶圓W中所包括的積體電路晶粒100彼此實體連接。在一些實施例中，半導體晶圓W包括：半導體基底110；內連結構120，形成在半導體基底110上；鈍化層130，形成在內連結構120上；多個凸塊接墊140，形成在鈍化層130上且電連接到內連結構120；以及後鈍化層150，覆蓋鈍化層130及凸塊接墊140。半導體基底110可以是矽基底，所述矽基底中形成有主動組件(例如，電晶體等)及被動組件(例如，電阻器、電容器、電 感器等)。內連結構120可包括交替堆疊的多個內連配線層及多個介電層。鈍化層130覆蓋內連結構120且包括多個接觸開口，以使得經由鈍化層130的接觸開口暴露出內連結構120的最頂部內連配線層。在一些實施例中，鈍化層130是氧化矽層、氮化矽層、氮氧化矽層或由其他適合的介電材料形成的介電層。凸塊接墊140形成在所述鈍化層130的接觸開口中且經由鈍化層130的接觸開口電連接到內連結構120的最頂部內連配線層。在一些實施例中，凸塊接墊140是鋁接墊、銅接墊或其他適合的金屬接墊。後鈍化層150可包括多個接觸開口，以使得後鈍化層150的接觸開口部分地暴露出凸塊接墊140。在一些實施例中，後鈍化層150是聚醯亞胺(polyimide，PI)層、聚苯並惡唑(polybenzoxazole，PBO)層或由其他適合的聚合物形成的介電層。
如圖1中所示，經由例如濺射(sputtering)製程在後鈍化層150及由後鈍化層150的接觸開口暴露出的凸塊接墊140上形成用於鍍覆的晶種層160。在一些實施例中，晶種層160包括底部晶種層160a，所述底部晶種層160a完全形成在半導體晶圓W之上以覆蓋後鈍化層150及由後鈍化層150的接觸開口暴露出的凸塊接墊140，且晶種層160還可包括形成在底部晶種層160a上的頂部晶種層160b。舉例來說，底部晶種層160a包括濺射鈦層，且頂部晶種層160b包括濺射銅層。在一些實施例中，底部晶種層160a的厚度處於從約0.05微米到約0.1微米的範圍內，而頂部晶種層160b的厚度處於從約0.1微米到約0.5微米的範圍內。
在一些實施例中，晶種層160可包括堆疊在半導體晶圓W之上的多個濺射層。在一些替代實施例中，所述晶種層可包括完全覆蓋半導體晶圓W的單個濺射層。
參考圖2，例如經由旋轉塗布、烘烤(baking)、微影及顯影製程在晶種層160的頂部晶種層160b上形成第一圖案化光阻層PR1。第一圖案化光阻層PR1包括排列成陣列的多個開口，所述多個開口暴露出頂部晶種層160b的與多個凸塊接墊140對應的多個部分。換句話說，第一圖案化光阻層PR1的開口位於凸塊接墊140上方。然後，可將上面形成有第一圖案化光阻層PR1的半導體晶圓W浸沒到鍍覆槽中所含有的鍍覆溶液中，以使得在第一圖案化光阻層PR1的開口中鍍覆上多個第一柱部分170a。第一柱部分170a被鍍覆在頂部晶種層160b的與凸塊接墊140對應的部分上。第一柱部分170a的高度是由第一圖案化光阻層PR1的厚度決定，而第一柱部分170a的寬度是由第一圖案化光阻層PR1的開口決定。將結合圖12詳細地闡述第一柱部分170a的尺寸(例如，高度及寬度)。在一些實施例中，第一柱部分170a是鍍銅柱或其他適合的導電柱。
參考圖3，在晶種層160的頂部晶種層160b上形成第一柱部分170a之後，在第一圖案化光阻層PR1上形成第二圖案化光阻層PR2以部分地覆蓋第一柱部分170a的頂表面。例如經由旋轉塗布、烘烤、微影及顯影製程來形成第二圖案化光阻層PR2。第二圖案化光阻層PR2包括排列成陣列的多個開口，所述多個開口 用於暴露出多個第一柱部分170a的多個頂表面的多個部分。第二圖案化光阻層PR2的開口位於凸塊接墊140上方。在一些實施例中，界定在第二圖案化光阻層PR2中的開口的寬度小於界定在第一圖案化光阻層PR1中的開口的寬度，界定在第二圖案化光阻層PR2中的開口與界定在第一圖案化光阻層PR1中的開口以及第一柱部分170a實質上對齊。
然後，可將上面形成有第一圖案化光阻層PR1、第一柱部分170a及第二圖案化光阻層PR2的半導體晶圓W浸沒到鍍覆槽中所含有的鍍覆溶液中，以使得在界定在第二圖案化光阻層PR2中的開口中鍍覆上多個第二柱部分170b。第二柱部分170b鍍覆且著陸(land)在第一柱部分170a的頂表面上，以使得形成多個導電凸塊170。第二柱部分170b的高度是由第二圖案化光阻層PR2的厚度決定，而第二柱部分170b的寬度是由第二圖案化光阻層PR2的開口決定。將結合圖12更詳細地闡述第二柱部分170b的尺寸(例如，高度及寬度)。
如圖3中所說明，第二柱部分170b的寬度小於第一柱部分170a的寬度，而第二柱部分170b的高度小於第一柱部分170a的高度。多個第二柱部分170b中的每一者可分別與多個第一柱部分170a中的一者實質上對齊。在一些實施例中，第一柱部分170a及第二柱部分170b可以是圓柱形的柱，且多個第二柱部分170b中的每一者同心地堆疊在多個第一柱部分170a中的一者上。
在一些實施例中，第二柱部分170b是包括鍍覆層 170b1、鍍覆層170b2、鍍覆層170b3及鍍覆層170b4的多層柱，其中鍍覆層170b1包括鍍銅層，鍍覆層170b2包括鍍鎳層，鍍覆層170b3包括另一鍍銅層，且鍍覆層170b3包括無鉛(lead-free)焊料層。舉例來說，鍍覆層170b1(例如，鍍銅層)的厚度處於從約10微米到約100微米的範圍內，鍍覆層170b2(例如，鍍鎳層)的厚度處於從約3微米到約10微米的範圍內，鍍覆層170b3(例如，鍍銅層)的厚度處於從約3微米到約10微米的範圍內，且鍍覆層170b4(例如，無鉛焊料層)的厚度處於從約3微米到約30微米的範圍內。
參考圖3及圖4，在形成第一柱部分170a及第二柱部分170b之後，移除第一圖案化光阻層PR1及第二圖案化光阻層PR2，以使得顯露出晶種層160的未被第一柱部分170a覆蓋的部分。在一些實施例中，經由剝離(stripping)製程同時移除第一圖案化光阻層PR1及第二圖案化光阻層PR2。
在一些實施例中，可經由圖2及圖3中所說明的兩步式鍍覆製程形成各自包括第一柱部分170a及第二柱部分170b的導電凸塊170。換句話說，用於形成導電凸塊170的凸塊形成製程(bumping process)是圖2及圖3中所說明的兩步式鍍覆製程。在一些替代實施例中，多個導電凸塊170中的每一者可包括多個堆疊柱部分(例如，三個或更多個堆疊柱部分)，且可經由多步式鍍覆製程來形成所述堆疊柱部分。以三步式鍍覆製程為例，使用第一圖案化光阻層在圖2中所說明的晶種層160上選擇性地鍍覆 多個第一柱部分，然後使用第二圖案化光阻層在第一柱部分上選擇性地鍍覆多個第二柱部分，並使用第三圖案化光阻層在第二柱部分上選擇性地鍍覆多個第三柱部分。然後，可經由剝離製程同時移除第一圖案化光阻層、第二圖案化光阻層及第三圖案化光阻層。
參考圖4及圖5，使用第一柱部分170a及第二柱部分170b作為硬罩幕，例如經由刻蝕製程移除晶種層160的未被第一柱部分170a及第二柱部分170b覆蓋的部分，直到顯露出後鈍化層150為止。在移除晶種層160的未被第一柱部分170a及第二柱部分170b覆蓋的部分之後，形成多個晶種圖案160’，其中多個晶種圖案160’中的每一者包括第一晶種圖案160a’及第二晶種圖案160b’。第一晶種圖案160a’覆蓋後鈍化層150的一些部分且著陸在凸塊接墊140的中心部分上，而第二晶種圖案160b’位於第一晶種圖案160a’與第一柱部分170a之間。
參考圖5及圖6，在於半導體晶圓W之上執行凸塊形成製程之後，將上面形成有導電凸塊170及晶種圖案160’的半導體晶圓W單體化，以獲得多個單體化的積體電路晶粒100a。在一些實施例中，為了與圖9中所說明的記憶體立方體300的厚度匹配，在將半導體晶圓W單體化之前不需要進行薄化製程來將半導體晶圓W向下薄化。如圖6中所說明，每一單體化的積體電路晶粒100a包括單體化的半導體基底110’、單體化的內連結構120’、單體化的鈍化層130’、凸塊接墊140、單體化的後鈍化層150’、晶種圖 案160’及導電凸塊170。在單體化的積體電路晶粒100a中，單體化的內連結構120’設置在單體化的半導體基底110’上；單體化的鈍化層130’覆蓋單體化的內連結構120’；凸塊接墊140設置在單體化的內連結構120’上且電連接到單體化的內連結構120’；單體化的後鈍化層150’覆蓋單體化的鈍化層130’且覆蓋導電凸塊170的一些部分；且晶種圖案160’及導電凸塊170設置在凸塊接墊140上且電連接到凸塊接墊140。
圖7及圖8示意性地說明製作根據本發明的一些實施例的半導體結構的另一製程流程。
參考圖7，在執行圖5中所說明的凸塊形成製程之後，可在半導體晶圓W的後鈍化層150之上形成介電材料層180。舉例來說，經由先進行施配(dispensing)製程後續接著進行固化製程來形成介電材料層180。在一些實施例中，介電材料層180可橫向地包封晶種圖案160’且沿著導電凸塊170的側壁向上延伸。如圖7中所說明，在一些實施例中，第一柱部分170a的側壁被介電材料層180部分地覆蓋，以使得介電材料層180可增強具有高縱橫比(例如，大於5)的導電凸塊170的可靠性。在一些替代實施例中，介電材料層180可進一步延伸以覆蓋第二柱部分170b的側壁的一些部分。
參考圖7及圖8，在對半導體晶圓W上執行凸塊形成製程之後，將上面形成有晶種圖案160’、導電凸塊170及介電材料層180的半導體晶圓W單體化，以獲得多個單體化的積體電路晶 粒100b。如圖8中所說明，每一單體化的積體電路晶粒100b包括單體化的半導體基底110’、單體化的內連結構120’、單體化的鈍化層130’、凸塊接墊140、單體化的後鈍化層150’、晶種圖案160’、導電凸塊170及單體化的介電材料層180’。在單體化的積體電路晶粒100b中，單體化的內連結構120’設置在單體化的半導體基底110’上；單體化的鈍化層130’覆蓋單體化的內連結構120’；凸塊接墊140設置在單體化的內連結構120’上且電連接到單體化的內連結構120’；單體化的後鈍化層150’覆蓋單體化的鈍化層130’且覆蓋導電凸塊170的一些部分；晶種圖案160’及導電凸塊170設置在凸塊接墊140上且電連接到凸塊接墊140；且單體化的介電材料層180’覆蓋單體化的後鈍化層150’並且與晶種圖案160’及第一柱部分170a的側壁的至少一些部分接觸。在一些實施例中，單體化的介電材料層180’可以是不含填充劑的介電材料。
圖9到圖11示意性地說明製作根據本發明的一些實施例的封裝結構的製程流程。圖12示意性地說明圖9所示區域X的放大剖視圖。
參考圖9，提供上面形成有多個導電凸塊220的中介層(interposer)晶圓200，且將積體電路晶粒拾起並倒裝到中介層晶圓200上。在將積體電路晶粒拾起並倒裝到中介層晶圓200上之後，執行回流製程以將積體電路晶粒接合到中介層晶圓200上。在一些實施例中，將圖8中所說明的單體化的多個積體電路晶粒100b中的一者拾起並放置到中介層晶圓200上，以使得例如經由 回流製程將單體化的積體電路晶粒100b電連接到中介層晶圓200。本申請不限制單體化的積體電路晶粒100b的數目。可將包括具有高縱橫比的導電凸塊的其他類型的積體電路晶粒拾起並放置到中介層晶圓200上。舉例來說，將圖6中所說明的單體化的多個積體電路晶粒100a中的一者拾起並放置到中介層晶圓200上，以使得例如經由回流製程將單體化的積體電路晶粒100a電連接到中介層晶圓200。本申請不限制單體化的積體電路晶粒100a的數目。
在對單體化的積體電路晶粒100b與中介層晶圓200執行接合之後，提供一個或多個記憶體立方體300(例如，高帶寬的記憶體立方體)，並將所述一個或多個記憶體立方體300放置到中介層晶圓200上。在將記憶體立方體300拾起並放置到中介層晶圓200上之後，執行回流製程以將記憶體立方體300接合到中介層晶圓200上。在一些實施例中，多個記憶體立方體300中的每一者包括多個堆疊式記憶體晶粒310(或記憶體積體電路晶片)及導電凸塊320，其中每一記憶體晶粒310中分別形成有多個半導體穿孔(through semiconductor via，TSV)312，且經由導電凸塊320電連接位於堆疊式記憶體晶粒310的不同層級中的半導體穿孔312。在一些其他實施例中，圖9中未說明，多個記憶體立方體中的每一者包括邏輯晶粒(或邏輯積體電路晶片)、設置在所述邏輯晶粒上的多個堆疊式記憶體晶粒及導電凸塊，其中邏輯晶粒及記憶體晶粒中的每一者中分別形成有多個半導體穿孔，邏輯晶粒經 由導電凸塊電連接到記憶體晶粒的最底部層級，且經由導電凸塊電連接位於堆疊式記憶體晶粒的不同層級中的半導體穿孔。在一些替代實施例中，圖9中未說明，多個記憶體立方體中的每一者包括邏輯晶粒、設置在所述邏輯晶粒上的多個堆疊式記憶體晶粒、導電凸塊及絕緣包封體(例如，模塑化合物)，其中邏輯晶粒及記憶體晶粒中的每一者中分別形成有多個半導體穿孔，邏輯晶粒經由導電凸塊電連接到記憶體晶粒的最底部層級，經由導電凸塊電連接位於堆疊式記憶體晶粒的不同層級中的半導體穿孔，且絕緣包封體包封邏輯晶粒及堆疊式記憶體晶粒。記憶體立方體300的配置僅是為了進行說明，本申請並不限制。
在一些實施例中，記憶體立方體300包括八個以上記憶體(例如，每一記憶體立方體300中包括9到12個堆疊式記憶體晶粒)，且記憶體立方體300的總厚度處於約875微米到約925微米的範圍內，其中每一記憶體晶粒310的厚度處於約20微米到約200微米的範圍內，且導電凸塊320的凸塊高度處於從約20微米到約80微米的範圍內。
如圖9及圖12中所說明，在執行回流製程之後，經由導電凸塊170及導電凸塊220將單體化的積體電路晶粒100b實體連接且電連接到中介層晶圓200。如圖12中所說明，中介層晶圓200包括多個導電配線202、鈍化層204、多個凸塊接墊206及後鈍化層208。鈍化層204包括用於暴露出導電配線202的一些部分的多個接觸開口。在一些實施例中，鈍化層204是氧化矽層、氮化矽 層、氮氧化矽層或由其他適合的介電材料形成的介電層。凸塊接墊206形成在鈍化層204及導電配線202的暴露部分上，以使得凸塊接墊206經由鈍化層204中的接觸開口電連接到導電配線202。後鈍化層208可包括多個接觸開口，以使得後鈍化層208的所述接觸開口部分地暴露出凸塊接墊206。舉例來說，後鈍化層208是聚醯亞胺(PI)層、聚苯並惡唑(PBO)層或由其他適合的聚合物形成的介電層。
如圖12所說明，形成各自包括多個堆疊晶種圖案的多個晶種圖案210以覆蓋暴露的凸塊接墊206且覆蓋後鈍化層208的一些部分。在一些實施例中，每一晶種圖案包括第一晶種圖案210a及第二晶種圖案210b，其中第一晶種圖案210a覆蓋暴露的凸塊接墊206且覆蓋後鈍化層208的一些部分，且第二晶種圖案210b設置在第一晶種圖案210a上。舉例來說，第一晶種層(第一晶種圖案210a)包括濺射鈦層，且第二晶種層(第二晶種圖案210b)包括濺射銅層。在一些實施例中，第一晶種層(第一晶種圖案210a)的厚度處於從約0.05微米到約0.1微米的範圍內，而第二晶種層(第二晶種圖案210b)的厚度處於從約0.1微米到約0.5微米的範圍內。此外，經由例如鍍覆製程在晶種圖案210上形成多個導電凸塊220。在一些實施例中，導電凸塊220是多層柱，所述多層柱各自包括鍍覆層220a、鍍覆層220b及鍍覆層220c，其中鍍覆層220a包括鍍銅層，鍍覆層220b包括鍍鎳層，且鍍覆層220c包括另一鍍銅層。在一些實施例中，多個導電凸塊220中的每一者還 包括設置在鍍覆層220c上的無鉛焊料層。舉例來說，鍍覆層220a(例如，鍍銅層)的厚度處於從約3微米到約20微米的範圍內，鍍覆層220b(例如，鍍鎳層)的厚度處於從約3微米到約10微米的範圍內，鍍覆層220c(例如，鍍銅層)的厚度處於從約3微米到約10微米的範圍內，且無鉛焊料層的厚度處於從約3微米到約20微米的範圍內。
如圖12中所說明，在執行回流製程之後，將導電凸塊170的鍍覆層170b4(例如，圖3中所說明的無鉛焊料層)及導電凸塊220的無鉛焊料層熔融並重塑，以在鍍覆層170b3與鍍覆層220c之間形成焊接層或接合層170b4’。
在一些實施例中，第一柱部分170a的第一寬度W1對導電凸塊170的排列節距P(如圖9中所說明)的比率處於從約0.7到約0.8的範圍內。舉例來說，導電凸塊170的排列節距P處於從約10微米到約100微米的範圍內，第一柱部分170a的第一寬度W1處於從約5微米到約80微米的範圍內，第一柱部分170a的第一高度H1處於從約30微米到約300微米的範圍內，且第一柱部分170a的縱橫比處於從約0.5到約8的範圍內。
在一些實施例中，第二柱部分170b的第二寬度W2對導電凸塊170的排列節距P(如圖9中所說明)的比率處於從約0.4到約0.6的範圍內。舉例來說，導電凸塊170的排列節距P處於從約10微米到約100微米的範圍內，且第二柱部分170b的第二寬度W2處於從約3微米到約70微米的範圍內，第二柱部分170b 的第二高度H2處於從約10微米到約100微米的範圍內，且第二柱部分170b的縱橫比處於從約0.5到約8的範圍內。
在一些實施例中，第一柱部分170a的第一寬度W1大於第二柱部分170b的第二寬度W2。舉例來說，第二柱部分170b的第二寬度W2對第一柱部分170a的第一寬度W1的比率大於約0.5且小於約1。
在一些實施例中，第一柱部分170a的第一高度H1實質上等於或大於第二柱部分170b的第二高度H2。舉例來說，第一柱部分170a的第一高度H1對第二柱部分170b的第二高度H2的比率處於從約1到約5的範圍內。
在一些實施例中，導電凸塊170的高度H處於從約20微米到約400微米的範圍內，且積體電路晶粒100b的厚度T處於從約300微米到約800微米的範圍內。舉例來說，導電凸塊170的高度H對積體電路晶粒100b的厚度T的比率處於從約0.05到約1的範圍內。
在一些實施例中，導電凸塊170的高度H對第一柱部分170a的第一寬度W1的比率(即，導電凸塊170的縱橫比)處於從約2到約10的範圍內。
在一些實施例中，導電凸塊170的第二柱部分170b的第二寬度W2小於導電凸塊220的第三寬度W3，而導電凸塊220的第三寬度W3實質上等於第一柱部分170a的第一寬度W1。舉例來說，導電凸塊220的第三寬度W3處於從約3微米到約70微米 的範圍內，導電凸塊220的高度H3處於從約5微米到約30微米的範圍內，且導電凸塊220的縱橫比處於從約0.5到約5的範圍內。此外，導電凸塊170的高度H大於導電凸塊220的高度H3。
在一些實施例中，圖12中未說明，導電凸塊170的第二柱部分170b的第二寬度W2小於導電凸塊220的第三寬度W3，而導電凸塊220的第三寬度W3大於或小於第一柱部分170a的第一寬度W1。
如圖12中所說明，導電凸塊170的高度H可以是每一記憶體晶粒310的厚度的約1/2到約10倍。此外，導電凸塊170的高度H與導電凸塊220的高度H3的總和可以是每一記憶體晶粒310的厚度的約1/10到約3倍。舉例來說，每一記憶體晶粒310的厚度處於從約20微米到約200微米的範圍內。
參考圖10，在將記憶體立方體300及單體化的積體電路晶粒100b接合到中介層晶圓200上之後，經由例如施配製程在中介層晶圓200之上形成填充底膠材料400。形成填充底膠材料400以包封導電凸塊170、導電凸塊220。在一些實施例中，填充底膠材料400不僅填充單體化的積體電路晶粒100b與中介層晶圓200之間的間隔，而且橫向地包封單體化的積體電路晶粒100b的側壁及記憶體立方體300的側壁。根據施配量，填充底膠材料400可部分地填充或完全填充單體化的積體電路晶粒100b與記憶體立方體300之間的間隙。
在於中介層晶圓200之上形成填充底膠400之後，形成 絕緣包封體500以橫向地包封單體化的積體電路晶粒100b及記憶體立方體300，以使得從絕緣包封體500可觸及地(accessibly)暴露出積體電路晶粒100b的後表面。在形成絕緣包封體500之後，在中介層晶圓200的下表面上形成多個導電凸塊700(例如，受控塌陷晶片連接(C4)凸塊)，以使得導電凸塊700經由中介層晶圓200電連接到單體化的積體電路晶粒100b且電連接到記憶體立方體300。然後，執行單體化製程以獲得多個半導體結構SS。如圖10中所說明，在執行單體化製程之後，實現各自包括積體電路晶粒100b及中介層200’的半導體結構SS的製作。
在一些實施例中，經由進行模塑製程(例如，包覆模塑製程)後續接著進行研磨製程(例如，機械研磨製程及/或化學機械拋光製程)來形成絕緣包封體500。上述研磨製程用於部分地研磨絕緣包封體500的模塑化合物以顯露出積體電路晶粒100b的後表面及記憶體立方體300的一些部分，以使得半導體結構SS的散熱性能可得以增強。
如圖10中所說明，在此實施例中，由於積體電路晶粒100b的厚度以及導電凸塊170及導電凸塊220的縱橫比高到足以與記憶體立方體300的相對高的厚度(例如，約900微米)匹配，因此積體電路晶粒100b的後表面不會被絕緣包封體500覆蓋且從絕緣包封體500可觸及地暴露出來。因此，圖10中所說明的半導體結構SS的散熱性能得以增強。
參考圖11，將半導體結構SS拾起並放置到包括多個導電 端子650(例如，焊球)的配線基底600(例如，印刷電路板)上。在一些實施例中，半導體結構SS安裝在配線基底600的上表面上，且導電端子650設置在配線基底600的下表面上。在一些實施例中，填充底膠材料750形成在配線基底600的上表面上以填充中介層200’與配線基底600之間的間隙。填充底膠材料750包封導電凸塊700且增強圖11中所說明的封裝結構的可靠性。
根據本發明的一些實施例，提供一種包括積體電路晶粒及多個導電凸塊的半導體結構。所述積體電路晶粒包括多個凸塊接墊。所述多個導電凸塊設置在所述多個凸塊接墊上。所述多個導電凸塊中的每一者分別包括設置在所述多個凸塊接墊中的一者上的第一柱部分及設置在所述第一柱部分上的第二柱部分。所述第二柱部分經由所述第一柱部分電連接到所述多個凸塊接墊中的一者，其中所述第一柱部分的第一寬度大於所述第二柱部分的第二寬度。在實施例中，所述多個導電凸塊的高度對所述積體電路晶粒的厚度的比率處於從約0.05到約1的範圍內。在實施例中，所述多個導電凸塊排列成陣列，所述第一寬度對所述多個導電凸塊的排列節距的第一比率處於從約0.7到約0.8的範圍內，且所述第二寬度對所述多個導電凸塊的所述排列節距的第二比率處於從約0.4到約0.6的範圍內。在實施例中，所述第一柱部分的第一高度對所述第二柱部分的第二高度的比率處於從約1到約5的範圍內。在實施例中，所述第二寬度對所述第一寬度的比率大於約0.5且小於約1。在實施例中，所述多個導電凸塊的高度對所述第一寬 度的比率處於從約2到約10的範圍內。在實施例中，半導體結構還包括部分地包封所述多個導電凸塊的多個側壁的介電層。
根據本發明的一些實施例，提供一種包括電路基底、半導體結構、記憶體立方體及絕緣包封體的封裝結構。所述半導體結構包括：積體電路晶粒，包括多個凸塊接墊；及多個導電凸塊，設置在所述多個凸塊接墊上。所述多個導電凸塊中的每一者分別包括設置在所述多個凸塊接墊中的一者上的第一柱部分及設置在所述第一柱部分上的第二柱部分。所述第二柱部分經由所述第一柱部分分別電連接到所述多個凸塊接墊中的一者。所述第一柱部分的第一寬度大於所述第二柱部分的第二寬度。所述積體電路晶粒設置在所述電路基底上且經由所述多個導電凸塊電連接到所述電路基底。所述記憶體立方體設置在所述電路基底上且電連接到所述電路基底。所述絕緣包封體橫向地包封所述積體電路晶粒及所述記憶體立方體，且所述積體電路的後表面從所述絕緣包封體可觸及地暴露出來。在實施例中，所述多個導電凸塊的高度對所述積體電路晶粒的厚度的比率處於從約0.05到約1的範圍內。在實施例中，所述多個導電凸塊排列成陣列，所述第一寬度對所述多個導電凸塊的排列節距的第一比率處於從約0.7到約0.8的範圍內，且所述第二寬度對所述多個導電凸塊的所述排列節距的第二比率處於從約0.4到約0.6的範圍內。在實施例中，所述第一柱部分的第一高度對所述第二柱部分的第二高度的比率處於從約1到約5的範圍內。在實施例中，所述第二寬度對所述第一寬度的比 率大於約0.5且小於約1。在實施例中，所述多個導電凸塊的高度對所述第一寬度的比率處於從約2到約10的範圍內。在實施例中，封裝結構還包括部分地包封所述多個導電凸塊的多個側壁的介電層。
根據本發明的一些實施例，提供一種形成半導體結構的方法，包括：在包括多個凸塊接墊的積體電路晶粒上形成晶種層；在所述晶種層之上形成第一圖案化光阻層，所述第一圖案化光阻層的多個第一開口暴露出所述積體電路晶粒的所述多個凸塊接墊；在由所述第一圖案化光阻層的所述多個第一開口暴露出的所述晶種層的多個部分上形成多個第一柱部分；在所述第一圖案化光阻層上形成第二圖案化光阻層，所述第二圖案化光阻層的多個第二開口暴露出所述多個第一柱部分；以及在由所述第二圖案化光阻層的所述多個第二開口暴露出的所述多個第一柱部分的多個部分上形成多個第二柱部分，其中所述多個第一柱部分的第一寬度大於所述多個第二柱部分的第二寬度。在實施例中，將所述晶種層濺射在所述積體電路晶粒上以覆蓋所述多個凸塊接墊。在實施例中，形成在所述晶種層之上的所述第一圖案化光阻層比所述第二圖案化光阻層厚。在實施例中，所述第二圖案化光阻層形成為覆蓋所述第一圖案化光阻層且覆蓋所述多個第一柱部分的多個頂表面的部分。在實施例中，所述的方法還包括：形成介電層，所述介電層覆蓋所述積體電路晶粒且部分地包封所述多個第一柱部分的多個側壁。在實施例中，所述介電層是經由先進行施配製 程後續接著進行固化製程而形成。
根據本發明的一些實施例，提供一種包括中介層基底、半導體結構、記憶體立方體及絕緣包封體的封裝結構。所述中介層基底包括多個第一導電凸塊。所述半導體結構包括：積體電路晶粒，包括多個凸塊接墊；及多個第二導電凸塊，設置在所述多個凸塊接墊上。所述多個第二導電凸塊中的每一者分別包括設置在所述多個凸塊接墊中的一者上的第一柱部分及設置在所述第一柱部分上的第二柱部分。所述第二柱部分位於所述第一柱部分與所述多個第一導電凸塊中的一者之間。所述第一柱部分的第一寬度大於所述第二柱部分的第二寬度。所述積體電路晶粒設置在所述中介層基底上且經由所述多個第一導電凸塊及所述多個第二導電凸塊電連接到所述中介層基底。所述記憶體立方體設置在所述中介層基底上且電連接到所述中介層基底。所述絕緣包封體橫向地包封所述積體電路晶粒及所述記憶體立方體，且所述積體電路晶粒的後表面從所述絕緣包封體可觸及地暴露出來。
上述內容概述了數個實施例的特徵，以使所屬領域的技術人員可更好地理解本發明的各方面。所屬領域的技術人員應瞭解，其可容易地使用本發明作為設計或修改其他製程及結構以實現與本文中所介紹的實施例相同的目的及/或達成相同的優勢的基礎。所屬領域的技術人員還應意識到這些等效構造並不背離本發明的精神及範圍，且其可在不背離本發明的精神及範圍的情況下在本文中做出各種變化、替代及更改。
100a:單體化的積體電路晶粒
110’:單體化的半導體基底
120’:單體化的內連結構
130’:單體化的鈍化層
140:凸塊接墊
150’:單體化的後鈍化層
160’:晶種圖案
160a’:第一晶種圖案
160b’:第二晶種圖案
170:導電凸塊
170a:第一柱部分
170b:第二柱部分

Claims (10)

  1. 一種半導體結構，包括：積體電路晶粒，包括多個凸塊接墊；多個導電凸塊，設置在所述多個凸塊接墊上，所述多個導電凸塊中的每一者分別包括：第一柱部分，設置在所述多個凸塊接墊中的一者上；及第二柱部分，設置在所述第一柱部分上，所述第二柱部分經由所述第一柱部分電連接到所述多個凸塊接墊中的一者，且所述第一柱部分的第一寬度大於所述第二柱部分的第二寬度，其中所述多個導電凸塊排列成陣列，所述第一寬度對所述多個導電凸塊的排列節距的第一比率處於從約0.7到約0.8的範圍內，且所述第二寬度對所述多個導電凸塊的所述排列節距的第二比率處於從約0.4到約0.6的範圍內。
  2. 如申請專利範圍第1項所述的半導體結構，其中所述多個導電凸塊的高度對所述積體電路晶粒的厚度的比率處於從約0.05到約1的範圍內。
  3. 如申請專利範圍第1項所述的半導體結構，其中所述多個導電凸塊的高度對所述第一寬度的比率處於從約2到約10的範圍內。
  4. 如申請專利範圍第1項所述的半導體結構，其中所述第一柱部分的第一高度對所述第二柱部分的第二高度的比率處於從約1到約5的範圍內。
  5. 如申請專利範圍第1項所述的半導體結構，其中所述第二寬度對所述第一寬度的比率大於約0.5且小於約1。
  6. 如申請專利範圍第1項所述的半導體結構，還包括部分地包封所述多個導電凸塊的多個側壁的介電層。
  7. 一種封裝結構，包括：電路基底；半導體結構，包括：積體電路晶粒，包括多個凸塊接墊；及設置在所述多個凸塊接墊上的多個導電凸塊，所述多個導電凸塊中的每一者分別包括設置在所述多個凸塊接墊中的一者上的第一柱部分及設置在所述第一柱部分上的第二柱部分，所述第二柱部分經由所述第一柱部分分別電連接到所述多個凸塊接墊中的一者，所述第一柱部分的第一寬度大於所述第二柱部分的第二寬度，且所述積體電路晶粒設置在所述電路基底上且經由所述多個導電凸塊電連接到所述電路基底；記憶體立方體，設置在所述電路基底上且電連接到所述電路基底；以及絕緣包封體，橫向地包封所述積體電路晶粒及所述記憶體立方體，所述積體電路晶粒的後表面從所述絕緣包封體可觸及地暴露出來。
  8. 一種形成半導體結構的方法，包括：在包括多個凸塊接墊的積體電路晶粒上形成晶種層；在所述晶種層之上形成第一圖案化光阻層，所述第一圖案化光阻層的多個第一開口暴露出所述積體電路晶粒的所述多個凸塊接墊；在由所述第一圖案化光阻層的所述多個第一開口暴露出的所述晶種層的多個部分上形成多個第一柱部分；在所述第一圖案化光阻層上形成第二圖案化光阻層，所述第二圖案化光阻層的多個第二開口暴露出所述多個第一柱部分；以及在由所述第二圖案化光阻層的所述多個第二開口暴露出的所述多個第一柱部分的多個部分上形成多個第二柱部分，其中所述多個第一柱部分的第一寬度大於所述多個第二柱部分的第二寬度。
  9. 如申請專利範圍第8項所述的方法，其中形成在所述晶種層之上的所述第一圖案化光阻層比所述第二圖案化光阻層厚。
  10. 如申請專利範圍第8項所述的方法，其中所述第二圖案化光阻層形成為覆蓋所述第一圖案化光阻層且覆蓋所述多個第一柱部分的多個頂表面的部分。
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